-2

Documentation/devicetree/bindings/clock/keystone-gate.txt

reviewed

··· 1 1 - Status: Unstable - ABI compatibility may be broken in the future 2 2 - 3 1 Binding for Keystone gate control driver which uses PSC controller IP. 4 2 5 3 This binding uses the common clock binding[1].

-2

Documentation/devicetree/bindings/clock/keystone-pll.txt

reviewed

··· 1 1 - Status: Unstable - ABI compatibility may be broken in the future 2 2 - 3 1 Binding for keystone PLLs. The main PLL IP typically has a multiplier, 4 2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL 5 3 and PAPLL are controlled by the memory mapped register where as the Main

-2

Documentation/devicetree/bindings/clock/ti/adpll.txt

reviewed

··· 1 1 Binding for Texas Instruments ADPLL clock. 2 2 3 3 - Binding status: Unstable - ABI compatibility may be broken in the future 4 4 - 5 3 This binding uses the common clock binding[1]. It assumes a 6 4 register-mapped ADPLL with two to three selectable input clocks 7 5 and three to four children.

-2

Documentation/devicetree/bindings/clock/ti/apll.txt

reviewed

··· 1 1 Binding for Texas Instruments APLL clock. 2 2 3 3 - Binding status: Unstable - ABI compatibility may be broken in the future 4 4 - 5 3 This binding uses the common clock binding[1]. It assumes a 6 4 register-mapped APLL with usually two selectable input clocks 7 5 (reference clock and bypass clock), with analog phase locked

-2

Documentation/devicetree/bindings/clock/ti/autoidle.txt

reviewed

··· 1 1 Binding for Texas Instruments autoidle clock. 2 2 3 3 - Binding status: Unstable - ABI compatibility may be broken in the future 4 4 - 5 3 This binding uses the common clock binding[1]. It assumes a register mapped 6 4 clock which can be put to idle automatically by hardware based on the usage 7 5 and a configuration bit setting. Autoidle clock is never an individual

-2

Documentation/devicetree/bindings/clock/ti/clockdomain.txt

reviewed

··· 1 1 Binding for Texas Instruments clockdomain. 2 2 3 3 - Binding status: Unstable - ABI compatibility may be broken in the future 4 4 - 5 3 This binding uses the common clock binding[1] in consumer role. 6 4 Every clock on TI SoC belongs to one clockdomain, but software 7 5 only needs this information for specific clocks which require

-2

Documentation/devicetree/bindings/clock/ti/composite.txt

reviewed

··· 1 1 Binding for TI composite clock. 2 2 3 3 - Binding status: Unstable - ABI compatibility may be broken in the future 4 4 - 5 3 This binding uses the common clock binding[1]. It assumes a 6 4 register-mapped composite clock with multiple different sub-types; 7 5

-2

Documentation/devicetree/bindings/clock/ti/divider.txt

reviewed

··· 1 1 Binding for TI divider clock 2 2 3 3 - Binding status: Unstable - ABI compatibility may be broken in the future 4 4 - 5 3 This binding uses the common clock binding[1]. It assumes a 6 4 register-mapped adjustable clock rate divider that does not gate and has 7 5 only one input clock or parent. By default the value programmed into

-2

Documentation/devicetree/bindings/clock/ti/dpll.txt

reviewed

··· 1 1 Binding for Texas Instruments DPLL clock. 2 2 3 3 - Binding status: Unstable - ABI compatibility may be broken in the future 4 4 - 5 3 This binding uses the common clock binding[1]. It assumes a 6 4 register-mapped DPLL with usually two selectable input clocks 7 5 (reference clock and bypass clock), with digital phase locked

-2

Documentation/devicetree/bindings/clock/ti/fapll.txt

reviewed

··· 1 1 Binding for Texas Instruments FAPLL clock. 2 2 3 3 - Binding status: Unstable - ABI compatibility may be broken in the future 4 4 - 5 3 This binding uses the common clock binding[1]. It assumes a 6 4 register-mapped FAPLL with usually two selectable input clocks 7 5 (reference clock and bypass clock), and one or more child

-2

Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt

reviewed

··· 1 1 Binding for TI fixed factor rate clock sources. 2 2 3 3 - Binding status: Unstable - ABI compatibility may be broken in the future 4 4 - 5 3 This binding uses the common clock binding[1], and also uses the autoidle 6 4 support from TI autoidle clock [2]. 7 5

-2

Documentation/devicetree/bindings/clock/ti/gate.txt

reviewed

··· 1 1 Binding for Texas Instruments gate clock. 2 2 3 3 - Binding status: Unstable - ABI compatibility may be broken in the future 4 4 - 5 3 This binding uses the common clock binding[1]. This clock is 6 4 quite much similar to the basic gate-clock [2], however, 7 5 it supports a number of additional features. If no register

-2

Documentation/devicetree/bindings/clock/ti/interface.txt

reviewed

··· 1 1 Binding for Texas Instruments interface clock. 2 2 3 3 - Binding status: Unstable - ABI compatibility may be broken in the future 4 4 - 5 3 This binding uses the common clock binding[1]. This clock is 6 4 quite much similar to the basic gate-clock [2], however, 7 5 it supports a number of additional features, including

-2

Documentation/devicetree/bindings/clock/ti/mux.txt

reviewed

··· 1 1 Binding for TI mux clock. 2 2 3 3 - Binding status: Unstable - ABI compatibility may be broken in the future 4 4 - 5 3 This binding uses the common clock binding[1]. It assumes a 6 4 register-mapped multiplexer with multiple input clock signals or 7 5 parents, one of which can be selected as output. This clock does not

+2

Documentation/devicetree/bindings/dts-coding-style.rst

reviewed

··· 144 144 #dma-cells = <1>; 145 145 clocks = <&clock_controller 0>, <&clock_controller 1>; 146 146 clock-names = "bus", "host"; 147 147 + #address-cells = <1>; 148 148 + #size-cells = <1>; 147 149 vendor,custom-property = <2>; 148 150 status = "disabled"; 149 151

-3

Documentation/devicetree/bindings/remoteproc/ti,davinci-rproc.txt

reviewed

··· 1 1 TI Davinci DSP devices 2 2 ======================= 3 3 4 4 - Binding status: Unstable - Subject to changes for DT representation of clocks 5 5 - and resets 6 6 - 7 4 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that 8 5 is used to offload some of the processor-intensive tasks or algorithms, for 9 6 achieving various system level goals.

+1 -1

Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml

reviewed

··· 51 51 ranges: true 52 52 53 53 patternProperties: 54 54 - "^clock-controller@[0-9a-z]+$": 54 54 + "^clock-controller@[0-9a-f]+$": 55 55 $ref: /schemas/clock/fsl,flexspi-clock.yaml# 56 56 57 57 required:

+1 -1

Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-scfg.yaml

reviewed

··· 41 41 ranges: true 42 42 43 43 patternProperties: 44 44 - "^interrupt-controller@[a-z0-9]+$": 44 44 + "^interrupt-controller@[a-f0-9]+$": 45 45 $ref: /schemas/interrupt-controller/fsl,ls-extirq.yaml# 46 46 47 47 required:

+1 -1

Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml

reviewed

··· 60 60 be implemented in an always-on power domain." 61 61 62 62 patternProperties: 63 63 - '^frame@[0-9a-z]*$': 63 63 + '^frame@[0-9a-f]+$': 64 64 type: object 65 65 additionalProperties: false 66 66 description: A timer node has up to 8 frame sub-nodes, each with the following properties.

+34 -4

Documentation/devicetree/bindings/ufs/qcom,ufs.yaml

reviewed

··· 27 27 - qcom,msm8996-ufshc 28 28 - qcom,msm8998-ufshc 29 29 - qcom,sa8775p-ufshc 30 30 + - qcom,sc7180-ufshc 30 31 - qcom,sc7280-ufshc 32 32 + - qcom,sc8180x-ufshc 31 33 - qcom,sc8280xp-ufshc 32 34 - qcom,sdm845-ufshc 33 35 - qcom,sm6115-ufshc 36 36 + - qcom,sm6125-ufshc 34 37 - qcom,sm6350-ufshc 35 38 - qcom,sm8150-ufshc 36 39 - qcom,sm8250-ufshc ··· 45 42 - const: jedec,ufs-2.0 46 43 47 44 clocks: 48 48 - minItems: 8 45 45 + minItems: 7 49 46 maxItems: 11 50 47 51 48 clock-names: 52 52 - minItems: 8 49 49 + minItems: 7 53 50 maxItems: 11 54 51 55 52 dma-coherent: true ··· 120 117 compatible: 121 118 contains: 122 119 enum: 120 120 + - qcom,sc7180-ufshc 121 121 + then: 122 122 + properties: 123 123 + clocks: 124 124 + minItems: 7 125 125 + maxItems: 7 126 126 + clock-names: 127 127 + items: 128 128 + - const: core_clk 129 129 + - const: bus_aggr_clk 130 130 + - const: iface_clk 131 131 + - const: core_clk_unipro 132 132 + - const: ref_clk 133 133 + - const: tx_lane0_sync_clk 134 134 + - const: rx_lane0_sync_clk 135 135 + reg: 136 136 + maxItems: 1 137 137 + reg-names: 138 138 + maxItems: 1 139 139 + 140 140 + - if: 141 141 + properties: 142 142 + compatible: 143 143 + contains: 144 144 + enum: 123 145 - qcom,msm8998-ufshc 124 146 - qcom,sa8775p-ufshc 125 147 - qcom,sc7280-ufshc 148 148 + - qcom,sc8180x-ufshc 126 149 - qcom,sc8280xp-ufshc 127 150 - qcom,sm8250-ufshc 128 151 - qcom,sm8350-ufshc ··· 244 215 contains: 245 216 enum: 246 217 - qcom,sm6115-ufshc 218 218 + - qcom,sm6125-ufshc 247 219 then: 248 220 properties: 249 221 clocks: ··· 278 248 reg: 279 249 maxItems: 1 280 250 clocks: 281 281 - minItems: 8 251 251 + minItems: 7 282 252 maxItems: 8 283 253 else: 284 254 properties: ··· 286 256 minItems: 1 287 257 maxItems: 2 288 258 clocks: 289 289 - minItems: 8 259 259 + minItems: 7 290 260 maxItems: 11 291 261 292 262 unevaluatedProperties: false

+1

MAINTAINERS

reviewed

··· 22430 22430 W: https://kernsec.org/wiki/index.php/Linux_Kernel_Integrity 22431 22431 Q: https://patchwork.kernel.org/project/linux-integrity/list/ 22432 22432 T: git git://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd.git 22433 22433 + F: Documentation/devicetree/bindings/tpm/ 22433 22434 F: drivers/char/tpm/ 22434 22435 22435 22436 TPS546D24 DRIVER

+5 -1

arch/nios2/kernel/prom.c

reviewed

··· 21 21 22 22 void __init early_init_devtree(void *params) 23 23 { 24 24 - __be32 *dtb = (u32 *)__dtb_start; 24 24 + __be32 __maybe_unused *dtb = (u32 *)__dtb_start; 25 25 + 25 26 #if defined(CONFIG_NIOS2_DTB_AT_PHYS_ADDR) 26 27 if (be32_to_cpup((__be32 *)CONFIG_NIOS2_DTB_PHYS_ADDR) == 27 28 OF_DT_HEADER) { ··· 31 30 return; 32 31 } 33 32 #endif 33 33 + 34 34 + #ifdef CONFIG_NIOS2_DTB_SOURCE_BOOL 34 35 if (be32_to_cpu((__be32) *dtb) == OF_DT_HEADER) 35 36 params = (void *)__dtb_start; 37 37 + #endif 36 38 37 39 early_init_dt_scan(params); 38 40 }

+23 -3

drivers/base/core.c

reviewed

··· 44 44 static void __fw_devlink_link_to_consumers(struct device *dev); 45 45 static bool fw_devlink_drv_reg_done; 46 46 static bool fw_devlink_best_effort; 47 47 + static struct workqueue_struct *device_link_wq; 47 48 48 49 /** 49 50 * __fwnode_link_add - Create a link between two fwnode_handles. ··· 534 533 /* 535 534 * It may take a while to complete this work because of the SRCU 536 535 * synchronization in device_link_release_fn() and if the consumer or 537 537 - * supplier devices get deleted when it runs, so put it into the "long" 538 538 - * workqueue. 536 536 + * supplier devices get deleted when it runs, so put it into the 537 537 + * dedicated workqueue. 539 538 */ 540 540 - queue_work(system_long_wq, &link->rm_work); 539 539 + queue_work(device_link_wq, &link->rm_work); 541 540 } 541 541 + 542 542 + /** 543 543 + * device_link_wait_removal - Wait for ongoing devlink removal jobs to terminate 544 544 + */ 545 545 + void device_link_wait_removal(void) 546 546 + { 547 547 + /* 548 548 + * devlink removal jobs are queued in the dedicated work queue. 549 549 + * To be sure that all removal jobs are terminated, ensure that any 550 550 + * scheduled work has run to completion. 551 551 + */ 552 552 + flush_workqueue(device_link_wq); 553 553 + } 554 554 + EXPORT_SYMBOL_GPL(device_link_wait_removal); 542 555 543 556 static struct class devlink_class = { 544 557 .name = "devlink", ··· 4179 4164 sysfs_dev_char_kobj = kobject_create_and_add("char", dev_kobj); 4180 4165 if (!sysfs_dev_char_kobj) 4181 4166 goto char_kobj_err; 4167 4167 + device_link_wq = alloc_workqueue("device_link_wq", 0, 0); 4168 4168 + if (!device_link_wq) 4169 4169 + goto wq_err; 4182 4170 4183 4171 return 0; 4184 4172 4173 4173 + wq_err: 4174 4174 + kobject_put(sysfs_dev_char_kobj); 4185 4175 char_kobj_err: 4186 4176 kobject_put(sysfs_dev_block_kobj); 4187 4177 block_kobj_err:

+12

drivers/of/dynamic.c

reviewed

··· 9 9 10 10 #define pr_fmt(fmt) "OF: " fmt 11 11 12 12 + #include <linux/device.h> 12 13 #include <linux/of.h> 13 14 #include <linux/spinlock.h> 14 15 #include <linux/slab.h> ··· 667 666 void of_changeset_destroy(struct of_changeset *ocs) 668 667 { 669 668 struct of_changeset_entry *ce, *cen; 669 669 + 670 670 + /* 671 671 + * When a device is deleted, the device links to/from it are also queued 672 672 + * for deletion. Until these device links are freed, the devices 673 673 + * themselves aren't freed. If the device being deleted is due to an 674 674 + * overlay change, this device might be holding a reference to a device 675 675 + * node that will be freed. So, wait until all already pending device 676 676 + * links are deleted before freeing a device node. This ensures we don't 677 677 + * free any device node that has a non-zero reference count. 678 678 + */ 679 679 + device_link_wait_removal(); 670 680 671 681 list_for_each_entry_safe_reverse(ce, cen, &ocs->entries, node) 672 682 __of_changeset_entry_destroy(ce);

+8

drivers/of/module.c

reviewed

··· 16 16 ssize_t csize; 17 17 ssize_t tsize; 18 18 19 19 + /* 20 20 + * Prevent a kernel oops in vsnprintf() -- it only allows passing a 21 21 + * NULL ptr when the length is also 0. Also filter out the negative 22 22 + * lengths... 23 23 + */ 24 24 + if ((len > 0 && !str) || len < 0) 25 25 + return -EINVAL; 26 26 + 19 27 /* Name & Type */ 20 28 /* %p eats all alphanum characters, so %c must be used here */ 21 29 csize = snprintf(str, len, "of:N%pOFn%c%s", np, 'T',

+1

include/linux/device.h

reviewed

··· 1247 1247 void device_link_remove(void *consumer, struct device *supplier); 1248 1248 void device_links_supplier_sync_state_pause(void); 1249 1249 void device_links_supplier_sync_state_resume(void); 1250 1250 + void device_link_wait_removal(void); 1250 1251 1251 1252 /* Create alias, so I can be autoloaded. */ 1252 1253 #define MODULE_ALIAS_CHARDEV(major,minor) \