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dt-bindings: pinctrl: qcom,glymur-tlmm: Document Mahua TLMM block

Document the pinctrl compatible for the Mahua SoC, a 12-core variant
of Glymur. The PDC wake IRQ map differs since PDC handles the interrupt
for GPIO 155 instead of GPIO 143 as seen on Glymur.

Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>

authored by

Gopikrishna Garmidi and committed by
Linus Walleij 84a3bc33 450e2487

+4 -2
+4 -2
Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml
··· 10 10 - Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> 11 11 12 12 description: 13 - Top Level Mode Multiplexer pin controller in Qualcomm Glymur SoC. 13 + Top Level Mode Multiplexer pin controller in Qualcomm Glymur and Mahua SoC. 14 14 15 15 allOf: 16 16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 17 17 18 18 properties: 19 19 compatible: 20 - const: qcom,glymur-tlmm 20 + enum: 21 + - qcom,glymur-tlmm 22 + - qcom,mahua-tlmm 21 23 22 24 reg: 23 25 maxItems: 1