Merge tag 'spi-for-linus' of git://git.secretlab.ca/git/linux-2.6

+1 -1

drivers/spi/Kconfig

··· 74 74 This selects a driver for the Atmel SPI Controller, present on 75 75 many AT32 (AVR32) and AT91 (ARM) chips. 76 76 77 - config SPI_BFIN 77 + config SPI_BFIN5XX 78 78 tristate "SPI controller driver for ADI Blackfin5xx" 79 79 depends on BLACKFIN 80 80 help

+1 -1

drivers/spi/Makefile

··· 15 15 obj-$(CONFIG_SPI_ATH79) += spi-ath79.o 16 16 obj-$(CONFIG_SPI_AU1550) += spi-au1550.o 17 17 obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o 18 - obj-$(CONFIG_SPI_BFIN) += spi-bfin5xx.o 18 + obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o 19 19 obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o 20 20 obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o 21 21 obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o

+93 -72

drivers/spi/spi-bcm63xx.c

··· 1 1 /* 2 2 * Broadcom BCM63xx SPI controller support 3 3 * 4 - * Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org> 4 + * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org> 5 5 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com> 6 6 * 7 7 * This program is free software; you can redistribute it and/or ··· 30 30 #include <linux/spi/spi.h> 31 31 #include <linux/completion.h> 32 32 #include <linux/err.h> 33 + #include <linux/workqueue.h> 34 + #include <linux/pm_runtime.h> 33 35 34 36 #include <bcm63xx_dev_spi.h> 35 37 ··· 39 37 #define DRV_VER "0.1.2" 40 38 41 39 struct bcm63xx_spi { 42 - spinlock_t lock; 43 - int stopping; 44 40 struct completion done; 45 41 46 42 void __iomem *regs; ··· 96 96 { 391000, SPI_CLK_0_391MHZ } 97 97 }; 98 98 99 - static int bcm63xx_spi_setup_transfer(struct spi_device *spi, 100 - struct spi_transfer *t) 99 + static int bcm63xx_spi_check_transfer(struct spi_device *spi, 100 + struct spi_transfer *t) 101 101 { 102 - struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); 103 102 u8 bits_per_word; 104 - u8 clk_cfg, reg; 105 - u32 hz; 106 - int i; 107 103 108 104 bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word; 109 - hz = (t) ? t->speed_hz : spi->max_speed_hz; 110 105 if (bits_per_word != 8) { 111 106 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", 112 107 __func__, bits_per_word); ··· 113 118 __func__, spi->chip_select); 114 119 return -EINVAL; 115 120 } 121 + 122 + return 0; 123 + } 124 + 125 + static void bcm63xx_spi_setup_transfer(struct spi_device *spi, 126 + struct spi_transfer *t) 127 + { 128 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); 129 + u32 hz; 130 + u8 clk_cfg, reg; 131 + int i; 132 + 133 + hz = (t) ? t->speed_hz : spi->max_speed_hz; 116 134 117 135 /* Find the closest clock configuration */ 118 136 for (i = 0; i < SPI_CLK_MASK; i++) { ··· 147 139 bcm_spi_writeb(bs, reg, SPI_CLK_CFG); 148 140 dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", 149 141 clk_cfg, hz); 150 - 151 - return 0; 152 142 } 153 143 154 144 /* the spi->mode bits understood by this driver: */ ··· 159 153 160 154 bs = spi_master_get_devdata(spi->master); 161 155 162 - if (bs->stopping) 163 - return -ESHUTDOWN; 164 - 165 156 if (!spi->bits_per_word) 166 157 spi->bits_per_word = 8; 167 158 ··· 168 165 return -EINVAL; 169 166 } 170 167 171 - ret = bcm63xx_spi_setup_transfer(spi, NULL); 168 + ret = bcm63xx_spi_check_transfer(spi, NULL); 172 169 if (ret < 0) { 173 170 dev_err(&spi->dev, "setup: unsupported mode bits %x\n", 174 171 spi->mode & ~MODEBITS); ··· 193 190 bs->remaining_bytes -= size; 194 191 } 195 192 196 - static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) 193 + static unsigned int bcm63xx_txrx_bufs(struct spi_device *spi, 194 + struct spi_transfer *t) 197 195 { 198 196 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); 199 197 u16 msg_ctl; 200 198 u16 cmd; 199 + 200 + /* Disable the CMD_DONE interrupt */ 201 + bcm_spi_writeb(bs, 0, SPI_INT_MASK); 201 202 202 203 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", 203 204 t->tx_buf, t->rx_buf, t->len); ··· 209 202 /* Transmitter is inhibited */ 210 203 bs->tx_ptr = t->tx_buf; 211 204 bs->rx_ptr = t->rx_buf; 212 - init_completion(&bs->done); 213 205 214 206 if (t->tx_buf) { 215 207 bs->remaining_bytes = t->len; 216 208 bcm63xx_spi_fill_tx_fifo(bs); 217 209 } 218 210 219 - /* Enable the command done interrupt which 220 - * we use to determine completion of a command */ 221 - bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); 211 + init_completion(&bs->done); 222 212 223 213 /* Fill in the Message control register */ 224 214 msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT); ··· 234 230 cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); 235 231 cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); 236 232 bcm_spi_writew(bs, cmd, SPI_CMD); 237 - wait_for_completion(&bs->done); 238 233 239 - /* Disable the CMD_DONE interrupt */ 240 - bcm_spi_writeb(bs, 0, SPI_INT_MASK); 234 + /* Enable the CMD_DONE interrupt */ 235 + bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); 241 236 242 237 return t->len - bs->remaining_bytes; 243 238 } 244 239 245 - static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m) 240 + static int bcm63xx_spi_prepare_transfer(struct spi_master *master) 246 241 { 247 - struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); 242 + struct bcm63xx_spi *bs = spi_master_get_devdata(master); 243 + 244 + pm_runtime_get_sync(&bs->pdev->dev); 245 + 246 + return 0; 247 + } 248 + 249 + static int bcm63xx_spi_unprepare_transfer(struct spi_master *master) 250 + { 251 + struct bcm63xx_spi *bs = spi_master_get_devdata(master); 252 + 253 + pm_runtime_put(&bs->pdev->dev); 254 + 255 + return 0; 256 + } 257 + 258 + static int bcm63xx_spi_transfer_one(struct spi_master *master, 259 + struct spi_message *m) 260 + { 261 + struct bcm63xx_spi *bs = spi_master_get_devdata(master); 248 262 struct spi_transfer *t; 249 - int ret = 0; 250 - 251 - if (unlikely(list_empty(&m->transfers))) 252 - return -EINVAL; 253 - 254 - if (bs->stopping) 255 - return -ESHUTDOWN; 263 + struct spi_device *spi = m->spi; 264 + int status = 0; 265 + unsigned int timeout = 0; 256 266 257 267 list_for_each_entry(t, &m->transfers, transfer_list) { 258 - ret += bcm63xx_txrx_bufs(spi, t); 268 + unsigned int len = t->len; 269 + u8 rx_tail; 270 + 271 + status = bcm63xx_spi_check_transfer(spi, t); 272 + if (status < 0) 273 + goto exit; 274 + 275 + /* configure adapter for a new transfer */ 276 + bcm63xx_spi_setup_transfer(spi, t); 277 + 278 + while (len) { 279 + /* send the data */ 280 + len -= bcm63xx_txrx_bufs(spi, t); 281 + 282 + timeout = wait_for_completion_timeout(&bs->done, HZ); 283 + if (!timeout) { 284 + status = -ETIMEDOUT; 285 + goto exit; 286 + } 287 + 288 + /* read out all data */ 289 + rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL); 290 + 291 + /* Read out all the data */ 292 + if (rx_tail) 293 + memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail); 294 + } 295 + 296 + m->actual_length += t->len; 259 297 } 298 + exit: 299 + m->status = status; 300 + spi_finalize_current_message(master); 260 301 261 - m->complete(m->context); 262 - 263 - return ret; 302 + return 0; 264 303 } 265 304 266 305 /* This driver supports single master mode only. Hence ··· 314 267 struct spi_master *master = (struct spi_master *)dev_id; 315 268 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 316 269 u8 intr; 317 - u16 cmd; 318 270 319 271 /* Read interupts and clear them immediately */ 320 272 intr = bcm_spi_readb(bs, SPI_INT_STATUS); 321 273 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); 322 274 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 323 275 324 - /* A tansfer completed */ 325 - if (intr & SPI_INTR_CMD_DONE) { 326 - u8 rx_tail; 327 - 328 - rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL); 329 - 330 - /* Read out all the data */ 331 - if (rx_tail) 332 - memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail); 333 - 334 - /* See if there is more data to send */ 335 - if (bs->remaining_bytes > 0) { 336 - bcm63xx_spi_fill_tx_fifo(bs); 337 - 338 - /* Start the transfer */ 339 - bcm_spi_writew(bs, SPI_HD_W << SPI_MSG_TYPE_SHIFT, 340 - SPI_MSG_CTL); 341 - cmd = bcm_spi_readw(bs, SPI_CMD); 342 - cmd |= SPI_CMD_START_IMMEDIATE; 343 - cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); 344 - bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); 345 - bcm_spi_writew(bs, cmd, SPI_CMD); 346 - } else { 347 - complete(&bs->done); 348 - } 349 - } 276 + /* A transfer completed */ 277 + if (intr & SPI_INTR_CMD_DONE) 278 + complete(&bs->done); 350 279 351 280 return IRQ_HANDLED; 352 281 } ··· 368 345 } 369 346 370 347 bs = spi_master_get_devdata(master); 371 - init_completion(&bs->done); 372 348 373 349 platform_set_drvdata(pdev, master); 374 350 bs->pdev = pdev; ··· 401 379 master->bus_num = pdata->bus_num; 402 380 master->num_chipselect = pdata->num_chipselect; 403 381 master->setup = bcm63xx_spi_setup; 404 - master->transfer = bcm63xx_transfer; 382 + master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer; 383 + master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer; 384 + master->transfer_one_message = bcm63xx_spi_transfer_one; 385 + master->mode_bits = MODEBITS; 405 386 bs->speed_hz = pdata->speed_hz; 406 - bs->stopping = 0; 407 387 bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA)); 408 388 bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA)); 409 - spin_lock_init(&bs->lock); 410 389 411 390 /* Initialize hardware */ 412 391 clk_enable(bs->clk); ··· 441 418 struct spi_master *master = platform_get_drvdata(pdev); 442 419 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 443 420 421 + spi_unregister_master(master); 422 + 444 423 /* reset spi block */ 445 424 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 446 - spin_lock(&bs->lock); 447 - bs->stopping = 1; 448 425 449 426 /* HW shutdown */ 450 427 clk_disable(bs->clk); 451 428 clk_put(bs->clk); 452 429 453 - spin_unlock(&bs->lock); 454 430 platform_set_drvdata(pdev, 0); 455 - spi_unregister_master(master); 456 431 457 432 return 0; 458 433 }

+11 -10

drivers/spi/spi-bfin-sport.c

··· 252 252 bfin_sport_spi_restore_state(struct bfin_sport_spi_master_data *drv_data) 253 253 { 254 254 struct bfin_sport_spi_slave_data *chip = drv_data->cur_chip; 255 - unsigned int bits = (drv_data->ops == &bfin_sport_transfer_ops_u8 ? 7 : 15); 256 255 257 256 bfin_sport_spi_disable(drv_data); 258 257 dev_dbg(drv_data->dev, "restoring spi ctl state\n"); 259 258 260 259 bfin_write(&drv_data->regs->tcr1, chip->ctl_reg); 261 - bfin_write(&drv_data->regs->tcr2, bits); 262 260 bfin_write(&drv_data->regs->tclkdiv, chip->baud); 263 - bfin_write(&drv_data->regs->tfsdiv, bits); 264 261 SSYNC(); 265 262 266 263 bfin_write(&drv_data->regs->rcr1, chip->ctl_reg & ~(ITCLK | ITFS)); 267 - bfin_write(&drv_data->regs->rcr2, bits); 268 264 SSYNC(); 269 265 270 266 bfin_sport_spi_cs_active(chip); ··· 416 420 drv_data->cs_change = transfer->cs_change; 417 421 418 422 /* Bits per word setup */ 419 - bits_per_word = transfer->bits_per_word ? : message->spi->bits_per_word; 420 - if (bits_per_word == 8) 421 - drv_data->ops = &bfin_sport_transfer_ops_u8; 422 - else 423 + bits_per_word = transfer->bits_per_word ? : 424 + message->spi->bits_per_word ? : 8; 425 + if (bits_per_word % 16 == 0) 423 426 drv_data->ops = &bfin_sport_transfer_ops_u16; 427 + else 428 + drv_data->ops = &bfin_sport_transfer_ops_u8; 429 + bfin_write(&drv_data->regs->tcr2, bits_per_word - 1); 430 + bfin_write(&drv_data->regs->tfsdiv, bits_per_word - 1); 431 + bfin_write(&drv_data->regs->rcr2, bits_per_word - 1); 424 432 425 433 drv_data->state = RUNNING_STATE; 426 434 ··· 598 598 } 599 599 chip->cs_chg_udelay = chip_info->cs_chg_udelay; 600 600 chip->idle_tx_val = chip_info->idle_tx_val; 601 - spi->bits_per_word = chip_info->bits_per_word; 602 601 } 603 602 } 604 603 605 - if (spi->bits_per_word != 8 && spi->bits_per_word != 16) { 604 + if (spi->bits_per_word % 8) { 605 + dev_err(&spi->dev, "%d bits_per_word is not supported\n", 606 + spi->bits_per_word); 606 607 ret = -EINVAL; 607 608 goto error; 608 609 }

+8 -6

drivers/spi/spi-bfin5xx.c

··· 396 396 /* last read */ 397 397 if (drv_data->rx) { 398 398 dev_dbg(&drv_data->pdev->dev, "last read\n"); 399 - if (n_bytes % 2) { 399 + if (!(n_bytes % 2)) { 400 400 u16 *buf = (u16 *)drv_data->rx; 401 401 for (loop = 0; loop < n_bytes / 2; loop++) 402 402 *buf++ = bfin_read(&drv_data->regs->rdbr); ··· 424 424 if (drv_data->rx && drv_data->tx) { 425 425 /* duplex */ 426 426 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n"); 427 - if (n_bytes % 2) { 427 + if (!(n_bytes % 2)) { 428 428 u16 *buf = (u16 *)drv_data->rx; 429 429 u16 *buf2 = (u16 *)drv_data->tx; 430 430 for (loop = 0; loop < n_bytes / 2; loop++) { ··· 442 442 } else if (drv_data->rx) { 443 443 /* read */ 444 444 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n"); 445 - if (n_bytes % 2) { 445 + if (!(n_bytes % 2)) { 446 446 u16 *buf = (u16 *)drv_data->rx; 447 447 for (loop = 0; loop < n_bytes / 2; loop++) { 448 448 *buf++ = bfin_read(&drv_data->regs->rdbr); ··· 458 458 } else if (drv_data->tx) { 459 459 /* write */ 460 460 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n"); 461 - if (n_bytes % 2) { 461 + if (!(n_bytes % 2)) { 462 462 u16 *buf = (u16 *)drv_data->tx; 463 463 for (loop = 0; loop < n_bytes / 2; loop++) { 464 464 bfin_read(&drv_data->regs->rdbr); ··· 587 587 if (message->state == DONE_STATE) { 588 588 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n"); 589 589 message->status = 0; 590 + bfin_spi_flush(drv_data); 590 591 bfin_spi_giveback(drv_data); 591 592 return; 592 593 } ··· 871 870 message->actual_length += drv_data->len_in_bytes; 872 871 /* Move to next transfer of this msg */ 873 872 message->state = bfin_spi_next_transfer(drv_data); 874 - if (drv_data->cs_change) 873 + if (drv_data->cs_change && message->state != DONE_STATE) { 874 + bfin_spi_flush(drv_data); 875 875 bfin_spi_cs_deactive(drv_data, chip); 876 + } 876 877 } 877 878 878 879 /* Schedule next transfer tasklet */ ··· 1029 1026 chip->cs_chg_udelay = chip_info->cs_chg_udelay; 1030 1027 chip->idle_tx_val = chip_info->idle_tx_val; 1031 1028 chip->pio_interrupt = chip_info->pio_interrupt; 1032 - spi->bits_per_word = chip_info->bits_per_word; 1033 1029 } else { 1034 1030 /* force a default base state */ 1035 1031 chip->ctl_reg &= bfin_ctl_reg;

+10 -14

drivers/spi/spi-ep93xx.c

··· 545 545 * in case of failure. 546 546 */ 547 547 static struct dma_async_tx_descriptor * 548 - ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_data_direction dir) 548 + ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir) 549 549 { 550 550 struct spi_transfer *t = espi->current_msg->state; 551 551 struct dma_async_tx_descriptor *txd; 552 552 enum dma_slave_buswidth buswidth; 553 553 struct dma_slave_config conf; 554 - enum dma_transfer_direction slave_dirn; 555 554 struct scatterlist *sg; 556 555 struct sg_table *sgt; 557 556 struct dma_chan *chan; ··· 566 567 memset(&conf, 0, sizeof(conf)); 567 568 conf.direction = dir; 568 569 569 - if (dir == DMA_FROM_DEVICE) { 570 + if (dir == DMA_DEV_TO_MEM) { 570 571 chan = espi->dma_rx; 571 572 buf = t->rx_buf; 572 573 sgt = &espi->rx_sgt; 573 574 574 575 conf.src_addr = espi->sspdr_phys; 575 576 conf.src_addr_width = buswidth; 576 - slave_dirn = DMA_DEV_TO_MEM; 577 577 } else { 578 578 chan = espi->dma_tx; 579 579 buf = t->tx_buf; ··· 580 582 581 583 conf.dst_addr = espi->sspdr_phys; 582 584 conf.dst_addr_width = buswidth; 583 - slave_dirn = DMA_MEM_TO_DEV; 584 585 } 585 586 586 587 ret = dmaengine_slave_config(chan, &conf); ··· 630 633 if (!nents) 631 634 return ERR_PTR(-ENOMEM); 632 635 633 - txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, 634 - slave_dirn, DMA_CTRL_ACK); 636 + txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir, DMA_CTRL_ACK); 635 637 if (!txd) { 636 638 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); 637 639 return ERR_PTR(-ENOMEM); ··· 647 651 * unmapped. 648 652 */ 649 653 static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi, 650 - enum dma_data_direction dir) 654 + enum dma_transfer_direction dir) 651 655 { 652 656 struct dma_chan *chan; 653 657 struct sg_table *sgt; 654 658 655 - if (dir == DMA_FROM_DEVICE) { 659 + if (dir == DMA_DEV_TO_MEM) { 656 660 chan = espi->dma_rx; 657 661 sgt = &espi->rx_sgt; 658 662 } else { ··· 673 677 struct spi_message *msg = espi->current_msg; 674 678 struct dma_async_tx_descriptor *rxd, *txd; 675 679 676 - rxd = ep93xx_spi_dma_prepare(espi, DMA_FROM_DEVICE); 680 + rxd = ep93xx_spi_dma_prepare(espi, DMA_DEV_TO_MEM); 677 681 if (IS_ERR(rxd)) { 678 682 dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd)); 679 683 msg->status = PTR_ERR(rxd); 680 684 return; 681 685 } 682 686 683 - txd = ep93xx_spi_dma_prepare(espi, DMA_TO_DEVICE); 687 + txd = ep93xx_spi_dma_prepare(espi, DMA_MEM_TO_DEV); 684 688 if (IS_ERR(txd)) { 685 - ep93xx_spi_dma_finish(espi, DMA_FROM_DEVICE); 689 + ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM); 686 690 dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(rxd)); 687 691 msg->status = PTR_ERR(txd); 688 692 return; ··· 701 705 702 706 wait_for_completion(&espi->wait); 703 707 704 - ep93xx_spi_dma_finish(espi, DMA_TO_DEVICE); 705 - ep93xx_spi_dma_finish(espi, DMA_FROM_DEVICE); 708 + ep93xx_spi_dma_finish(espi, DMA_MEM_TO_DEV); 709 + ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM); 706 710 } 707 711 708 712 /**

+34 -24

drivers/spi/spi-pl022.c

··· 1667 1667 /* cpsdvsr = 254 & scr = 255 */ 1668 1668 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); 1669 1669 1670 - if (!((freq <= max_tclk) && (freq >= min_tclk))) { 1670 + if (freq > max_tclk) 1671 + dev_warn(&pl022->adev->dev, 1672 + "Max speed that can be programmed is %d Hz, you requested %d\n", 1673 + max_tclk, freq); 1674 + 1675 + if (freq < min_tclk) { 1671 1676 dev_err(&pl022->adev->dev, 1672 - "controller data is incorrect: out of range frequency"); 1677 + "Requested frequency: %d Hz is less than minimum possible %d Hz\n", 1678 + freq, min_tclk); 1673 1679 return -EINVAL; 1674 1680 } 1675 1681 ··· 1687 1681 while (scr <= SCR_MAX) { 1688 1682 tmp = spi_rate(rate, cpsdvsr, scr); 1689 1683 1690 - if (tmp > freq) 1684 + if (tmp > freq) { 1685 + /* we need lower freq */ 1691 1686 scr++; 1687 + continue; 1688 + } 1689 + 1692 1690 /* 1693 - * If found exact value, update and break. 1694 - * If found more closer value, update and continue. 1691 + * If found exact value, mark found and break. 1692 + * If found more closer value, update and break. 1695 1693 */ 1696 - else if ((tmp == freq) || (tmp > best_freq)) { 1694 + if (tmp > best_freq) { 1697 1695 best_freq = tmp; 1698 1696 best_cpsdvsr = cpsdvsr; 1699 1697 best_scr = scr; 1700 1698 1701 1699 if (tmp == freq) 1702 - break; 1700 + found = 1; 1703 1701 } 1704 - scr++; 1702 + /* 1703 + * increased scr will give lower rates, which are not 1704 + * required 1705 + */ 1706 + break; 1705 1707 } 1706 1708 cpsdvsr += 2; 1707 1709 scr = SCR_MIN; 1708 1710 } 1711 + 1712 + WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n", 1713 + freq); 1709 1714 1710 1715 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); 1711 1716 clk_freq->scr = (u8) (best_scr & 0xFF); ··· 1840 1823 } else 1841 1824 chip->cs_control = chip_info->cs_control; 1842 1825 1843 - if (bits <= 3) { 1844 - /* PL022 doesn't support less than 4-bits */ 1826 + /* Check bits per word with vendor specific range */ 1827 + if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { 1845 1828 status = -ENOTSUPP; 1829 + dev_err(&spi->dev, "illegal data size for this controller!\n"); 1830 + dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", 1831 + pl022->vendor->max_bpw); 1846 1832 goto err_config_params; 1847 1833 } else if (bits <= 8) { 1848 1834 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); ··· 1858 1838 chip->read = READING_U16; 1859 1839 chip->write = WRITING_U16; 1860 1840 } else { 1861 - if (pl022->vendor->max_bpw >= 32) { 1862 - dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 1863 - chip->n_bytes = 4; 1864 - chip->read = READING_U32; 1865 - chip->write = WRITING_U32; 1866 - } else { 1867 - dev_err(&spi->dev, 1868 - "illegal data size for this controller!\n"); 1869 - dev_err(&spi->dev, 1870 - "a standard pl022 can only handle " 1871 - "1 <= n <= 16 bit words\n"); 1872 - status = -ENOTSUPP; 1873 - goto err_config_params; 1874 - } 1841 + dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 1842 + chip->n_bytes = 4; 1843 + chip->read = READING_U32; 1844 + chip->write = WRITING_U32; 1875 1845 } 1876 1846 1877 1847 /* Now Initialize all register settings required for this chip */

+1 -1

include/linux/spi/spi.h

··· 254 254 * driver is finished with this message, it must call 255 255 * spi_finalize_current_message() so the subsystem can issue the next 256 256 * transfer 257 - * @prepare_transfer_hardware: there are currently no more messages on the 257 + * @unprepare_transfer_hardware: there are currently no more messages on the 258 258 * queue so the subsystem notifies the driver that it may relax the 259 259 * hardware by issuing this call 260 260 *

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