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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: Add support for Camera Clock Controller on SA8775P
Add support for Camera Clock Controller on SA8755P platform.
Reviewed-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-4-4a9f17dc683a@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Taniya Das
and committed by
Bjorn Andersson
84c74dfb
9c28d1b9
+1879
+10
drivers/clk/qcom/Kconfig
+10
drivers/clk/qcom/Kconfig
···
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Say Y if you want to use multimedia devices or peripheral
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devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
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469
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+
config SA_CAMCC_8775P
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tristate "SA8775P Camera Clock Controller"
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depends on ARM64 || COMPILE_TEST
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select SA_GCC_8775P
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help
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Support for the camera clock controller on Qualcomm Technologies, Inc
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SA8775P devices.
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Say Y if you want to support camera devices and functionality such as
478
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capturing pictures.
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+
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config SC_CAMCC_7180
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tristate "SC7180 Camera Clock Controller"
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depends on ARM64 || COMPILE_TEST
+1
drivers/clk/qcom/Makefile
+1
drivers/clk/qcom/Makefile
···
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obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o
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obj-$(CONFIG_SC_DISPCC_7280) += dispcc-sc7280.o
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obj-$(CONFIG_SC_DISPCC_8280XP) += dispcc-sc8280xp.o
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+
obj-$(CONFIG_SA_CAMCC_8775P) += camcc-sa8775p.o
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obj-$(CONFIG_SA_GCC_8775P) += gcc-sa8775p.o
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obj-$(CONFIG_SA_GPUCC_8775P) += gpucc-sa8775p.o
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obj-$(CONFIG_SA_VIDEOCC_8775P) += videocc-sa8775p.o
+1868
drivers/clk/qcom/camcc-sa8775p.c
+1868
drivers/clk/qcom/camcc-sa8775p.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
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+
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+
#include <linux/clk-provider.h>
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+
#include <linux/module.h>
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+
#include <linux/mod_devicetable.h>
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+
#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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+
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#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
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+
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#include "clk-alpha-pll.h"
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+
#include "clk-branch.h"
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#include "clk-pll.h"
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#include "clk-rcg.h"
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+
#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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+
#include "clk-regmap-mux.h"
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+
#include "common.h"
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#include "gdsc.h"
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#include "reset.h"
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+
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enum {
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DT_IFACE,
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DT_BI_TCXO,
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DT_BI_TCXO_AO,
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DT_SLEEP_CLK,
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};
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+
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enum {
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P_BI_TCXO,
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P_BI_TCXO_AO,
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P_CAM_CC_PLL0_OUT_EVEN,
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P_CAM_CC_PLL0_OUT_MAIN,
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P_CAM_CC_PLL0_OUT_ODD,
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P_CAM_CC_PLL2_OUT_EVEN,
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P_CAM_CC_PLL2_OUT_MAIN,
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P_CAM_CC_PLL3_OUT_EVEN,
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P_CAM_CC_PLL4_OUT_EVEN,
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P_CAM_CC_PLL5_OUT_EVEN,
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P_SLEEP_CLK,
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};
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+
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static const struct pll_vco lucid_evo_vco[] = {
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{ 249600000, 2020000000, 0 },
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};
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+
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static const struct pll_vco rivian_evo_vco[] = {
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{ 864000000, 1056000000, 0 },
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};
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+
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static const struct alpha_pll_config cam_cc_pll0_config = {
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.l = 0x3e,
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.alpha = 0x8000,
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+
.config_ctl_val = 0x20485699,
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+
.config_ctl_hi_val = 0x00182261,
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+
.config_ctl_hi1_val = 0x32aa299c,
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.user_ctl_val = 0x00008400,
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.user_ctl_hi_val = 0x00400805,
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};
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+
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static struct clk_alpha_pll cam_cc_pll0 = {
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+
.offset = 0x0,
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+
.vco_table = lucid_evo_vco,
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+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
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+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll0",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_evo_ops,
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},
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},
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};
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+
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static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
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{ 0x1, 2 },
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{ }
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};
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+
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static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
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.offset = 0x0,
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.post_div_shift = 10,
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.post_div_table = post_div_table_cam_cc_pll0_out_even,
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.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll0_out_even",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll0.clkr.hw,
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},
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+
.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
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},
104
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};
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+
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static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
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{ 0x2, 3 },
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{ }
109
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};
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+
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static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
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+
.offset = 0x0,
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.post_div_shift = 14,
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.post_div_table = post_div_table_cam_cc_pll0_out_odd,
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.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr.hw.init = &(const struct clk_init_data) {
119
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.name = "cam_cc_pll0_out_odd",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll0.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
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},
127
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};
128
+
129
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static const struct alpha_pll_config cam_cc_pll2_config = {
130
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.l = 0x32,
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+
.alpha = 0x0,
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.config_ctl_val = 0x90008820,
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+
.config_ctl_hi_val = 0x00890263,
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+
.config_ctl_hi1_val = 0x00000247,
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+
.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00400000,
137
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};
138
+
139
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static struct clk_alpha_pll cam_cc_pll2 = {
140
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.offset = 0x1000,
141
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.vco_table = rivian_evo_vco,
142
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.num_vco = ARRAY_SIZE(rivian_evo_vco),
143
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
144
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.clkr = {
145
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.hw.init = &(const struct clk_init_data) {
146
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.name = "cam_cc_pll2",
147
+
.parent_data = &(const struct clk_parent_data) {
148
+
.index = DT_BI_TCXO,
149
+
},
150
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.num_parents = 1,
151
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.ops = &clk_alpha_pll_rivian_evo_ops,
152
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},
153
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},
154
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};
155
+
156
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static const struct alpha_pll_config cam_cc_pll3_config = {
157
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.l = 0x32,
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.alpha = 0x0,
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.config_ctl_val = 0x20485699,
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+
.config_ctl_hi_val = 0x00182261,
161
+
.config_ctl_hi1_val = 0x32aa299c,
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.user_ctl_val = 0x00000400,
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.user_ctl_hi_val = 0x00400805,
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};
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+
166
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static struct clk_alpha_pll cam_cc_pll3 = {
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.offset = 0x2000,
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.vco_table = lucid_evo_vco,
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+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll3",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
177
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_evo_ops,
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},
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},
181
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};
182
+
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static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
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{ 0x1, 2 },
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{ }
186
+
};
187
+
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static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
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.offset = 0x2000,
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.post_div_shift = 10,
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.post_div_table = post_div_table_cam_cc_pll3_out_even,
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+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
193
+
.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll3_out_even",
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+
.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll3.clkr.hw,
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+
},
200
+
.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
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},
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};
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+
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static const struct alpha_pll_config cam_cc_pll4_config = {
207
+
.l = 0x32,
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.alpha = 0x0,
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.config_ctl_val = 0x20485699,
210
+
.config_ctl_hi_val = 0x00182261,
211
+
.config_ctl_hi1_val = 0x32aa299c,
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+
.user_ctl_val = 0x00000400,
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.user_ctl_hi_val = 0x00400805,
214
+
};
215
+
216
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static struct clk_alpha_pll cam_cc_pll4 = {
217
+
.offset = 0x3000,
218
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.vco_table = lucid_evo_vco,
219
+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
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+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
221
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.clkr = {
222
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.hw.init = &(const struct clk_init_data) {
223
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.name = "cam_cc_pll4",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
227
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_evo_ops,
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},
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},
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};
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+
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static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
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{ 0x1, 2 },
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{ }
236
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};
237
+
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static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
239
+
.offset = 0x3000,
240
+
.post_div_shift = 10,
241
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.post_div_table = post_div_table_cam_cc_pll4_out_even,
242
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
243
+
.width = 4,
244
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
245
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.clkr.hw.init = &(const struct clk_init_data) {
246
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.name = "cam_cc_pll4_out_even",
247
+
.parent_hws = (const struct clk_hw*[]) {
248
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&cam_cc_pll4.clkr.hw,
249
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},
250
+
.num_parents = 1,
251
+
.flags = CLK_SET_RATE_PARENT,
252
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.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
253
+
},
254
+
};
255
+
256
+
static const struct alpha_pll_config cam_cc_pll5_config = {
257
+
.l = 0x32,
258
+
.alpha = 0x0,
259
+
.config_ctl_val = 0x20485699,
260
+
.config_ctl_hi_val = 0x00182261,
261
+
.config_ctl_hi1_val = 0x32aa299c,
262
+
.user_ctl_val = 0x00000400,
263
+
.user_ctl_hi_val = 0x00400805,
264
+
};
265
+
266
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static struct clk_alpha_pll cam_cc_pll5 = {
267
+
.offset = 0x4000,
268
+
.vco_table = lucid_evo_vco,
269
+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
270
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
271
+
.clkr = {
272
+
.hw.init = &(const struct clk_init_data) {
273
+
.name = "cam_cc_pll5",
274
+
.parent_data = &(const struct clk_parent_data) {
275
+
.index = DT_BI_TCXO,
276
+
},
277
+
.num_parents = 1,
278
+
.ops = &clk_alpha_pll_lucid_evo_ops,
279
+
},
280
+
},
281
+
};
282
+
283
+
static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
284
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{ 0x1, 2 },
285
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{ }
286
+
};
287
+
288
+
static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
289
+
.offset = 0x4000,
290
+
.post_div_shift = 10,
291
+
.post_div_table = post_div_table_cam_cc_pll5_out_even,
292
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even),
293
+
.width = 4,
294
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
295
+
.clkr.hw.init = &(const struct clk_init_data) {
296
+
.name = "cam_cc_pll5_out_even",
297
+
.parent_hws = (const struct clk_hw*[]) {
298
+
&cam_cc_pll5.clkr.hw,
299
+
},
300
+
.num_parents = 1,
301
+
.flags = CLK_SET_RATE_PARENT,
302
+
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
303
+
},
304
+
};
305
+
306
+
static const struct parent_map cam_cc_parent_map_0[] = {
307
+
{ P_BI_TCXO, 0 },
308
+
{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
309
+
{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
310
+
{ P_CAM_CC_PLL0_OUT_ODD, 3 },
311
+
};
312
+
313
+
static const struct clk_parent_data cam_cc_parent_data_0[] = {
314
+
{ .index = DT_BI_TCXO },
315
+
{ .hw = &cam_cc_pll0.clkr.hw },
316
+
{ .hw = &cam_cc_pll0_out_even.clkr.hw },
317
+
{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
318
+
};
319
+
320
+
static const struct parent_map cam_cc_parent_map_1[] = {
321
+
{ P_BI_TCXO, 0 },
322
+
{ P_CAM_CC_PLL2_OUT_EVEN, 3 },
323
+
{ P_CAM_CC_PLL2_OUT_MAIN, 5 },
324
+
};
325
+
326
+
static const struct clk_parent_data cam_cc_parent_data_1[] = {
327
+
{ .index = DT_BI_TCXO },
328
+
{ .hw = &cam_cc_pll2.clkr.hw },
329
+
{ .hw = &cam_cc_pll2.clkr.hw },
330
+
};
331
+
332
+
static const struct parent_map cam_cc_parent_map_2[] = {
333
+
{ P_BI_TCXO, 0 },
334
+
{ P_CAM_CC_PLL4_OUT_EVEN, 6 },
335
+
};
336
+
337
+
static const struct clk_parent_data cam_cc_parent_data_2[] = {
338
+
{ .index = DT_BI_TCXO },
339
+
{ .hw = &cam_cc_pll4_out_even.clkr.hw },
340
+
};
341
+
342
+
static const struct parent_map cam_cc_parent_map_3[] = {
343
+
{ P_BI_TCXO, 0 },
344
+
{ P_CAM_CC_PLL5_OUT_EVEN, 6 },
345
+
};
346
+
347
+
static const struct clk_parent_data cam_cc_parent_data_3[] = {
348
+
{ .index = DT_BI_TCXO },
349
+
{ .hw = &cam_cc_pll5_out_even.clkr.hw },
350
+
};
351
+
352
+
static const struct parent_map cam_cc_parent_map_4[] = {
353
+
{ P_BI_TCXO, 0 },
354
+
{ P_CAM_CC_PLL3_OUT_EVEN, 6 },
355
+
};
356
+
357
+
static const struct clk_parent_data cam_cc_parent_data_4[] = {
358
+
{ .index = DT_BI_TCXO },
359
+
{ .hw = &cam_cc_pll3_out_even.clkr.hw },
360
+
};
361
+
362
+
static const struct parent_map cam_cc_parent_map_5[] = {
363
+
{ P_SLEEP_CLK, 0 },
364
+
};
365
+
366
+
static const struct clk_parent_data cam_cc_parent_data_5[] = {
367
+
{ .index = DT_SLEEP_CLK },
368
+
};
369
+
370
+
static const struct parent_map cam_cc_parent_map_6_ao[] = {
371
+
{ P_BI_TCXO_AO, 0 },
372
+
};
373
+
374
+
static const struct clk_parent_data cam_cc_parent_data_6_ao[] = {
375
+
{ .index = DT_BI_TCXO_AO },
376
+
};
377
+
378
+
static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
379
+
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
380
+
{ }
381
+
};
382
+
383
+
static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
384
+
.cmd_rcgr = 0x13170,
385
+
.mnd_width = 0,
386
+
.hid_width = 5,
387
+
.parent_map = cam_cc_parent_map_0,
388
+
.freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
389
+
.clkr.hw.init = &(const struct clk_init_data) {
390
+
.name = "cam_cc_camnoc_axi_clk_src",
391
+
.parent_data = cam_cc_parent_data_0,
392
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
393
+
.flags = CLK_SET_RATE_PARENT,
394
+
.ops = &clk_rcg2_shared_ops,
395
+
},
396
+
};
397
+
398
+
static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
399
+
F(37500000, P_CAM_CC_PLL0_OUT_MAIN, 16, 1, 2),
400
+
{ }
401
+
};
402
+
403
+
static struct clk_rcg2 cam_cc_cci_0_clk_src = {
404
+
.cmd_rcgr = 0x130a0,
405
+
.mnd_width = 8,
406
+
.hid_width = 5,
407
+
.parent_map = cam_cc_parent_map_0,
408
+
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
409
+
.clkr.hw.init = &(const struct clk_init_data) {
410
+
.name = "cam_cc_cci_0_clk_src",
411
+
.parent_data = cam_cc_parent_data_0,
412
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
413
+
.flags = CLK_SET_RATE_PARENT,
414
+
.ops = &clk_rcg2_shared_ops,
415
+
},
416
+
};
417
+
418
+
static struct clk_rcg2 cam_cc_cci_1_clk_src = {
419
+
.cmd_rcgr = 0x130bc,
420
+
.mnd_width = 8,
421
+
.hid_width = 5,
422
+
.parent_map = cam_cc_parent_map_0,
423
+
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
424
+
.clkr.hw.init = &(const struct clk_init_data) {
425
+
.name = "cam_cc_cci_1_clk_src",
426
+
.parent_data = cam_cc_parent_data_0,
427
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
428
+
.flags = CLK_SET_RATE_PARENT,
429
+
.ops = &clk_rcg2_shared_ops,
430
+
},
431
+
};
432
+
433
+
static struct clk_rcg2 cam_cc_cci_2_clk_src = {
434
+
.cmd_rcgr = 0x130d8,
435
+
.mnd_width = 8,
436
+
.hid_width = 5,
437
+
.parent_map = cam_cc_parent_map_0,
438
+
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
439
+
.clkr.hw.init = &(const struct clk_init_data) {
440
+
.name = "cam_cc_cci_2_clk_src",
441
+
.parent_data = cam_cc_parent_data_0,
442
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
443
+
.flags = CLK_SET_RATE_PARENT,
444
+
.ops = &clk_rcg2_shared_ops,
445
+
},
446
+
};
447
+
448
+
static struct clk_rcg2 cam_cc_cci_3_clk_src = {
449
+
.cmd_rcgr = 0x130f4,
450
+
.mnd_width = 8,
451
+
.hid_width = 5,
452
+
.parent_map = cam_cc_parent_map_0,
453
+
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
454
+
.clkr.hw.init = &(const struct clk_init_data) {
455
+
.name = "cam_cc_cci_3_clk_src",
456
+
.parent_data = cam_cc_parent_data_0,
457
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
458
+
.flags = CLK_SET_RATE_PARENT,
459
+
.ops = &clk_rcg2_shared_ops,
460
+
},
461
+
};
462
+
463
+
static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
464
+
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
465
+
{ }
466
+
};
467
+
468
+
static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
469
+
.cmd_rcgr = 0x11034,
470
+
.mnd_width = 0,
471
+
.hid_width = 5,
472
+
.parent_map = cam_cc_parent_map_0,
473
+
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
474
+
.clkr.hw.init = &(const struct clk_init_data) {
475
+
.name = "cam_cc_cphy_rx_clk_src",
476
+
.parent_data = cam_cc_parent_data_0,
477
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
478
+
.flags = CLK_SET_RATE_PARENT,
479
+
.ops = &clk_rcg2_shared_ops,
480
+
},
481
+
};
482
+
483
+
static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
484
+
.cmd_rcgr = 0x15074,
485
+
.mnd_width = 0,
486
+
.hid_width = 5,
487
+
.parent_map = cam_cc_parent_map_0,
488
+
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
489
+
.clkr.hw.init = &(const struct clk_init_data) {
490
+
.name = "cam_cc_csi0phytimer_clk_src",
491
+
.parent_data = cam_cc_parent_data_0,
492
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
493
+
.flags = CLK_SET_RATE_PARENT,
494
+
.ops = &clk_rcg2_shared_ops,
495
+
},
496
+
};
497
+
498
+
static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
499
+
.cmd_rcgr = 0x15098,
500
+
.mnd_width = 0,
501
+
.hid_width = 5,
502
+
.parent_map = cam_cc_parent_map_0,
503
+
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
504
+
.clkr.hw.init = &(const struct clk_init_data) {
505
+
.name = "cam_cc_csi1phytimer_clk_src",
506
+
.parent_data = cam_cc_parent_data_0,
507
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
508
+
.flags = CLK_SET_RATE_PARENT,
509
+
.ops = &clk_rcg2_shared_ops,
510
+
},
511
+
};
512
+
513
+
static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
514
+
.cmd_rcgr = 0x150b8,
515
+
.mnd_width = 0,
516
+
.hid_width = 5,
517
+
.parent_map = cam_cc_parent_map_0,
518
+
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
519
+
.clkr.hw.init = &(const struct clk_init_data) {
520
+
.name = "cam_cc_csi2phytimer_clk_src",
521
+
.parent_data = cam_cc_parent_data_0,
522
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
523
+
.flags = CLK_SET_RATE_PARENT,
524
+
.ops = &clk_rcg2_shared_ops,
525
+
},
526
+
};
527
+
528
+
static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
529
+
.cmd_rcgr = 0x150d8,
530
+
.mnd_width = 0,
531
+
.hid_width = 5,
532
+
.parent_map = cam_cc_parent_map_0,
533
+
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
534
+
.clkr.hw.init = &(const struct clk_init_data) {
535
+
.name = "cam_cc_csi3phytimer_clk_src",
536
+
.parent_data = cam_cc_parent_data_0,
537
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
538
+
.flags = CLK_SET_RATE_PARENT,
539
+
.ops = &clk_rcg2_shared_ops,
540
+
},
541
+
};
542
+
543
+
static struct clk_rcg2 cam_cc_csid_clk_src = {
544
+
.cmd_rcgr = 0x13150,
545
+
.mnd_width = 0,
546
+
.hid_width = 5,
547
+
.parent_map = cam_cc_parent_map_0,
548
+
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
549
+
.clkr.hw.init = &(const struct clk_init_data) {
550
+
.name = "cam_cc_csid_clk_src",
551
+
.parent_data = cam_cc_parent_data_0,
552
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
553
+
.flags = CLK_SET_RATE_PARENT,
554
+
.ops = &clk_rcg2_shared_ops,
555
+
},
556
+
};
557
+
558
+
static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
559
+
F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
560
+
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
561
+
{ }
562
+
};
563
+
564
+
static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
565
+
.cmd_rcgr = 0x13120,
566
+
.mnd_width = 0,
567
+
.hid_width = 5,
568
+
.parent_map = cam_cc_parent_map_0,
569
+
.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
570
+
.clkr.hw.init = &(const struct clk_init_data) {
571
+
.name = "cam_cc_fast_ahb_clk_src",
572
+
.parent_data = cam_cc_parent_data_0,
573
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
574
+
.flags = CLK_SET_RATE_PARENT,
575
+
.ops = &clk_rcg2_shared_ops,
576
+
},
577
+
};
578
+
579
+
static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
580
+
F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
581
+
F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
582
+
{ }
583
+
};
584
+
585
+
static struct clk_rcg2 cam_cc_icp_clk_src = {
586
+
.cmd_rcgr = 0x1307c,
587
+
.mnd_width = 0,
588
+
.hid_width = 5,
589
+
.parent_map = cam_cc_parent_map_0,
590
+
.freq_tbl = ftbl_cam_cc_icp_clk_src,
591
+
.clkr.hw.init = &(const struct clk_init_data) {
592
+
.name = "cam_cc_icp_clk_src",
593
+
.parent_data = cam_cc_parent_data_0,
594
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
595
+
.flags = CLK_SET_RATE_PARENT,
596
+
.ops = &clk_rcg2_shared_ops,
597
+
},
598
+
};
599
+
600
+
static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
601
+
F(480000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
602
+
F(600000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
603
+
{ }
604
+
};
605
+
606
+
static struct clk_rcg2 cam_cc_ife_0_clk_src = {
607
+
.cmd_rcgr = 0x11004,
608
+
.mnd_width = 0,
609
+
.hid_width = 5,
610
+
.parent_map = cam_cc_parent_map_2,
611
+
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
612
+
.clkr.hw.init = &(const struct clk_init_data) {
613
+
.name = "cam_cc_ife_0_clk_src",
614
+
.parent_data = cam_cc_parent_data_2,
615
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
616
+
.flags = CLK_SET_RATE_PARENT,
617
+
.ops = &clk_rcg2_shared_ops,
618
+
},
619
+
};
620
+
621
+
static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
622
+
F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
623
+
F(600000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
624
+
{ }
625
+
};
626
+
627
+
static struct clk_rcg2 cam_cc_ife_1_clk_src = {
628
+
.cmd_rcgr = 0x12004,
629
+
.mnd_width = 0,
630
+
.hid_width = 5,
631
+
.parent_map = cam_cc_parent_map_3,
632
+
.freq_tbl = ftbl_cam_cc_ife_1_clk_src,
633
+
.clkr.hw.init = &(const struct clk_init_data) {
634
+
.name = "cam_cc_ife_1_clk_src",
635
+
.parent_data = cam_cc_parent_data_3,
636
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
637
+
.flags = CLK_SET_RATE_PARENT,
638
+
.ops = &clk_rcg2_shared_ops,
639
+
},
640
+
};
641
+
642
+
static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = {
643
+
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
644
+
F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
645
+
{ }
646
+
};
647
+
648
+
static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
649
+
.cmd_rcgr = 0x13000,
650
+
.mnd_width = 0,
651
+
.hid_width = 5,
652
+
.parent_map = cam_cc_parent_map_0,
653
+
.freq_tbl = ftbl_cam_cc_ife_lite_clk_src,
654
+
.clkr.hw.init = &(const struct clk_init_data) {
655
+
.name = "cam_cc_ife_lite_clk_src",
656
+
.parent_data = cam_cc_parent_data_0,
657
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
658
+
.flags = CLK_SET_RATE_PARENT,
659
+
.ops = &clk_rcg2_shared_ops,
660
+
},
661
+
};
662
+
663
+
static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
664
+
.cmd_rcgr = 0x13020,
665
+
.mnd_width = 0,
666
+
.hid_width = 5,
667
+
.parent_map = cam_cc_parent_map_0,
668
+
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
669
+
.clkr.hw.init = &(const struct clk_init_data) {
670
+
.name = "cam_cc_ife_lite_csid_clk_src",
671
+
.parent_data = cam_cc_parent_data_0,
672
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
673
+
.flags = CLK_SET_RATE_PARENT,
674
+
.ops = &clk_rcg2_shared_ops,
675
+
},
676
+
};
677
+
678
+
static const struct freq_tbl ftbl_cam_cc_ipe_clk_src[] = {
679
+
F(480000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
680
+
F(600000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
681
+
{ }
682
+
};
683
+
684
+
static struct clk_rcg2 cam_cc_ipe_clk_src = {
685
+
.cmd_rcgr = 0x10004,
686
+
.mnd_width = 0,
687
+
.hid_width = 5,
688
+
.parent_map = cam_cc_parent_map_4,
689
+
.freq_tbl = ftbl_cam_cc_ipe_clk_src,
690
+
.clkr.hw.init = &(const struct clk_init_data) {
691
+
.name = "cam_cc_ipe_clk_src",
692
+
.parent_data = cam_cc_parent_data_4,
693
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
694
+
.flags = CLK_SET_RATE_PARENT,
695
+
.ops = &clk_rcg2_shared_ops,
696
+
},
697
+
};
698
+
699
+
static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
700
+
F(19200000, P_CAM_CC_PLL2_OUT_MAIN, 1, 1, 50),
701
+
F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4),
702
+
F(64000000, P_CAM_CC_PLL2_OUT_MAIN, 15, 0, 0),
703
+
{ }
704
+
};
705
+
706
+
static struct clk_rcg2 cam_cc_mclk0_clk_src = {
707
+
.cmd_rcgr = 0x15004,
708
+
.mnd_width = 8,
709
+
.hid_width = 5,
710
+
.parent_map = cam_cc_parent_map_1,
711
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
712
+
.clkr.hw.init = &(const struct clk_init_data) {
713
+
.name = "cam_cc_mclk0_clk_src",
714
+
.parent_data = cam_cc_parent_data_1,
715
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
716
+
.flags = CLK_SET_RATE_PARENT,
717
+
.ops = &clk_rcg2_shared_ops,
718
+
},
719
+
};
720
+
721
+
static struct clk_rcg2 cam_cc_mclk1_clk_src = {
722
+
.cmd_rcgr = 0x15020,
723
+
.mnd_width = 8,
724
+
.hid_width = 5,
725
+
.parent_map = cam_cc_parent_map_1,
726
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
727
+
.clkr.hw.init = &(const struct clk_init_data) {
728
+
.name = "cam_cc_mclk1_clk_src",
729
+
.parent_data = cam_cc_parent_data_1,
730
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
731
+
.flags = CLK_SET_RATE_PARENT,
732
+
.ops = &clk_rcg2_shared_ops,
733
+
},
734
+
};
735
+
736
+
static struct clk_rcg2 cam_cc_mclk2_clk_src = {
737
+
.cmd_rcgr = 0x1503c,
738
+
.mnd_width = 8,
739
+
.hid_width = 5,
740
+
.parent_map = cam_cc_parent_map_1,
741
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
742
+
.clkr.hw.init = &(const struct clk_init_data) {
743
+
.name = "cam_cc_mclk2_clk_src",
744
+
.parent_data = cam_cc_parent_data_1,
745
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
746
+
.flags = CLK_SET_RATE_PARENT,
747
+
.ops = &clk_rcg2_shared_ops,
748
+
},
749
+
};
750
+
751
+
static struct clk_rcg2 cam_cc_mclk3_clk_src = {
752
+
.cmd_rcgr = 0x15058,
753
+
.mnd_width = 8,
754
+
.hid_width = 5,
755
+
.parent_map = cam_cc_parent_map_1,
756
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
757
+
.clkr.hw.init = &(const struct clk_init_data) {
758
+
.name = "cam_cc_mclk3_clk_src",
759
+
.parent_data = cam_cc_parent_data_1,
760
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
761
+
.flags = CLK_SET_RATE_PARENT,
762
+
.ops = &clk_rcg2_shared_ops,
763
+
},
764
+
};
765
+
766
+
static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
767
+
F(32000, P_SLEEP_CLK, 1, 0, 0),
768
+
{ }
769
+
};
770
+
771
+
static struct clk_rcg2 cam_cc_sleep_clk_src = {
772
+
.cmd_rcgr = 0x131f0,
773
+
.mnd_width = 0,
774
+
.hid_width = 5,
775
+
.parent_map = cam_cc_parent_map_5,
776
+
.freq_tbl = ftbl_cam_cc_sleep_clk_src,
777
+
.clkr.hw.init = &(const struct clk_init_data) {
778
+
.name = "cam_cc_sleep_clk_src",
779
+
.parent_data = cam_cc_parent_data_5,
780
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
781
+
.flags = CLK_SET_RATE_PARENT,
782
+
.ops = &clk_rcg2_shared_ops,
783
+
},
784
+
};
785
+
786
+
static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
787
+
F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
788
+
{ }
789
+
};
790
+
791
+
static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
792
+
.cmd_rcgr = 0x13138,
793
+
.mnd_width = 8,
794
+
.hid_width = 5,
795
+
.parent_map = cam_cc_parent_map_0,
796
+
.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
797
+
.clkr.hw.init = &(const struct clk_init_data) {
798
+
.name = "cam_cc_slow_ahb_clk_src",
799
+
.parent_data = cam_cc_parent_data_0,
800
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
801
+
.flags = CLK_SET_RATE_PARENT,
802
+
.ops = &clk_rcg2_shared_ops,
803
+
},
804
+
};
805
+
806
+
static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
807
+
F(19200000, P_BI_TCXO_AO, 1, 0, 0),
808
+
{ }
809
+
};
810
+
811
+
static struct clk_rcg2 cam_cc_xo_clk_src = {
812
+
.cmd_rcgr = 0x131d4,
813
+
.mnd_width = 0,
814
+
.hid_width = 5,
815
+
.parent_map = cam_cc_parent_map_6_ao,
816
+
.freq_tbl = ftbl_cam_cc_xo_clk_src,
817
+
.clkr.hw.init = &(const struct clk_init_data) {
818
+
.name = "cam_cc_xo_clk_src",
819
+
.parent_data = cam_cc_parent_data_6_ao,
820
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_6_ao),
821
+
.flags = CLK_SET_RATE_PARENT,
822
+
.ops = &clk_rcg2_shared_ops,
823
+
},
824
+
};
825
+
826
+
static struct clk_branch cam_cc_camnoc_axi_clk = {
827
+
.halt_reg = 0x13188,
828
+
.halt_check = BRANCH_HALT,
829
+
.clkr = {
830
+
.enable_reg = 0x13188,
831
+
.enable_mask = BIT(0),
832
+
.hw.init = &(const struct clk_init_data) {
833
+
.name = "cam_cc_camnoc_axi_clk",
834
+
.parent_hws = (const struct clk_hw*[]) {
835
+
&cam_cc_camnoc_axi_clk_src.clkr.hw,
836
+
},
837
+
.num_parents = 1,
838
+
.flags = CLK_SET_RATE_PARENT,
839
+
.ops = &clk_branch2_ops,
840
+
},
841
+
},
842
+
};
843
+
844
+
static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
845
+
.halt_reg = 0x13190,
846
+
.halt_check = BRANCH_HALT,
847
+
.clkr = {
848
+
.enable_reg = 0x13190,
849
+
.enable_mask = BIT(0),
850
+
.hw.init = &(const struct clk_init_data) {
851
+
.name = "cam_cc_camnoc_dcd_xo_clk",
852
+
.parent_hws = (const struct clk_hw*[]) {
853
+
&cam_cc_xo_clk_src.clkr.hw,
854
+
},
855
+
.num_parents = 1,
856
+
.flags = CLK_SET_RATE_PARENT,
857
+
.ops = &clk_branch2_ops,
858
+
},
859
+
},
860
+
};
861
+
862
+
static struct clk_branch cam_cc_qdss_debug_xo_clk = {
863
+
.halt_reg = 0x131b8,
864
+
.halt_check = BRANCH_HALT,
865
+
.clkr = {
866
+
.enable_reg = 0x131b8,
867
+
.enable_mask = BIT(0),
868
+
.hw.init = &(const struct clk_init_data) {
869
+
.name = "cam_cc_qdss_debug_xo_clk",
870
+
.parent_hws = (const struct clk_hw*[]) {
871
+
&cam_cc_xo_clk_src.clkr.hw,
872
+
},
873
+
.num_parents = 1,
874
+
.flags = CLK_SET_RATE_PARENT,
875
+
.ops = &clk_branch2_ops,
876
+
},
877
+
},
878
+
};
879
+
880
+
static struct clk_branch cam_cc_cci_0_clk = {
881
+
.halt_reg = 0x130b8,
882
+
.halt_check = BRANCH_HALT,
883
+
.clkr = {
884
+
.enable_reg = 0x130b8,
885
+
.enable_mask = BIT(0),
886
+
.hw.init = &(const struct clk_init_data) {
887
+
.name = "cam_cc_cci_0_clk",
888
+
.parent_hws = (const struct clk_hw*[]) {
889
+
&cam_cc_cci_0_clk_src.clkr.hw,
890
+
},
891
+
.num_parents = 1,
892
+
.flags = CLK_SET_RATE_PARENT,
893
+
.ops = &clk_branch2_ops,
894
+
},
895
+
},
896
+
};
897
+
898
+
static struct clk_branch cam_cc_cci_1_clk = {
899
+
.halt_reg = 0x130d4,
900
+
.halt_check = BRANCH_HALT,
901
+
.clkr = {
902
+
.enable_reg = 0x130d4,
903
+
.enable_mask = BIT(0),
904
+
.hw.init = &(const struct clk_init_data) {
905
+
.name = "cam_cc_cci_1_clk",
906
+
.parent_hws = (const struct clk_hw*[]) {
907
+
&cam_cc_cci_1_clk_src.clkr.hw,
908
+
},
909
+
.num_parents = 1,
910
+
.flags = CLK_SET_RATE_PARENT,
911
+
.ops = &clk_branch2_ops,
912
+
},
913
+
},
914
+
};
915
+
916
+
static struct clk_branch cam_cc_cci_2_clk = {
917
+
.halt_reg = 0x130f0,
918
+
.halt_check = BRANCH_HALT,
919
+
.clkr = {
920
+
.enable_reg = 0x130f0,
921
+
.enable_mask = BIT(0),
922
+
.hw.init = &(const struct clk_init_data) {
923
+
.name = "cam_cc_cci_2_clk",
924
+
.parent_hws = (const struct clk_hw*[]) {
925
+
&cam_cc_cci_2_clk_src.clkr.hw,
926
+
},
927
+
.num_parents = 1,
928
+
.flags = CLK_SET_RATE_PARENT,
929
+
.ops = &clk_branch2_ops,
930
+
},
931
+
},
932
+
};
933
+
934
+
static struct clk_branch cam_cc_cci_3_clk = {
935
+
.halt_reg = 0x1310c,
936
+
.halt_check = BRANCH_HALT,
937
+
.clkr = {
938
+
.enable_reg = 0x1310c,
939
+
.enable_mask = BIT(0),
940
+
.hw.init = &(const struct clk_init_data) {
941
+
.name = "cam_cc_cci_3_clk",
942
+
.parent_hws = (const struct clk_hw*[]) {
943
+
&cam_cc_cci_3_clk_src.clkr.hw,
944
+
},
945
+
.num_parents = 1,
946
+
.flags = CLK_SET_RATE_PARENT,
947
+
.ops = &clk_branch2_ops,
948
+
},
949
+
},
950
+
};
951
+
952
+
static struct clk_branch cam_cc_core_ahb_clk = {
953
+
.halt_reg = 0x131d0,
954
+
.halt_check = BRANCH_HALT_DELAY,
955
+
.clkr = {
956
+
.enable_reg = 0x131d0,
957
+
.enable_mask = BIT(0),
958
+
.hw.init = &(const struct clk_init_data) {
959
+
.name = "cam_cc_core_ahb_clk",
960
+
.parent_hws = (const struct clk_hw*[]) {
961
+
&cam_cc_slow_ahb_clk_src.clkr.hw,
962
+
},
963
+
.num_parents = 1,
964
+
.flags = CLK_SET_RATE_PARENT,
965
+
.ops = &clk_branch2_ops,
966
+
},
967
+
},
968
+
};
969
+
970
+
static struct clk_branch cam_cc_cpas_ahb_clk = {
971
+
.halt_reg = 0x13110,
972
+
.halt_check = BRANCH_HALT,
973
+
.clkr = {
974
+
.enable_reg = 0x13110,
975
+
.enable_mask = BIT(0),
976
+
.hw.init = &(const struct clk_init_data) {
977
+
.name = "cam_cc_cpas_ahb_clk",
978
+
.parent_hws = (const struct clk_hw*[]) {
979
+
&cam_cc_slow_ahb_clk_src.clkr.hw,
980
+
},
981
+
.num_parents = 1,
982
+
.flags = CLK_SET_RATE_PARENT,
983
+
.ops = &clk_branch2_ops,
984
+
},
985
+
},
986
+
};
987
+
988
+
static struct clk_branch cam_cc_cpas_fast_ahb_clk = {
989
+
.halt_reg = 0x13118,
990
+
.halt_check = BRANCH_HALT,
991
+
.clkr = {
992
+
.enable_reg = 0x13118,
993
+
.enable_mask = BIT(0),
994
+
.hw.init = &(const struct clk_init_data) {
995
+
.name = "cam_cc_cpas_fast_ahb_clk",
996
+
.parent_hws = (const struct clk_hw*[]) {
997
+
&cam_cc_fast_ahb_clk_src.clkr.hw,
998
+
},
999
+
.num_parents = 1,
1000
+
.flags = CLK_SET_RATE_PARENT,
1001
+
.ops = &clk_branch2_ops,
1002
+
},
1003
+
},
1004
+
};
1005
+
1006
+
static struct clk_branch cam_cc_cpas_ife_0_clk = {
1007
+
.halt_reg = 0x11024,
1008
+
.halt_check = BRANCH_HALT,
1009
+
.clkr = {
1010
+
.enable_reg = 0x11024,
1011
+
.enable_mask = BIT(0),
1012
+
.hw.init = &(const struct clk_init_data) {
1013
+
.name = "cam_cc_cpas_ife_0_clk",
1014
+
.parent_hws = (const struct clk_hw*[]) {
1015
+
&cam_cc_ife_0_clk_src.clkr.hw,
1016
+
},
1017
+
.num_parents = 1,
1018
+
.flags = CLK_SET_RATE_PARENT,
1019
+
.ops = &clk_branch2_ops,
1020
+
},
1021
+
},
1022
+
};
1023
+
1024
+
static struct clk_branch cam_cc_cpas_ife_1_clk = {
1025
+
.halt_reg = 0x12024,
1026
+
.halt_check = BRANCH_HALT,
1027
+
.clkr = {
1028
+
.enable_reg = 0x12024,
1029
+
.enable_mask = BIT(0),
1030
+
.hw.init = &(const struct clk_init_data) {
1031
+
.name = "cam_cc_cpas_ife_1_clk",
1032
+
.parent_hws = (const struct clk_hw*[]) {
1033
+
&cam_cc_ife_1_clk_src.clkr.hw,
1034
+
},
1035
+
.num_parents = 1,
1036
+
.flags = CLK_SET_RATE_PARENT,
1037
+
.ops = &clk_branch2_ops,
1038
+
},
1039
+
},
1040
+
};
1041
+
1042
+
static struct clk_branch cam_cc_cpas_ife_lite_clk = {
1043
+
.halt_reg = 0x1301c,
1044
+
.halt_check = BRANCH_HALT,
1045
+
.clkr = {
1046
+
.enable_reg = 0x1301c,
1047
+
.enable_mask = BIT(0),
1048
+
.hw.init = &(const struct clk_init_data) {
1049
+
.name = "cam_cc_cpas_ife_lite_clk",
1050
+
.parent_hws = (const struct clk_hw*[]) {
1051
+
&cam_cc_ife_lite_clk_src.clkr.hw,
1052
+
},
1053
+
.num_parents = 1,
1054
+
.flags = CLK_SET_RATE_PARENT,
1055
+
.ops = &clk_branch2_ops,
1056
+
},
1057
+
},
1058
+
};
1059
+
1060
+
static struct clk_branch cam_cc_cpas_ipe_clk = {
1061
+
.halt_reg = 0x10024,
1062
+
.halt_check = BRANCH_HALT,
1063
+
.clkr = {
1064
+
.enable_reg = 0x10024,
1065
+
.enable_mask = BIT(0),
1066
+
.hw.init = &(const struct clk_init_data) {
1067
+
.name = "cam_cc_cpas_ipe_clk",
1068
+
.parent_hws = (const struct clk_hw*[]) {
1069
+
&cam_cc_ipe_clk_src.clkr.hw,
1070
+
},
1071
+
.num_parents = 1,
1072
+
.flags = CLK_SET_RATE_PARENT,
1073
+
.ops = &clk_branch2_ops,
1074
+
},
1075
+
},
1076
+
};
1077
+
1078
+
static struct clk_branch cam_cc_cpas_sfe_lite_0_clk = {
1079
+
.halt_reg = 0x13050,
1080
+
.halt_check = BRANCH_HALT,
1081
+
.clkr = {
1082
+
.enable_reg = 0x13050,
1083
+
.enable_mask = BIT(0),
1084
+
.hw.init = &(const struct clk_init_data) {
1085
+
.name = "cam_cc_cpas_sfe_lite_0_clk",
1086
+
.parent_hws = (const struct clk_hw*[]) {
1087
+
&cam_cc_ife_0_clk_src.clkr.hw,
1088
+
},
1089
+
.num_parents = 1,
1090
+
.flags = CLK_SET_RATE_PARENT,
1091
+
.ops = &clk_branch2_ops,
1092
+
},
1093
+
},
1094
+
};
1095
+
1096
+
static struct clk_branch cam_cc_cpas_sfe_lite_1_clk = {
1097
+
.halt_reg = 0x13068,
1098
+
.halt_check = BRANCH_HALT,
1099
+
.clkr = {
1100
+
.enable_reg = 0x13068,
1101
+
.enable_mask = BIT(0),
1102
+
.hw.init = &(const struct clk_init_data) {
1103
+
.name = "cam_cc_cpas_sfe_lite_1_clk",
1104
+
.parent_hws = (const struct clk_hw*[]) {
1105
+
&cam_cc_ife_1_clk_src.clkr.hw,
1106
+
},
1107
+
.num_parents = 1,
1108
+
.flags = CLK_SET_RATE_PARENT,
1109
+
.ops = &clk_branch2_ops,
1110
+
},
1111
+
},
1112
+
};
1113
+
1114
+
static struct clk_branch cam_cc_csi0phytimer_clk = {
1115
+
.halt_reg = 0x1508c,
1116
+
.halt_check = BRANCH_HALT,
1117
+
.clkr = {
1118
+
.enable_reg = 0x1508c,
1119
+
.enable_mask = BIT(0),
1120
+
.hw.init = &(const struct clk_init_data) {
1121
+
.name = "cam_cc_csi0phytimer_clk",
1122
+
.parent_hws = (const struct clk_hw*[]) {
1123
+
&cam_cc_csi0phytimer_clk_src.clkr.hw,
1124
+
},
1125
+
.num_parents = 1,
1126
+
.flags = CLK_SET_RATE_PARENT,
1127
+
.ops = &clk_branch2_ops,
1128
+
},
1129
+
},
1130
+
};
1131
+
1132
+
static struct clk_branch cam_cc_csi1phytimer_clk = {
1133
+
.halt_reg = 0x150b0,
1134
+
.halt_check = BRANCH_HALT,
1135
+
.clkr = {
1136
+
.enable_reg = 0x150b0,
1137
+
.enable_mask = BIT(0),
1138
+
.hw.init = &(const struct clk_init_data) {
1139
+
.name = "cam_cc_csi1phytimer_clk",
1140
+
.parent_hws = (const struct clk_hw*[]) {
1141
+
&cam_cc_csi1phytimer_clk_src.clkr.hw,
1142
+
},
1143
+
.num_parents = 1,
1144
+
.flags = CLK_SET_RATE_PARENT,
1145
+
.ops = &clk_branch2_ops,
1146
+
},
1147
+
},
1148
+
};
1149
+
1150
+
static struct clk_branch cam_cc_csi2phytimer_clk = {
1151
+
.halt_reg = 0x150d0,
1152
+
.halt_check = BRANCH_HALT,
1153
+
.clkr = {
1154
+
.enable_reg = 0x150d0,
1155
+
.enable_mask = BIT(0),
1156
+
.hw.init = &(const struct clk_init_data) {
1157
+
.name = "cam_cc_csi2phytimer_clk",
1158
+
.parent_hws = (const struct clk_hw*[]) {
1159
+
&cam_cc_csi2phytimer_clk_src.clkr.hw,
1160
+
},
1161
+
.num_parents = 1,
1162
+
.flags = CLK_SET_RATE_PARENT,
1163
+
.ops = &clk_branch2_ops,
1164
+
},
1165
+
},
1166
+
};
1167
+
1168
+
static struct clk_branch cam_cc_csi3phytimer_clk = {
1169
+
.halt_reg = 0x150f0,
1170
+
.halt_check = BRANCH_HALT,
1171
+
.clkr = {
1172
+
.enable_reg = 0x150f0,
1173
+
.enable_mask = BIT(0),
1174
+
.hw.init = &(const struct clk_init_data) {
1175
+
.name = "cam_cc_csi3phytimer_clk",
1176
+
.parent_hws = (const struct clk_hw*[]) {
1177
+
&cam_cc_csi3phytimer_clk_src.clkr.hw,
1178
+
},
1179
+
.num_parents = 1,
1180
+
.flags = CLK_SET_RATE_PARENT,
1181
+
.ops = &clk_branch2_ops,
1182
+
},
1183
+
},
1184
+
};
1185
+
1186
+
static struct clk_branch cam_cc_csid_clk = {
1187
+
.halt_reg = 0x13168,
1188
+
.halt_check = BRANCH_HALT,
1189
+
.clkr = {
1190
+
.enable_reg = 0x13168,
1191
+
.enable_mask = BIT(0),
1192
+
.hw.init = &(const struct clk_init_data) {
1193
+
.name = "cam_cc_csid_clk",
1194
+
.parent_hws = (const struct clk_hw*[]) {
1195
+
&cam_cc_csid_clk_src.clkr.hw,
1196
+
},
1197
+
.num_parents = 1,
1198
+
.flags = CLK_SET_RATE_PARENT,
1199
+
.ops = &clk_branch2_ops,
1200
+
},
1201
+
},
1202
+
};
1203
+
1204
+
static struct clk_branch cam_cc_csid_csiphy_rx_clk = {
1205
+
.halt_reg = 0x15094,
1206
+
.halt_check = BRANCH_HALT,
1207
+
.clkr = {
1208
+
.enable_reg = 0x15094,
1209
+
.enable_mask = BIT(0),
1210
+
.hw.init = &(const struct clk_init_data) {
1211
+
.name = "cam_cc_csid_csiphy_rx_clk",
1212
+
.parent_hws = (const struct clk_hw*[]) {
1213
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
1214
+
},
1215
+
.num_parents = 1,
1216
+
.flags = CLK_SET_RATE_PARENT,
1217
+
.ops = &clk_branch2_ops,
1218
+
},
1219
+
},
1220
+
};
1221
+
1222
+
static struct clk_branch cam_cc_csiphy0_clk = {
1223
+
.halt_reg = 0x15090,
1224
+
.halt_check = BRANCH_HALT,
1225
+
.clkr = {
1226
+
.enable_reg = 0x15090,
1227
+
.enable_mask = BIT(0),
1228
+
.hw.init = &(const struct clk_init_data) {
1229
+
.name = "cam_cc_csiphy0_clk",
1230
+
.parent_hws = (const struct clk_hw*[]) {
1231
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
1232
+
},
1233
+
.num_parents = 1,
1234
+
.flags = CLK_SET_RATE_PARENT,
1235
+
.ops = &clk_branch2_ops,
1236
+
},
1237
+
},
1238
+
};
1239
+
1240
+
static struct clk_branch cam_cc_csiphy1_clk = {
1241
+
.halt_reg = 0x150b4,
1242
+
.halt_check = BRANCH_HALT,
1243
+
.clkr = {
1244
+
.enable_reg = 0x150b4,
1245
+
.enable_mask = BIT(0),
1246
+
.hw.init = &(const struct clk_init_data) {
1247
+
.name = "cam_cc_csiphy1_clk",
1248
+
.parent_hws = (const struct clk_hw*[]) {
1249
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
1250
+
},
1251
+
.num_parents = 1,
1252
+
.flags = CLK_SET_RATE_PARENT,
1253
+
.ops = &clk_branch2_ops,
1254
+
},
1255
+
},
1256
+
};
1257
+
1258
+
static struct clk_branch cam_cc_csiphy2_clk = {
1259
+
.halt_reg = 0x150d4,
1260
+
.halt_check = BRANCH_HALT,
1261
+
.clkr = {
1262
+
.enable_reg = 0x150d4,
1263
+
.enable_mask = BIT(0),
1264
+
.hw.init = &(const struct clk_init_data) {
1265
+
.name = "cam_cc_csiphy2_clk",
1266
+
.parent_hws = (const struct clk_hw*[]) {
1267
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
1268
+
},
1269
+
.num_parents = 1,
1270
+
.flags = CLK_SET_RATE_PARENT,
1271
+
.ops = &clk_branch2_ops,
1272
+
},
1273
+
},
1274
+
};
1275
+
1276
+
static struct clk_branch cam_cc_csiphy3_clk = {
1277
+
.halt_reg = 0x150f4,
1278
+
.halt_check = BRANCH_HALT,
1279
+
.clkr = {
1280
+
.enable_reg = 0x150f4,
1281
+
.enable_mask = BIT(0),
1282
+
.hw.init = &(const struct clk_init_data) {
1283
+
.name = "cam_cc_csiphy3_clk",
1284
+
.parent_hws = (const struct clk_hw*[]) {
1285
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
1286
+
},
1287
+
.num_parents = 1,
1288
+
.flags = CLK_SET_RATE_PARENT,
1289
+
.ops = &clk_branch2_ops,
1290
+
},
1291
+
},
1292
+
};
1293
+
1294
+
static struct clk_branch cam_cc_icp_ahb_clk = {
1295
+
.halt_reg = 0x1309c,
1296
+
.halt_check = BRANCH_HALT,
1297
+
.clkr = {
1298
+
.enable_reg = 0x1309c,
1299
+
.enable_mask = BIT(0),
1300
+
.hw.init = &(const struct clk_init_data) {
1301
+
.name = "cam_cc_icp_ahb_clk",
1302
+
.parent_hws = (const struct clk_hw*[]) {
1303
+
&cam_cc_slow_ahb_clk_src.clkr.hw,
1304
+
},
1305
+
.num_parents = 1,
1306
+
.flags = CLK_SET_RATE_PARENT,
1307
+
.ops = &clk_branch2_ops,
1308
+
},
1309
+
},
1310
+
};
1311
+
1312
+
static struct clk_branch cam_cc_icp_clk = {
1313
+
.halt_reg = 0x13094,
1314
+
.halt_check = BRANCH_HALT,
1315
+
.clkr = {
1316
+
.enable_reg = 0x13094,
1317
+
.enable_mask = BIT(0),
1318
+
.hw.init = &(const struct clk_init_data) {
1319
+
.name = "cam_cc_icp_clk",
1320
+
.parent_hws = (const struct clk_hw*[]) {
1321
+
&cam_cc_icp_clk_src.clkr.hw,
1322
+
},
1323
+
.num_parents = 1,
1324
+
.flags = CLK_SET_RATE_PARENT,
1325
+
.ops = &clk_branch2_ops,
1326
+
},
1327
+
},
1328
+
};
1329
+
1330
+
static struct clk_branch cam_cc_ife_0_clk = {
1331
+
.halt_reg = 0x1101c,
1332
+
.halt_check = BRANCH_HALT,
1333
+
.clkr = {
1334
+
.enable_reg = 0x1101c,
1335
+
.enable_mask = BIT(0),
1336
+
.hw.init = &(const struct clk_init_data) {
1337
+
.name = "cam_cc_ife_0_clk",
1338
+
.parent_hws = (const struct clk_hw*[]) {
1339
+
&cam_cc_ife_0_clk_src.clkr.hw,
1340
+
},
1341
+
.num_parents = 1,
1342
+
.flags = CLK_SET_RATE_PARENT,
1343
+
.ops = &clk_branch2_ops,
1344
+
},
1345
+
},
1346
+
};
1347
+
1348
+
static struct clk_branch cam_cc_ife_0_fast_ahb_clk = {
1349
+
.halt_reg = 0x11030,
1350
+
.halt_check = BRANCH_HALT,
1351
+
.clkr = {
1352
+
.enable_reg = 0x11030,
1353
+
.enable_mask = BIT(0),
1354
+
.hw.init = &(const struct clk_init_data) {
1355
+
.name = "cam_cc_ife_0_fast_ahb_clk",
1356
+
.parent_hws = (const struct clk_hw*[]) {
1357
+
&cam_cc_fast_ahb_clk_src.clkr.hw,
1358
+
},
1359
+
.num_parents = 1,
1360
+
.flags = CLK_SET_RATE_PARENT,
1361
+
.ops = &clk_branch2_ops,
1362
+
},
1363
+
},
1364
+
};
1365
+
1366
+
static struct clk_branch cam_cc_ife_1_clk = {
1367
+
.halt_reg = 0x1201c,
1368
+
.halt_check = BRANCH_HALT,
1369
+
.clkr = {
1370
+
.enable_reg = 0x1201c,
1371
+
.enable_mask = BIT(0),
1372
+
.hw.init = &(const struct clk_init_data) {
1373
+
.name = "cam_cc_ife_1_clk",
1374
+
.parent_hws = (const struct clk_hw*[]) {
1375
+
&cam_cc_ife_1_clk_src.clkr.hw,
1376
+
},
1377
+
.num_parents = 1,
1378
+
.flags = CLK_SET_RATE_PARENT,
1379
+
.ops = &clk_branch2_ops,
1380
+
},
1381
+
},
1382
+
};
1383
+
1384
+
static struct clk_branch cam_cc_ife_1_fast_ahb_clk = {
1385
+
.halt_reg = 0x12030,
1386
+
.halt_check = BRANCH_HALT,
1387
+
.clkr = {
1388
+
.enable_reg = 0x12030,
1389
+
.enable_mask = BIT(0),
1390
+
.hw.init = &(const struct clk_init_data) {
1391
+
.name = "cam_cc_ife_1_fast_ahb_clk",
1392
+
.parent_hws = (const struct clk_hw*[]) {
1393
+
&cam_cc_fast_ahb_clk_src.clkr.hw,
1394
+
},
1395
+
.num_parents = 1,
1396
+
.flags = CLK_SET_RATE_PARENT,
1397
+
.ops = &clk_branch2_ops,
1398
+
},
1399
+
},
1400
+
};
1401
+
1402
+
static struct clk_branch cam_cc_ife_lite_ahb_clk = {
1403
+
.halt_reg = 0x13044,
1404
+
.halt_check = BRANCH_HALT,
1405
+
.clkr = {
1406
+
.enable_reg = 0x13044,
1407
+
.enable_mask = BIT(0),
1408
+
.hw.init = &(const struct clk_init_data) {
1409
+
.name = "cam_cc_ife_lite_ahb_clk",
1410
+
.parent_hws = (const struct clk_hw*[]) {
1411
+
&cam_cc_slow_ahb_clk_src.clkr.hw,
1412
+
},
1413
+
.num_parents = 1,
1414
+
.flags = CLK_SET_RATE_PARENT,
1415
+
.ops = &clk_branch2_ops,
1416
+
},
1417
+
},
1418
+
};
1419
+
1420
+
static struct clk_branch cam_cc_ife_lite_clk = {
1421
+
.halt_reg = 0x13018,
1422
+
.halt_check = BRANCH_HALT,
1423
+
.clkr = {
1424
+
.enable_reg = 0x13018,
1425
+
.enable_mask = BIT(0),
1426
+
.hw.init = &(const struct clk_init_data) {
1427
+
.name = "cam_cc_ife_lite_clk",
1428
+
.parent_hws = (const struct clk_hw*[]) {
1429
+
&cam_cc_ife_lite_clk_src.clkr.hw,
1430
+
},
1431
+
.num_parents = 1,
1432
+
.flags = CLK_SET_RATE_PARENT,
1433
+
.ops = &clk_branch2_ops,
1434
+
},
1435
+
},
1436
+
};
1437
+
1438
+
static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
1439
+
.halt_reg = 0x13040,
1440
+
.halt_check = BRANCH_HALT,
1441
+
.clkr = {
1442
+
.enable_reg = 0x13040,
1443
+
.enable_mask = BIT(0),
1444
+
.hw.init = &(const struct clk_init_data) {
1445
+
.name = "cam_cc_ife_lite_cphy_rx_clk",
1446
+
.parent_hws = (const struct clk_hw*[]) {
1447
+
&cam_cc_cphy_rx_clk_src.clkr.hw,
1448
+
},
1449
+
.num_parents = 1,
1450
+
.flags = CLK_SET_RATE_PARENT,
1451
+
.ops = &clk_branch2_ops,
1452
+
},
1453
+
},
1454
+
};
1455
+
1456
+
static struct clk_branch cam_cc_ife_lite_csid_clk = {
1457
+
.halt_reg = 0x13038,
1458
+
.halt_check = BRANCH_HALT,
1459
+
.clkr = {
1460
+
.enable_reg = 0x13038,
1461
+
.enable_mask = BIT(0),
1462
+
.hw.init = &(const struct clk_init_data) {
1463
+
.name = "cam_cc_ife_lite_csid_clk",
1464
+
.parent_hws = (const struct clk_hw*[]) {
1465
+
&cam_cc_ife_lite_csid_clk_src.clkr.hw,
1466
+
},
1467
+
.num_parents = 1,
1468
+
.flags = CLK_SET_RATE_PARENT,
1469
+
.ops = &clk_branch2_ops,
1470
+
},
1471
+
},
1472
+
};
1473
+
1474
+
static struct clk_branch cam_cc_ipe_ahb_clk = {
1475
+
.halt_reg = 0x10030,
1476
+
.halt_check = BRANCH_HALT,
1477
+
.clkr = {
1478
+
.enable_reg = 0x10030,
1479
+
.enable_mask = BIT(0),
1480
+
.hw.init = &(const struct clk_init_data) {
1481
+
.name = "cam_cc_ipe_ahb_clk",
1482
+
.parent_hws = (const struct clk_hw*[]) {
1483
+
&cam_cc_slow_ahb_clk_src.clkr.hw,
1484
+
},
1485
+
.num_parents = 1,
1486
+
.flags = CLK_SET_RATE_PARENT,
1487
+
.ops = &clk_branch2_ops,
1488
+
},
1489
+
},
1490
+
};
1491
+
1492
+
static struct clk_branch cam_cc_ipe_clk = {
1493
+
.halt_reg = 0x1001c,
1494
+
.halt_check = BRANCH_HALT,
1495
+
.clkr = {
1496
+
.enable_reg = 0x1001c,
1497
+
.enable_mask = BIT(0),
1498
+
.hw.init = &(const struct clk_init_data) {
1499
+
.name = "cam_cc_ipe_clk",
1500
+
.parent_hws = (const struct clk_hw*[]) {
1501
+
&cam_cc_ipe_clk_src.clkr.hw,
1502
+
},
1503
+
.num_parents = 1,
1504
+
.flags = CLK_SET_RATE_PARENT,
1505
+
.ops = &clk_branch2_ops,
1506
+
},
1507
+
},
1508
+
};
1509
+
1510
+
static struct clk_branch cam_cc_ipe_fast_ahb_clk = {
1511
+
.halt_reg = 0x10034,
1512
+
.halt_check = BRANCH_HALT,
1513
+
.clkr = {
1514
+
.enable_reg = 0x10034,
1515
+
.enable_mask = BIT(0),
1516
+
.hw.init = &(const struct clk_init_data) {
1517
+
.name = "cam_cc_ipe_fast_ahb_clk",
1518
+
.parent_hws = (const struct clk_hw*[]) {
1519
+
&cam_cc_fast_ahb_clk_src.clkr.hw,
1520
+
},
1521
+
.num_parents = 1,
1522
+
.flags = CLK_SET_RATE_PARENT,
1523
+
.ops = &clk_branch2_ops,
1524
+
},
1525
+
},
1526
+
};
1527
+
1528
+
static struct clk_branch cam_cc_mclk0_clk = {
1529
+
.halt_reg = 0x1501c,
1530
+
.halt_check = BRANCH_HALT,
1531
+
.clkr = {
1532
+
.enable_reg = 0x1501c,
1533
+
.enable_mask = BIT(0),
1534
+
.hw.init = &(const struct clk_init_data) {
1535
+
.name = "cam_cc_mclk0_clk",
1536
+
.parent_hws = (const struct clk_hw*[]) {
1537
+
&cam_cc_mclk0_clk_src.clkr.hw,
1538
+
},
1539
+
.num_parents = 1,
1540
+
.flags = CLK_SET_RATE_PARENT,
1541
+
.ops = &clk_branch2_ops,
1542
+
},
1543
+
},
1544
+
};
1545
+
1546
+
static struct clk_branch cam_cc_mclk1_clk = {
1547
+
.halt_reg = 0x15038,
1548
+
.halt_check = BRANCH_HALT,
1549
+
.clkr = {
1550
+
.enable_reg = 0x15038,
1551
+
.enable_mask = BIT(0),
1552
+
.hw.init = &(const struct clk_init_data) {
1553
+
.name = "cam_cc_mclk1_clk",
1554
+
.parent_hws = (const struct clk_hw*[]) {
1555
+
&cam_cc_mclk1_clk_src.clkr.hw,
1556
+
},
1557
+
.num_parents = 1,
1558
+
.flags = CLK_SET_RATE_PARENT,
1559
+
.ops = &clk_branch2_ops,
1560
+
},
1561
+
},
1562
+
};
1563
+
1564
+
static struct clk_branch cam_cc_mclk2_clk = {
1565
+
.halt_reg = 0x15054,
1566
+
.halt_check = BRANCH_HALT,
1567
+
.clkr = {
1568
+
.enable_reg = 0x15054,
1569
+
.enable_mask = BIT(0),
1570
+
.hw.init = &(const struct clk_init_data) {
1571
+
.name = "cam_cc_mclk2_clk",
1572
+
.parent_hws = (const struct clk_hw*[]) {
1573
+
&cam_cc_mclk2_clk_src.clkr.hw,
1574
+
},
1575
+
.num_parents = 1,
1576
+
.flags = CLK_SET_RATE_PARENT,
1577
+
.ops = &clk_branch2_ops,
1578
+
},
1579
+
},
1580
+
};
1581
+
1582
+
static struct clk_branch cam_cc_mclk3_clk = {
1583
+
.halt_reg = 0x15070,
1584
+
.halt_check = BRANCH_HALT,
1585
+
.clkr = {
1586
+
.enable_reg = 0x15070,
1587
+
.enable_mask = BIT(0),
1588
+
.hw.init = &(const struct clk_init_data) {
1589
+
.name = "cam_cc_mclk3_clk",
1590
+
.parent_hws = (const struct clk_hw*[]) {
1591
+
&cam_cc_mclk3_clk_src.clkr.hw,
1592
+
},
1593
+
.num_parents = 1,
1594
+
.flags = CLK_SET_RATE_PARENT,
1595
+
.ops = &clk_branch2_ops,
1596
+
},
1597
+
},
1598
+
};
1599
+
1600
+
static struct clk_branch cam_cc_sfe_lite_0_clk = {
1601
+
.halt_reg = 0x1304c,
1602
+
.halt_check = BRANCH_HALT,
1603
+
.clkr = {
1604
+
.enable_reg = 0x1304c,
1605
+
.enable_mask = BIT(0),
1606
+
.hw.init = &(const struct clk_init_data) {
1607
+
.name = "cam_cc_sfe_lite_0_clk",
1608
+
.parent_hws = (const struct clk_hw*[]) {
1609
+
&cam_cc_ife_0_clk_src.clkr.hw,
1610
+
},
1611
+
.num_parents = 1,
1612
+
.flags = CLK_SET_RATE_PARENT,
1613
+
.ops = &clk_branch2_ops,
1614
+
},
1615
+
},
1616
+
};
1617
+
1618
+
static struct clk_branch cam_cc_sfe_lite_0_fast_ahb_clk = {
1619
+
.halt_reg = 0x1305c,
1620
+
.halt_check = BRANCH_HALT,
1621
+
.clkr = {
1622
+
.enable_reg = 0x1305c,
1623
+
.enable_mask = BIT(0),
1624
+
.hw.init = &(const struct clk_init_data) {
1625
+
.name = "cam_cc_sfe_lite_0_fast_ahb_clk",
1626
+
.parent_hws = (const struct clk_hw*[]) {
1627
+
&cam_cc_fast_ahb_clk_src.clkr.hw,
1628
+
},
1629
+
.num_parents = 1,
1630
+
.flags = CLK_SET_RATE_PARENT,
1631
+
.ops = &clk_branch2_ops,
1632
+
},
1633
+
},
1634
+
};
1635
+
1636
+
static struct clk_branch cam_cc_sfe_lite_1_clk = {
1637
+
.halt_reg = 0x13064,
1638
+
.halt_check = BRANCH_HALT,
1639
+
.clkr = {
1640
+
.enable_reg = 0x13064,
1641
+
.enable_mask = BIT(0),
1642
+
.hw.init = &(const struct clk_init_data) {
1643
+
.name = "cam_cc_sfe_lite_1_clk",
1644
+
.parent_hws = (const struct clk_hw*[]) {
1645
+
&cam_cc_ife_1_clk_src.clkr.hw,
1646
+
},
1647
+
.num_parents = 1,
1648
+
.flags = CLK_SET_RATE_PARENT,
1649
+
.ops = &clk_branch2_ops,
1650
+
},
1651
+
},
1652
+
};
1653
+
1654
+
static struct clk_branch cam_cc_sfe_lite_1_fast_ahb_clk = {
1655
+
.halt_reg = 0x13074,
1656
+
.halt_check = BRANCH_HALT,
1657
+
.clkr = {
1658
+
.enable_reg = 0x13074,
1659
+
.enable_mask = BIT(0),
1660
+
.hw.init = &(const struct clk_init_data) {
1661
+
.name = "cam_cc_sfe_lite_1_fast_ahb_clk",
1662
+
.parent_hws = (const struct clk_hw*[]) {
1663
+
&cam_cc_fast_ahb_clk_src.clkr.hw,
1664
+
},
1665
+
.num_parents = 1,
1666
+
.flags = CLK_SET_RATE_PARENT,
1667
+
.ops = &clk_branch2_ops,
1668
+
},
1669
+
},
1670
+
};
1671
+
1672
+
static struct clk_branch cam_cc_sm_obs_clk = {
1673
+
.halt_reg = 0x1510c,
1674
+
.halt_check = BRANCH_HALT_SKIP,
1675
+
.clkr = {
1676
+
.enable_reg = 0x1510c,
1677
+
.enable_mask = BIT(0),
1678
+
.hw.init = &(const struct clk_init_data) {
1679
+
.name = "cam_cc_sm_obs_clk",
1680
+
.ops = &clk_branch2_ops,
1681
+
},
1682
+
},
1683
+
};
1684
+
1685
+
static struct gdsc cam_cc_titan_top_gdsc = {
1686
+
.gdscr = 0x131bc,
1687
+
.en_rest_wait_val = 0x2,
1688
+
.en_few_wait_val = 0x2,
1689
+
.clk_dis_wait_val = 0xf,
1690
+
.pd = {
1691
+
.name = "cam_cc_titan_top_gdsc",
1692
+
},
1693
+
.pwrsts = PWRSTS_OFF_ON,
1694
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
1695
+
};
1696
+
1697
+
static struct clk_regmap *cam_cc_sa8775p_clocks[] = {
1698
+
[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
1699
+
[CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
1700
+
[CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
1701
+
[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
1702
+
[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
1703
+
[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
1704
+
[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
1705
+
[CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr,
1706
+
[CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr,
1707
+
[CAM_CC_CCI_3_CLK] = &cam_cc_cci_3_clk.clkr,
1708
+
[CAM_CC_CCI_3_CLK_SRC] = &cam_cc_cci_3_clk_src.clkr,
1709
+
[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
1710
+
[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
1711
+
[CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr,
1712
+
[CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr,
1713
+
[CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr,
1714
+
[CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr,
1715
+
[CAM_CC_CPAS_IPE_CLK] = &cam_cc_cpas_ipe_clk.clkr,
1716
+
[CAM_CC_CPAS_SFE_LITE_0_CLK] = &cam_cc_cpas_sfe_lite_0_clk.clkr,
1717
+
[CAM_CC_CPAS_SFE_LITE_1_CLK] = &cam_cc_cpas_sfe_lite_1_clk.clkr,
1718
+
[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
1719
+
[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
1720
+
[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
1721
+
[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
1722
+
[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
1723
+
[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
1724
+
[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
1725
+
[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
1726
+
[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
1727
+
[CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr,
1728
+
[CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr,
1729
+
[CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr,
1730
+
[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
1731
+
[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
1732
+
[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
1733
+
[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
1734
+
[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
1735
+
[CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
1736
+
[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
1737
+
[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
1738
+
[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
1739
+
[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
1740
+
[CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr,
1741
+
[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
1742
+
[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
1743
+
[CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr,
1744
+
[CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr,
1745
+
[CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
1746
+
[CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
1747
+
[CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
1748
+
[CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
1749
+
[CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
1750
+
[CAM_CC_IPE_AHB_CLK] = &cam_cc_ipe_ahb_clk.clkr,
1751
+
[CAM_CC_IPE_CLK] = &cam_cc_ipe_clk.clkr,
1752
+
[CAM_CC_IPE_CLK_SRC] = &cam_cc_ipe_clk_src.clkr,
1753
+
[CAM_CC_IPE_FAST_AHB_CLK] = &cam_cc_ipe_fast_ahb_clk.clkr,
1754
+
[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
1755
+
[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
1756
+
[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
1757
+
[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
1758
+
[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
1759
+
[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
1760
+
[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
1761
+
[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
1762
+
[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
1763
+
[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
1764
+
[CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
1765
+
[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
1766
+
[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
1767
+
[CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
1768
+
[CAM_CC_PLL4] = &cam_cc_pll4.clkr,
1769
+
[CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
1770
+
[CAM_CC_PLL5] = &cam_cc_pll5.clkr,
1771
+
[CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr,
1772
+
[CAM_CC_SFE_LITE_0_CLK] = &cam_cc_sfe_lite_0_clk.clkr,
1773
+
[CAM_CC_SFE_LITE_0_FAST_AHB_CLK] = &cam_cc_sfe_lite_0_fast_ahb_clk.clkr,
1774
+
[CAM_CC_SFE_LITE_1_CLK] = &cam_cc_sfe_lite_1_clk.clkr,
1775
+
[CAM_CC_SFE_LITE_1_FAST_AHB_CLK] = &cam_cc_sfe_lite_1_fast_ahb_clk.clkr,
1776
+
[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
1777
+
[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
1778
+
[CAM_CC_SM_OBS_CLK] = &cam_cc_sm_obs_clk.clkr,
1779
+
[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
1780
+
[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
1781
+
};
1782
+
1783
+
static struct gdsc *cam_cc_sa8775p_gdscs[] = {
1784
+
[CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc,
1785
+
};
1786
+
1787
+
static const struct qcom_reset_map cam_cc_sa8775p_resets[] = {
1788
+
[CAM_CC_ICP_BCR] = { 0x13078 },
1789
+
[CAM_CC_IFE_0_BCR] = { 0x11000 },
1790
+
[CAM_CC_IFE_1_BCR] = { 0x12000 },
1791
+
[CAM_CC_IPE_0_BCR] = { 0x10000 },
1792
+
[CAM_CC_SFE_LITE_0_BCR] = { 0x13048 },
1793
+
[CAM_CC_SFE_LITE_1_BCR] = { 0x13060 },
1794
+
};
1795
+
1796
+
static const struct regmap_config cam_cc_sa8775p_regmap_config = {
1797
+
.reg_bits = 32,
1798
+
.reg_stride = 4,
1799
+
.val_bits = 32,
1800
+
.max_register = 0x16218,
1801
+
.fast_io = true,
1802
+
};
1803
+
1804
+
static struct qcom_cc_desc cam_cc_sa8775p_desc = {
1805
+
.config = &cam_cc_sa8775p_regmap_config,
1806
+
.clks = cam_cc_sa8775p_clocks,
1807
+
.num_clks = ARRAY_SIZE(cam_cc_sa8775p_clocks),
1808
+
.resets = cam_cc_sa8775p_resets,
1809
+
.num_resets = ARRAY_SIZE(cam_cc_sa8775p_resets),
1810
+
.gdscs = cam_cc_sa8775p_gdscs,
1811
+
.num_gdscs = ARRAY_SIZE(cam_cc_sa8775p_gdscs),
1812
+
};
1813
+
1814
+
static const struct of_device_id cam_cc_sa8775p_match_table[] = {
1815
+
{ .compatible = "qcom,sa8775p-camcc" },
1816
+
{ }
1817
+
};
1818
+
MODULE_DEVICE_TABLE(of, cam_cc_sa8775p_match_table);
1819
+
1820
+
static int cam_cc_sa8775p_probe(struct platform_device *pdev)
1821
+
{
1822
+
struct regmap *regmap;
1823
+
int ret;
1824
+
1825
+
ret = devm_pm_runtime_enable(&pdev->dev);
1826
+
if (ret)
1827
+
return ret;
1828
+
1829
+
ret = pm_runtime_resume_and_get(&pdev->dev);
1830
+
if (ret)
1831
+
return ret;
1832
+
1833
+
regmap = qcom_cc_map(pdev, &cam_cc_sa8775p_desc);
1834
+
if (IS_ERR(regmap)) {
1835
+
pm_runtime_put(&pdev->dev);
1836
+
return PTR_ERR(regmap);
1837
+
}
1838
+
1839
+
clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
1840
+
clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
1841
+
clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
1842
+
clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
1843
+
clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
1844
+
1845
+
/* Keep some clocks always enabled */
1846
+
qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */
1847
+
qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */
1848
+
qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */
1849
+
1850
+
ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap);
1851
+
1852
+
pm_runtime_put(&pdev->dev);
1853
+
1854
+
return ret;
1855
+
}
1856
+
1857
+
static struct platform_driver cam_cc_sa8775p_driver = {
1858
+
.probe = cam_cc_sa8775p_probe,
1859
+
.driver = {
1860
+
.name = "camcc-sa8775p",
1861
+
.of_match_table = cam_cc_sa8775p_match_table,
1862
+
},
1863
+
};
1864
+
1865
+
module_platform_driver(cam_cc_sa8775p_driver);
1866
+
1867
+
MODULE_DESCRIPTION("QTI CAMCC SA8775P Driver");
1868
+
MODULE_LICENSE("GPL");