Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Kevin Hilman:
"A fairly random colletion of fixes based on -rc1 for OMAP, sunxi and
prima2 as well as a few arm64-specific DT fixes.
This series also includes a late to support a new Allwinner (sunxi)
SoC, but since it's rather simple and isolated to the
platform-specific code, it's included it for this -rc"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
arm64: dts: add device tree for ARM SMM-A53x2 on LogicTile Express 20MG
arm: dts: vexpress: add missing CCI PMU device node to TC2
arm: dts: vexpress: describe all PMUs in TC2 dts
GICv3: Add ITS entry to THUNDER dts
arm64: dts: Add poweroff button device node for APM X-Gene platform
ARM: dts: am4372.dtsi: disable rfbi
ARM: dts: am57xx-beagle-x15: Provide supply for usb2_phy2
ARM: dts: am4372: Add emif node
Revert "ARM: dts: am335x-boneblack: disable RTC-only sleep"
ARM: sunxi: Enable simplefb in the defconfig
ARM: Remove deprecated symbol from defconfig files
ARM: sunxi: Add Machine support for A33
ARM: sunxi: Introduce Allwinner H3 support
Documentation: sunxi: Update Allwinner SoC documentation
ARM: prima2: move to use REGMAP APIs for rtciobrg
ARM: dts: atlas7: add pinctrl and gpio descriptions
ARM: OMAP2+: Remove unnessary return statement from the void function, omap2_show_dma_caps
memory: omap-gpmc: Fix parsing of devices
+1373
-19
+17
-1
Documentation/arm/sunxi/README
+17
-1
Documentation/arm/sunxi/README
···
36
36
+ User Manual
37
37
http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf
38
38
39
-
- Allwinner A23
39
+
- Allwinner A23 (sun8i)
40
40
+ Datasheet
41
41
http://dl.linux-sunxi.org/A23/A23%20Datasheet%20V1.0%2020130830.pdf
42
42
+ User Manual
···
55
55
+ User Manual
56
56
http://dl.linux-sunxi.org/A31/A3x_release_document/A31s/IC/A31s%20User%20Manual%20%20V1.0%2020130322.pdf
57
57
58
+
- Allwinner A33 (sun8i)
59
+
+ Datasheet
60
+
http://dl.linux-sunxi.org/A33/A33%20Datasheet%20release%201.1.pdf
61
+
+ User Manual
62
+
http://dl.linux-sunxi.org/A33/A33%20user%20manual%20release%201.1.pdf
63
+
64
+
- Allwinner H3 (sun8i)
65
+
+ Datasheet
66
+
http://dl.linux-sunxi.org/H3/Allwinner_H3_Datasheet_V1.0.pdf
67
+
58
68
* Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
59
69
- Allwinner A80
60
70
+ Datasheet
61
71
http://dl.linux-sunxi.org/A80/A80_Datasheet_Revision_1.0_0404.pdf
72
+
73
+
* Octa ARM Cortex-A7 based SoCs
74
+
- Allwinner A83T
75
+
+ Not Supported
76
+
+ Datasheet
77
+
http://dl.linux-sunxi.org/A83T/A83T_datasheet_Revision_1.1.pdf
+2
Documentation/devicetree/bindings/arm/sunxi.txt
+2
Documentation/devicetree/bindings/arm/sunxi.txt
+1
Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
+1
Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
···
8
8
Required properties:
9
9
- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
10
10
is the IP revision of the specific EMIF instance.
11
+
For am437x should be ti,emif-am4372.
11
12
12
13
- phy-type : <u32> indicating the DDR phy type. Following are the
13
14
allowed values
+1
MAINTAINERS
+1
MAINTAINERS
+4
arch/arm/boot/dts/am335x-boneblack.dts
+4
arch/arm/boot/dts/am335x-boneblack.dts
+7
arch/arm/boot/dts/am4372.dtsi
+7
arch/arm/boot/dts/am4372.dtsi
···
132
132
};
133
133
};
134
134
135
+
emif: emif@4c000000 {
136
+
compatible = "ti,emif-am4372";
137
+
reg = <0x4c000000 0x1000000>;
138
+
ti,hwmods = "emif";
139
+
};
140
+
135
141
edma: edma@49000000 {
136
142
compatible = "ti,edma3";
137
143
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
···
947
941
ti,hwmods = "dss_rfbi";
948
942
clocks = <&disp_clk>;
949
943
clock-names = "fck";
944
+
status = "disabled";
950
945
};
951
946
};
952
947
+4
arch/arm/boot/dts/am57xx-beagle-x15.dts
+4
arch/arm/boot/dts/am57xx-beagle-x15.dts
+1041
-1
arch/arm/boot/dts/atlas7.dtsi
+1041
-1
arch/arm/boot/dts/atlas7.dtsi
···
135
135
compatible = "sirf,atlas7-ioc";
136
136
reg = <0x18880000 0x1000>,
137
137
<0x10E40000 0x1000>;
138
+
139
+
audio_ac97_pmx: audio_ac97@0 {
140
+
audio_ac97 {
141
+
groups = "audio_ac97_grp";
142
+
function = "audio_ac97";
143
+
};
144
+
};
145
+
146
+
audio_func_dbg_pmx: audio_func_dbg@0 {
147
+
audio_func_dbg {
148
+
groups = "audio_func_dbg_grp";
149
+
function = "audio_func_dbg";
150
+
};
151
+
};
152
+
153
+
audio_i2s_pmx: audio_i2s@0 {
154
+
audio_i2s {
155
+
groups = "audio_i2s_grp";
156
+
function = "audio_i2s";
157
+
};
158
+
};
159
+
160
+
audio_i2s_2ch_pmx: audio_i2s_2ch@0 {
161
+
audio_i2s_2ch {
162
+
groups = "audio_i2s_2ch_grp";
163
+
function = "audio_i2s_2ch";
164
+
};
165
+
};
166
+
167
+
audio_i2s_extclk_pmx: audio_i2s_extclk@0 {
168
+
audio_i2s_extclk {
169
+
groups = "audio_i2s_extclk_grp";
170
+
function = "audio_i2s_extclk";
171
+
};
172
+
};
173
+
174
+
audio_uart0_pmx: audio_uart0@0 {
175
+
audio_uart0 {
176
+
groups = "audio_uart0_grp";
177
+
function = "audio_uart0";
178
+
};
179
+
};
180
+
181
+
audio_uart1_pmx: audio_uart1@0 {
182
+
audio_uart1 {
183
+
groups = "audio_uart1_grp";
184
+
function = "audio_uart1";
185
+
};
186
+
};
187
+
188
+
audio_uart2_pmx0: audio_uart2@0 {
189
+
audio_uart2_0 {
190
+
groups = "audio_uart2_grp0";
191
+
function = "audio_uart2_m0";
192
+
};
193
+
};
194
+
195
+
audio_uart2_pmx1: audio_uart2@1 {
196
+
audio_uart2_1 {
197
+
groups = "audio_uart2_grp1";
198
+
function = "audio_uart2_m1";
199
+
};
200
+
};
201
+
202
+
c_can_trnsvr_pmx: c_can_trnsvr@0 {
203
+
c_can_trnsvr {
204
+
groups = "c_can_trnsvr_grp";
205
+
function = "c_can_trnsvr";
206
+
};
207
+
};
208
+
209
+
c0_can_pmx0: c0_can@0 {
210
+
c0_can_0 {
211
+
groups = "c0_can_grp0";
212
+
function = "c0_can_m0";
213
+
};
214
+
};
215
+
216
+
c0_can_pmx1: c0_can@1 {
217
+
c0_can_1 {
218
+
groups = "c0_can_grp1";
219
+
function = "c0_can_m1";
220
+
};
221
+
};
222
+
223
+
c1_can_pmx0: c1_can@0 {
224
+
c1_can_0 {
225
+
groups = "c1_can_grp0";
226
+
function = "c1_can_m0";
227
+
};
228
+
};
229
+
230
+
c1_can_pmx1: c1_can@1 {
231
+
c1_can_1 {
232
+
groups = "c1_can_grp1";
233
+
function = "c1_can_m1";
234
+
};
235
+
};
236
+
237
+
c1_can_pmx2: c1_can@2 {
238
+
c1_can_2 {
239
+
groups = "c1_can_grp2";
240
+
function = "c1_can_m2";
241
+
};
242
+
};
243
+
244
+
ca_audio_lpc_pmx: ca_audio_lpc@0 {
245
+
ca_audio_lpc {
246
+
groups = "ca_audio_lpc_grp";
247
+
function = "ca_audio_lpc";
248
+
};
249
+
};
250
+
251
+
ca_bt_lpc_pmx: ca_bt_lpc@0 {
252
+
ca_bt_lpc {
253
+
groups = "ca_bt_lpc_grp";
254
+
function = "ca_bt_lpc";
255
+
};
256
+
};
257
+
258
+
ca_coex_pmx: ca_coex@0 {
259
+
ca_coex {
260
+
groups = "ca_coex_grp";
261
+
function = "ca_coex";
262
+
};
263
+
};
264
+
265
+
ca_curator_lpc_pmx: ca_curator_lpc@0 {
266
+
ca_curator_lpc {
267
+
groups = "ca_curator_lpc_grp";
268
+
function = "ca_curator_lpc";
269
+
};
270
+
};
271
+
272
+
ca_pcm_debug_pmx: ca_pcm_debug@0 {
273
+
ca_pcm_debug {
274
+
groups = "ca_pcm_debug_grp";
275
+
function = "ca_pcm_debug";
276
+
};
277
+
};
278
+
279
+
ca_pio_pmx: ca_pio@0 {
280
+
ca_pio {
281
+
groups = "ca_pio_grp";
282
+
function = "ca_pio";
283
+
};
284
+
};
285
+
286
+
ca_sdio_debug_pmx: ca_sdio_debug@0 {
287
+
ca_sdio_debug {
288
+
groups = "ca_sdio_debug_grp";
289
+
function = "ca_sdio_debug";
290
+
};
291
+
};
292
+
293
+
ca_spi_pmx: ca_spi@0 {
294
+
ca_spi {
295
+
groups = "ca_spi_grp";
296
+
function = "ca_spi";
297
+
};
298
+
};
299
+
300
+
ca_trb_pmx: ca_trb@0 {
301
+
ca_trb {
302
+
groups = "ca_trb_grp";
303
+
function = "ca_trb";
304
+
};
305
+
};
306
+
307
+
ca_uart_debug_pmx: ca_uart_debug@0 {
308
+
ca_uart_debug {
309
+
groups = "ca_uart_debug_grp";
310
+
function = "ca_uart_debug";
311
+
};
312
+
};
313
+
314
+
clkc_pmx0: clkc@0 {
315
+
clkc_0 {
316
+
groups = "clkc_grp0";
317
+
function = "clkc_m0";
318
+
};
319
+
};
320
+
321
+
clkc_pmx1: clkc@1 {
322
+
clkc_1 {
323
+
groups = "clkc_grp1";
324
+
function = "clkc_m1";
325
+
};
326
+
};
327
+
328
+
gn_gnss_i2c_pmx: gn_gnss_i2c@0 {
329
+
gn_gnss_i2c {
330
+
groups = "gn_gnss_i2c_grp";
331
+
function = "gn_gnss_i2c";
332
+
};
333
+
};
334
+
335
+
gn_gnss_uart_nopause_pmx: gn_gnss_uart_nopause@0 {
336
+
gn_gnss_uart_nopause {
337
+
groups = "gn_gnss_uart_nopause_grp";
338
+
function = "gn_gnss_uart_nopause";
339
+
};
340
+
};
341
+
342
+
gn_gnss_uart_pmx: gn_gnss_uart@0 {
343
+
gn_gnss_uart {
344
+
groups = "gn_gnss_uart_grp";
345
+
function = "gn_gnss_uart";
346
+
};
347
+
};
348
+
349
+
gn_trg_spi_pmx0: gn_trg_spi@0 {
350
+
gn_trg_spi_0 {
351
+
groups = "gn_trg_spi_grp0";
352
+
function = "gn_trg_spi_m0";
353
+
};
354
+
};
355
+
356
+
gn_trg_spi_pmx1: gn_trg_spi@1 {
357
+
gn_trg_spi_1 {
358
+
groups = "gn_trg_spi_grp1";
359
+
function = "gn_trg_spi_m1";
360
+
};
361
+
};
362
+
363
+
cvbs_dbg_pmx: cvbs_dbg@0 {
364
+
cvbs_dbg {
365
+
groups = "cvbs_dbg_grp";
366
+
function = "cvbs_dbg";
367
+
};
368
+
};
369
+
370
+
cvbs_dbg_test_pmx0: cvbs_dbg_test@0 {
371
+
cvbs_dbg_test_0 {
372
+
groups = "cvbs_dbg_test_grp0";
373
+
function = "cvbs_dbg_test_m0";
374
+
};
375
+
};
376
+
377
+
cvbs_dbg_test_pmx1: cvbs_dbg_test@1 {
378
+
cvbs_dbg_test_1 {
379
+
groups = "cvbs_dbg_test_grp1";
380
+
function = "cvbs_dbg_test_m1";
381
+
};
382
+
};
383
+
384
+
cvbs_dbg_test_pmx2: cvbs_dbg_test@2 {
385
+
cvbs_dbg_test_2 {
386
+
groups = "cvbs_dbg_test_grp2";
387
+
function = "cvbs_dbg_test_m2";
388
+
};
389
+
};
390
+
391
+
cvbs_dbg_test_pmx3: cvbs_dbg_test@3 {
392
+
cvbs_dbg_test_3 {
393
+
groups = "cvbs_dbg_test_grp3";
394
+
function = "cvbs_dbg_test_m3";
395
+
};
396
+
};
397
+
398
+
cvbs_dbg_test_pmx4: cvbs_dbg_test@4 {
399
+
cvbs_dbg_test_4 {
400
+
groups = "cvbs_dbg_test_grp4";
401
+
function = "cvbs_dbg_test_m4";
402
+
};
403
+
};
404
+
405
+
cvbs_dbg_test_pmx5: cvbs_dbg_test@5 {
406
+
cvbs_dbg_test_5 {
407
+
groups = "cvbs_dbg_test_grp5";
408
+
function = "cvbs_dbg_test_m5";
409
+
};
410
+
};
411
+
412
+
cvbs_dbg_test_pmx6: cvbs_dbg_test@6 {
413
+
cvbs_dbg_test_6 {
414
+
groups = "cvbs_dbg_test_grp6";
415
+
function = "cvbs_dbg_test_m6";
416
+
};
417
+
};
418
+
419
+
cvbs_dbg_test_pmx7: cvbs_dbg_test@7 {
420
+
cvbs_dbg_test_7 {
421
+
groups = "cvbs_dbg_test_grp7";
422
+
function = "cvbs_dbg_test_m7";
423
+
};
424
+
};
425
+
426
+
cvbs_dbg_test_pmx8: cvbs_dbg_test@8 {
427
+
cvbs_dbg_test_8 {
428
+
groups = "cvbs_dbg_test_grp8";
429
+
function = "cvbs_dbg_test_m8";
430
+
};
431
+
};
432
+
433
+
cvbs_dbg_test_pmx9: cvbs_dbg_test@9 {
434
+
cvbs_dbg_test_9 {
435
+
groups = "cvbs_dbg_test_grp9";
436
+
function = "cvbs_dbg_test_m9";
437
+
};
438
+
};
439
+
440
+
cvbs_dbg_test_pmx10: cvbs_dbg_test@10 {
441
+
cvbs_dbg_test_10 {
442
+
groups = "cvbs_dbg_test_grp10";
443
+
function = "cvbs_dbg_test_m10";
444
+
};
445
+
};
446
+
447
+
cvbs_dbg_test_pmx11: cvbs_dbg_test@11 {
448
+
cvbs_dbg_test_11 {
449
+
groups = "cvbs_dbg_test_grp11";
450
+
function = "cvbs_dbg_test_m11";
451
+
};
452
+
};
453
+
454
+
cvbs_dbg_test_pmx12: cvbs_dbg_test@12 {
455
+
cvbs_dbg_test_12 {
456
+
groups = "cvbs_dbg_test_grp12";
457
+
function = "cvbs_dbg_test_m12";
458
+
};
459
+
};
460
+
461
+
cvbs_dbg_test_pmx13: cvbs_dbg_test@13 {
462
+
cvbs_dbg_test_13 {
463
+
groups = "cvbs_dbg_test_grp13";
464
+
function = "cvbs_dbg_test_m13";
465
+
};
466
+
};
467
+
468
+
cvbs_dbg_test_pmx14: cvbs_dbg_test@14 {
469
+
cvbs_dbg_test_14 {
470
+
groups = "cvbs_dbg_test_grp14";
471
+
function = "cvbs_dbg_test_m14";
472
+
};
473
+
};
474
+
475
+
cvbs_dbg_test_pmx15: cvbs_dbg_test@15 {
476
+
cvbs_dbg_test_15 {
477
+
groups = "cvbs_dbg_test_grp15";
478
+
function = "cvbs_dbg_test_m15";
479
+
};
480
+
};
481
+
482
+
gn_gnss_power_pmx: gn_gnss_power@0 {
483
+
gn_gnss_power {
484
+
groups = "gn_gnss_power_grp";
485
+
function = "gn_gnss_power";
486
+
};
487
+
};
488
+
489
+
gn_gnss_sw_status_pmx: gn_gnss_sw_status@0 {
490
+
gn_gnss_sw_status {
491
+
groups = "gn_gnss_sw_status_grp";
492
+
function = "gn_gnss_sw_status";
493
+
};
494
+
};
495
+
496
+
gn_gnss_eclk_pmx: gn_gnss_eclk@0 {
497
+
gn_gnss_eclk {
498
+
groups = "gn_gnss_eclk_grp";
499
+
function = "gn_gnss_eclk";
500
+
};
501
+
};
502
+
503
+
gn_gnss_irq1_pmx0: gn_gnss_irq1@0 {
504
+
gn_gnss_irq1_0 {
505
+
groups = "gn_gnss_irq1_grp0";
506
+
function = "gn_gnss_irq1_m0";
507
+
};
508
+
};
509
+
510
+
gn_gnss_irq2_pmx0: gn_gnss_irq2@0 {
511
+
gn_gnss_irq2_0 {
512
+
groups = "gn_gnss_irq2_grp0";
513
+
function = "gn_gnss_irq2_m0";
514
+
};
515
+
};
516
+
517
+
gn_gnss_tm_pmx: gn_gnss_tm@0 {
518
+
gn_gnss_tm {
519
+
groups = "gn_gnss_tm_grp";
520
+
function = "gn_gnss_tm";
521
+
};
522
+
};
523
+
524
+
gn_gnss_tsync_pmx: gn_gnss_tsync@0 {
525
+
gn_gnss_tsync {
526
+
groups = "gn_gnss_tsync_grp";
527
+
function = "gn_gnss_tsync";
528
+
};
529
+
};
530
+
531
+
gn_io_gnsssys_sw_cfg_pmx: gn_io_gnsssys_sw_cfg@0 {
532
+
gn_io_gnsssys_sw_cfg {
533
+
groups = "gn_io_gnsssys_sw_cfg_grp";
534
+
function = "gn_io_gnsssys_sw_cfg";
535
+
};
536
+
};
537
+
538
+
gn_trg_pmx0: gn_trg@0 {
539
+
gn_trg_0 {
540
+
groups = "gn_trg_grp0";
541
+
function = "gn_trg_m0";
542
+
};
543
+
};
544
+
545
+
gn_trg_pmx1: gn_trg@1 {
546
+
gn_trg_1 {
547
+
groups = "gn_trg_grp1";
548
+
function = "gn_trg_m1";
549
+
};
550
+
};
551
+
552
+
gn_trg_shutdown_pmx0: gn_trg_shutdown@0 {
553
+
gn_trg_shutdown_0 {
554
+
groups = "gn_trg_shutdown_grp0";
555
+
function = "gn_trg_shutdown_m0";
556
+
};
557
+
};
558
+
559
+
gn_trg_shutdown_pmx1: gn_trg_shutdown@1 {
560
+
gn_trg_shutdown_1 {
561
+
groups = "gn_trg_shutdown_grp1";
562
+
function = "gn_trg_shutdown_m1";
563
+
};
564
+
};
565
+
566
+
gn_trg_shutdown_pmx2: gn_trg_shutdown@2 {
567
+
gn_trg_shutdown_2 {
568
+
groups = "gn_trg_shutdown_grp2";
569
+
function = "gn_trg_shutdown_m2";
570
+
};
571
+
};
572
+
573
+
gn_trg_shutdown_pmx3: gn_trg_shutdown@3 {
574
+
gn_trg_shutdown_3 {
575
+
groups = "gn_trg_shutdown_grp3";
576
+
function = "gn_trg_shutdown_m3";
577
+
};
578
+
};
579
+
580
+
i2c0_pmx: i2c0@0 {
581
+
i2c0 {
582
+
groups = "i2c0_grp";
583
+
function = "i2c0";
584
+
};
585
+
};
586
+
587
+
i2c1_pmx: i2c1@0 {
588
+
i2c1 {
589
+
groups = "i2c1_grp";
590
+
function = "i2c1";
591
+
};
592
+
};
593
+
594
+
jtag_pmx0: jtag@0 {
595
+
jtag_0 {
596
+
groups = "jtag_grp0";
597
+
function = "jtag_m0";
598
+
};
599
+
};
600
+
601
+
ks_kas_spi_pmx0: ks_kas_spi@0 {
602
+
ks_kas_spi_0 {
603
+
groups = "ks_kas_spi_grp0";
604
+
function = "ks_kas_spi_m0";
605
+
};
606
+
};
607
+
608
+
ld_ldd_pmx: ld_ldd@0 {
609
+
ld_ldd {
610
+
groups = "ld_ldd_grp";
611
+
function = "ld_ldd";
612
+
};
613
+
};
614
+
615
+
ld_ldd_16bit_pmx: ld_ldd_16bit@0 {
616
+
ld_ldd_16bit {
617
+
groups = "ld_ldd_16bit_grp";
618
+
function = "ld_ldd_16bit";
619
+
};
620
+
};
621
+
622
+
ld_ldd_fck_pmx: ld_ldd_fck@0 {
623
+
ld_ldd_fck {
624
+
groups = "ld_ldd_fck_grp";
625
+
function = "ld_ldd_fck";
626
+
};
627
+
};
628
+
629
+
ld_ldd_lck_pmx: ld_ldd_lck@0 {
630
+
ld_ldd_lck {
631
+
groups = "ld_ldd_lck_grp";
632
+
function = "ld_ldd_lck";
633
+
};
634
+
};
635
+
636
+
lr_lcdrom_pmx: lr_lcdrom@0 {
637
+
lr_lcdrom {
638
+
groups = "lr_lcdrom_grp";
639
+
function = "lr_lcdrom";
640
+
};
641
+
};
642
+
643
+
lvds_analog_pmx: lvds_analog@0 {
644
+
lvds_analog {
645
+
groups = "lvds_analog_grp";
646
+
function = "lvds_analog";
647
+
};
648
+
};
649
+
650
+
nd_df_pmx: nd_df@0 {
651
+
nd_df {
652
+
groups = "nd_df_grp";
653
+
function = "nd_df";
654
+
};
655
+
};
656
+
657
+
nd_df_nowp_pmx: nd_df_nowp@0 {
658
+
nd_df_nowp {
659
+
groups = "nd_df_nowp_grp";
660
+
function = "nd_df_nowp";
661
+
};
662
+
};
663
+
664
+
ps_pmx: ps@0 {
665
+
ps {
666
+
groups = "ps_grp";
667
+
function = "ps";
668
+
};
669
+
};
670
+
671
+
pwc_core_on_pmx: pwc_core_on@0 {
672
+
pwc_core_on {
673
+
groups = "pwc_core_on_grp";
674
+
function = "pwc_core_on";
675
+
};
676
+
};
677
+
678
+
pwc_ext_on_pmx: pwc_ext_on@0 {
679
+
pwc_ext_on {
680
+
groups = "pwc_ext_on_grp";
681
+
function = "pwc_ext_on";
682
+
};
683
+
};
684
+
685
+
pwc_gpio3_clk_pmx: pwc_gpio3_clk@0 {
686
+
pwc_gpio3_clk {
687
+
groups = "pwc_gpio3_clk_grp";
688
+
function = "pwc_gpio3_clk";
689
+
};
690
+
};
691
+
692
+
pwc_io_on_pmx: pwc_io_on@0 {
693
+
pwc_io_on {
694
+
groups = "pwc_io_on_grp";
695
+
function = "pwc_io_on";
696
+
};
697
+
};
698
+
699
+
pwc_lowbatt_b_pmx0: pwc_lowbatt_b@0 {
700
+
pwc_lowbatt_b_0 {
701
+
groups = "pwc_lowbatt_b_grp0";
702
+
function = "pwc_lowbatt_b_m0";
703
+
};
704
+
};
705
+
706
+
pwc_mem_on_pmx: pwc_mem_on@0 {
707
+
pwc_mem_on {
708
+
groups = "pwc_mem_on_grp";
709
+
function = "pwc_mem_on";
710
+
};
711
+
};
712
+
713
+
pwc_on_key_b_pmx0: pwc_on_key_b@0 {
714
+
pwc_on_key_b_0 {
715
+
groups = "pwc_on_key_b_grp0";
716
+
function = "pwc_on_key_b_m0";
717
+
};
718
+
};
719
+
720
+
pwc_wakeup_src0_pmx: pwc_wakeup_src0@0 {
721
+
pwc_wakeup_src0 {
722
+
groups = "pwc_wakeup_src0_grp";
723
+
function = "pwc_wakeup_src0";
724
+
};
725
+
};
726
+
727
+
pwc_wakeup_src1_pmx: pwc_wakeup_src1@0 {
728
+
pwc_wakeup_src1 {
729
+
groups = "pwc_wakeup_src1_grp";
730
+
function = "pwc_wakeup_src1";
731
+
};
732
+
};
733
+
734
+
pwc_wakeup_src2_pmx: pwc_wakeup_src2@0 {
735
+
pwc_wakeup_src2 {
736
+
groups = "pwc_wakeup_src2_grp";
737
+
function = "pwc_wakeup_src2";
738
+
};
739
+
};
740
+
741
+
pwc_wakeup_src3_pmx: pwc_wakeup_src3@0 {
742
+
pwc_wakeup_src3 {
743
+
groups = "pwc_wakeup_src3_grp";
744
+
function = "pwc_wakeup_src3";
745
+
};
746
+
};
747
+
748
+
pw_cko0_pmx0: pw_cko0@0 {
749
+
pw_cko0_0 {
750
+
groups = "pw_cko0_grp0";
751
+
function = "pw_cko0_m0";
752
+
};
753
+
};
754
+
755
+
pw_cko0_pmx1: pw_cko0@1 {
756
+
pw_cko0_1 {
757
+
groups = "pw_cko0_grp1";
758
+
function = "pw_cko0_m1";
759
+
};
760
+
};
761
+
762
+
pw_cko0_pmx2: pw_cko0@2 {
763
+
pw_cko0_2 {
764
+
groups = "pw_cko0_grp2";
765
+
function = "pw_cko0_m2";
766
+
};
767
+
};
768
+
769
+
pw_cko1_pmx0: pw_cko1@0 {
770
+
pw_cko1_0 {
771
+
groups = "pw_cko1_grp0";
772
+
function = "pw_cko1_m0";
773
+
};
774
+
};
775
+
776
+
pw_cko1_pmx1: pw_cko1@1 {
777
+
pw_cko1_1 {
778
+
groups = "pw_cko1_grp1";
779
+
function = "pw_cko1_m1";
780
+
};
781
+
};
782
+
783
+
pw_i2s01_clk_pmx0: pw_i2s01_clk@0 {
784
+
pw_i2s01_clk_0 {
785
+
groups = "pw_i2s01_clk_grp0";
786
+
function = "pw_i2s01_clk_m0";
787
+
};
788
+
};
789
+
790
+
pw_i2s01_clk_pmx1: pw_i2s01_clk@1 {
791
+
pw_i2s01_clk_1 {
792
+
groups = "pw_i2s01_clk_grp1";
793
+
function = "pw_i2s01_clk_m1";
794
+
};
795
+
};
796
+
797
+
pw_pwm0_pmx: pw_pwm0@0 {
798
+
pw_pwm0 {
799
+
groups = "pw_pwm0_grp";
800
+
function = "pw_pwm0";
801
+
};
802
+
};
803
+
804
+
pw_pwm1_pmx: pw_pwm1@0 {
805
+
pw_pwm1 {
806
+
groups = "pw_pwm1_grp";
807
+
function = "pw_pwm1";
808
+
};
809
+
};
810
+
811
+
pw_pwm2_pmx0: pw_pwm2@0 {
812
+
pw_pwm2_0 {
813
+
groups = "pw_pwm2_grp0";
814
+
function = "pw_pwm2_m0";
815
+
};
816
+
};
817
+
818
+
pw_pwm2_pmx1: pw_pwm2@1 {
819
+
pw_pwm2_1 {
820
+
groups = "pw_pwm2_grp1";
821
+
function = "pw_pwm2_m1";
822
+
};
823
+
};
824
+
825
+
pw_pwm3_pmx0: pw_pwm3@0 {
826
+
pw_pwm3_0 {
827
+
groups = "pw_pwm3_grp0";
828
+
function = "pw_pwm3_m0";
829
+
};
830
+
};
831
+
832
+
pw_pwm3_pmx1: pw_pwm3@1 {
833
+
pw_pwm3_1 {
834
+
groups = "pw_pwm3_grp1";
835
+
function = "pw_pwm3_m1";
836
+
};
837
+
};
838
+
839
+
pw_pwm_cpu_vol_pmx0: pw_pwm_cpu_vol@0 {
840
+
pw_pwm_cpu_vol_0 {
841
+
groups = "pw_pwm_cpu_vol_grp0";
842
+
function = "pw_pwm_cpu_vol_m0";
843
+
};
844
+
};
845
+
846
+
pw_pwm_cpu_vol_pmx1: pw_pwm_cpu_vol@1 {
847
+
pw_pwm_cpu_vol_1 {
848
+
groups = "pw_pwm_cpu_vol_grp1";
849
+
function = "pw_pwm_cpu_vol_m1";
850
+
};
851
+
};
852
+
853
+
pw_backlight_pmx0: pw_backlight@0 {
854
+
pw_backlight_0 {
855
+
groups = "pw_backlight_grp0";
856
+
function = "pw_backlight_m0";
857
+
};
858
+
};
859
+
860
+
pw_backlight_pmx1: pw_backlight@1 {
861
+
pw_backlight_1 {
862
+
groups = "pw_backlight_grp1";
863
+
function = "pw_backlight_m1";
864
+
};
865
+
};
866
+
867
+
rg_eth_mac_pmx: rg_eth_mac@0 {
868
+
rg_eth_mac {
869
+
groups = "rg_eth_mac_grp";
870
+
function = "rg_eth_mac";
871
+
};
872
+
};
873
+
874
+
rg_gmac_phy_intr_n_pmx: rg_gmac_phy_intr_n@0 {
875
+
rg_gmac_phy_intr_n {
876
+
groups = "rg_gmac_phy_intr_n_grp";
877
+
function = "rg_gmac_phy_intr_n";
878
+
};
879
+
};
880
+
881
+
rg_rgmii_mac_pmx: rg_rgmii_mac@0 {
882
+
rg_rgmii_mac {
883
+
groups = "rg_rgmii_mac_grp";
884
+
function = "rg_rgmii_mac";
885
+
};
886
+
};
887
+
888
+
rg_rgmii_phy_ref_clk_pmx0: rg_rgmii_phy_ref_clk@0 {
889
+
rg_rgmii_phy_ref_clk_0 {
890
+
groups =
891
+
"rg_rgmii_phy_ref_clk_grp0";
892
+
function =
893
+
"rg_rgmii_phy_ref_clk_m0";
894
+
};
895
+
};
896
+
897
+
rg_rgmii_phy_ref_clk_pmx1: rg_rgmii_phy_ref_clk@1 {
898
+
rg_rgmii_phy_ref_clk_1 {
899
+
groups =
900
+
"rg_rgmii_phy_ref_clk_grp1";
901
+
function =
902
+
"rg_rgmii_phy_ref_clk_m1";
903
+
};
904
+
};
905
+
906
+
sd0_pmx: sd0@0 {
907
+
sd0 {
908
+
groups = "sd0_grp";
909
+
function = "sd0";
910
+
};
911
+
};
912
+
913
+
sd0_4bit_pmx: sd0_4bit@0 {
914
+
sd0_4bit {
915
+
groups = "sd0_4bit_grp";
916
+
function = "sd0_4bit";
917
+
};
918
+
};
919
+
920
+
sd1_pmx: sd1@0 {
921
+
sd1 {
922
+
groups = "sd1_grp";
923
+
function = "sd1";
924
+
};
925
+
};
926
+
927
+
sd1_4bit_pmx0: sd1_4bit@0 {
928
+
sd1_4bit_0 {
929
+
groups = "sd1_4bit_grp0";
930
+
function = "sd1_4bit_m0";
931
+
};
932
+
};
933
+
934
+
sd1_4bit_pmx1: sd1_4bit@1 {
935
+
sd1_4bit_1 {
936
+
groups = "sd1_4bit_grp1";
937
+
function = "sd1_4bit_m1";
938
+
};
939
+
};
940
+
941
+
sd2_pmx0: sd2@0 {
942
+
sd2_0 {
943
+
groups = "sd2_grp0";
944
+
function = "sd2_m0";
945
+
};
946
+
};
947
+
948
+
sd2_no_cdb_pmx0: sd2_no_cdb@0 {
949
+
sd2_no_cdb_0 {
950
+
groups = "sd2_no_cdb_grp0";
951
+
function = "sd2_no_cdb_m0";
952
+
};
953
+
};
954
+
955
+
sd3_pmx: sd3@0 {
956
+
sd3 {
957
+
groups = "sd3_grp";
958
+
function = "sd3";
959
+
};
960
+
};
961
+
962
+
sd5_pmx: sd5@0 {
963
+
sd5 {
964
+
groups = "sd5_grp";
965
+
function = "sd5";
966
+
};
967
+
};
968
+
969
+
sd6_pmx0: sd6@0 {
970
+
sd6_0 {
971
+
groups = "sd6_grp0";
972
+
function = "sd6_m0";
973
+
};
974
+
};
975
+
976
+
sd6_pmx1: sd6@1 {
977
+
sd6_1 {
978
+
groups = "sd6_grp1";
979
+
function = "sd6_m1";
980
+
};
981
+
};
982
+
983
+
sp0_ext_ldo_on_pmx: sp0_ext_ldo_on@0 {
984
+
sp0_ext_ldo_on {
985
+
groups = "sp0_ext_ldo_on_grp";
986
+
function = "sp0_ext_ldo_on";
987
+
};
988
+
};
989
+
990
+
sp0_qspi_pmx: sp0_qspi@0 {
991
+
sp0_qspi {
992
+
groups = "sp0_qspi_grp";
993
+
function = "sp0_qspi";
994
+
};
995
+
};
996
+
997
+
sp1_spi_pmx: sp1_spi@0 {
998
+
sp1_spi {
999
+
groups = "sp1_spi_grp";
1000
+
function = "sp1_spi";
1001
+
};
1002
+
};
1003
+
1004
+
tpiu_trace_pmx: tpiu_trace@0 {
1005
+
tpiu_trace {
1006
+
groups = "tpiu_trace_grp";
1007
+
function = "tpiu_trace";
1008
+
};
1009
+
};
1010
+
1011
+
uart0_pmx: uart0@0 {
1012
+
uart0 {
1013
+
groups = "uart0_grp";
1014
+
function = "uart0";
1015
+
};
1016
+
};
1017
+
1018
+
uart0_nopause_pmx: uart0_nopause@0 {
1019
+
uart0_nopause {
1020
+
groups = "uart0_nopause_grp";
1021
+
function = "uart0_nopause";
1022
+
};
1023
+
};
1024
+
1025
+
uart1_pmx: uart1@0 {
1026
+
uart1 {
1027
+
groups = "uart1_grp";
1028
+
function = "uart1";
1029
+
};
1030
+
};
1031
+
1032
+
uart2_pmx: uart2@0 {
1033
+
uart2 {
1034
+
groups = "uart2_grp";
1035
+
function = "uart2";
1036
+
};
1037
+
};
1038
+
1039
+
uart3_pmx0: uart3@0 {
1040
+
uart3_0 {
1041
+
groups = "uart3_grp0";
1042
+
function = "uart3_m0";
1043
+
};
1044
+
};
1045
+
1046
+
uart3_pmx1: uart3@1 {
1047
+
uart3_1 {
1048
+
groups = "uart3_grp1";
1049
+
function = "uart3_m1";
1050
+
};
1051
+
};
1052
+
1053
+
uart3_pmx2: uart3@2 {
1054
+
uart3_2 {
1055
+
groups = "uart3_grp2";
1056
+
function = "uart3_m2";
1057
+
};
1058
+
};
1059
+
1060
+
uart3_pmx3: uart3@3 {
1061
+
uart3_3 {
1062
+
groups = "uart3_grp3";
1063
+
function = "uart3_m3";
1064
+
};
1065
+
};
1066
+
1067
+
uart3_nopause_pmx0: uart3_nopause@0 {
1068
+
uart3_nopause_0 {
1069
+
groups = "uart3_nopause_grp0";
1070
+
function = "uart3_nopause_m0";
1071
+
};
1072
+
};
1073
+
1074
+
uart3_nopause_pmx1: uart3_nopause@1 {
1075
+
uart3_nopause_1 {
1076
+
groups = "uart3_nopause_grp1";
1077
+
function = "uart3_nopause_m1";
1078
+
};
1079
+
};
1080
+
1081
+
uart4_pmx0: uart4@0 {
1082
+
uart4_0 {
1083
+
groups = "uart4_grp0";
1084
+
function = "uart4_m0";
1085
+
};
1086
+
};
1087
+
1088
+
uart4_pmx1: uart4@1 {
1089
+
uart4_1 {
1090
+
groups = "uart4_grp1";
1091
+
function = "uart4_m1";
1092
+
};
1093
+
};
1094
+
1095
+
uart4_pmx2: uart4@2 {
1096
+
uart4_2 {
1097
+
groups = "uart4_grp2";
1098
+
function = "uart4_m2";
1099
+
};
1100
+
};
1101
+
1102
+
uart4_nopause_pmx: uart4_nopause@0 {
1103
+
uart4_nopause {
1104
+
groups = "uart4_nopause_grp";
1105
+
function = "uart4_nopause";
1106
+
};
1107
+
};
1108
+
1109
+
usb0_drvvbus_pmx: usb0_drvvbus@0 {
1110
+
usb0_drvvbus {
1111
+
groups = "usb0_drvvbus_grp";
1112
+
function = "usb0_drvvbus";
1113
+
};
1114
+
};
1115
+
1116
+
usb1_drvvbus_pmx: usb1_drvvbus@0 {
1117
+
usb1_drvvbus {
1118
+
groups = "usb1_drvvbus_grp";
1119
+
function = "usb1_drvvbus";
1120
+
};
1121
+
};
1122
+
1123
+
visbus_dout_pmx: visbus_dout@0 {
1124
+
visbus_dout {
1125
+
groups = "visbus_dout_grp";
1126
+
function = "visbus_dout";
1127
+
};
1128
+
};
1129
+
1130
+
vi_vip1_pmx: vi_vip1@0 {
1131
+
vi_vip1 {
1132
+
groups = "vi_vip1_grp";
1133
+
function = "vi_vip1";
1134
+
};
1135
+
};
1136
+
1137
+
vi_vip1_ext_pmx: vi_vip1_ext@0 {
1138
+
vi_vip1_ext {
1139
+
groups = "vi_vip1_ext_grp";
1140
+
function = "vi_vip1_ext";
1141
+
};
1142
+
};
1143
+
1144
+
vi_vip1_low8bit_pmx: vi_vip1_low8bit@0 {
1145
+
vi_vip1_low8bit {
1146
+
groups = "vi_vip1_low8bit_grp";
1147
+
function = "vi_vip1_low8bit";
1148
+
};
1149
+
};
1150
+
1151
+
vi_vip1_high8bit_pmx: vi_vip1_high8bit@0 {
1152
+
vi_vip1_high8bit {
1153
+
groups = "vi_vip1_high8bit_grp";
1154
+
function = "vi_vip1_high8bit";
1155
+
};
1156
+
};
138
1157
};
139
1158
140
1159
pmipc {
···
1375
356
clock-names = "gpio0_io";
1376
357
gpio-controller;
1377
358
interrupt-controller;
359
+
360
+
gpio-banks = <2>;
361
+
gpio-ranges = <&pinctrl 0 0 0>,
362
+
<&pinctrl 32 0 0>;
363
+
gpio-ranges-group-names = "lvds_gpio_grp",
364
+
"uart_nand_gpio_grp";
1378
365
};
1379
366
1380
367
nand@17050000 {
···
1486
461
#interrupt-cells = <2>;
1487
462
compatible = "sirf,atlas7-gpio";
1488
463
reg = <0x13300000 0x1000>;
1489
-
interrupts = <0 43 0>, <0 44 0>, <0 45 0>;
464
+
interrupts = <0 43 0>, <0 44 0>,
465
+
<0 45 0>, <0 46 0>;
1490
466
clocks = <&car 84>;
1491
467
clock-names = "gpio1_io";
1492
468
gpio-controller;
1493
469
interrupt-controller;
470
+
471
+
gpio-banks = <4>;
472
+
gpio-ranges = <&pinctrl 0 0 0>,
473
+
<&pinctrl 32 0 0>,
474
+
<&pinctrl 64 0 0>,
475
+
<&pinctrl 96 0 0>;
476
+
gpio-ranges-group-names = "gnss_gpio_grp",
477
+
"lcd_vip_gpio_grp",
478
+
"sdio_i2s_gpio_grp",
479
+
"sp_rgmii_gpio_grp";
1494
480
};
1495
481
1496
482
sd2: sdhci@14200000 {
···
1780
744
interrupts = <0 47 0>;
1781
745
gpio-controller;
1782
746
interrupt-controller;
747
+
748
+
gpio-banks = <1>;
749
+
gpio-ranges = <&pinctrl 0 0 0>;
750
+
gpio-ranges-group-names = "rtc_gpio_grp";
1783
751
};
1784
752
1785
753
rtc-iobg@18840000 {
+23
-2
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+23
-2
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
···
150
150
interface-type = "ace";
151
151
reg = <0x5000 0x1000>;
152
152
};
153
+
154
+
pmu@9000 {
155
+
compatible = "arm,cci-400-pmu,r0";
156
+
reg = <0x9000 0x5000>;
157
+
interrupts = <0 105 4>,
158
+
<0 101 4>,
159
+
<0 102 4>,
160
+
<0 103 4>,
161
+
<0 104 4>;
162
+
};
153
163
};
154
164
155
165
memory-controller@7ffd0000 {
···
197
187
<1 10 0xf08>;
198
188
};
199
189
200
-
pmu {
190
+
pmu_a15 {
201
191
compatible = "arm,cortex-a15-pmu";
202
192
interrupts = <0 68 4>,
203
193
<0 69 4>;
204
-
interrupt-affinity = <&cpu0>, <&cpu1>;
194
+
interrupt-affinity = <&cpu0>,
195
+
<&cpu1>;
196
+
};
197
+
198
+
pmu_a7 {
199
+
compatible = "arm,cortex-a7-pmu";
200
+
interrupts = <0 128 4>,
201
+
<0 129 4>,
202
+
<0 130 4>;
203
+
interrupt-affinity = <&cpu2>,
204
+
<&cpu3>,
205
+
<&cpu4>;
205
206
};
206
207
207
208
oscclk6a: oscclk6a {
-1
arch/arm/configs/multi_v7_defconfig
-1
arch/arm/configs/multi_v7_defconfig
+5
-1
arch/arm/configs/sunxi_defconfig
+5
-1
arch/arm/configs/sunxi_defconfig
···
2
2
CONFIG_HIGH_RES_TIMERS=y
3
3
CONFIG_BLK_DEV_INITRD=y
4
4
CONFIG_PERF_EVENTS=y
5
+
CONFIG_MODULES=y
5
6
CONFIG_ARCH_SUNXI=y
6
7
CONFIG_SMP=y
7
8
CONFIG_NR_CPUS=8
···
78
77
CONFIG_GPIO_SYSFS=y
79
78
CONFIG_POWER_SUPPLY=y
80
79
CONFIG_POWER_RESET=y
81
-
CONFIG_POWER_RESET_SUN6I=y
82
80
CONFIG_THERMAL=y
83
81
CONFIG_CPU_THERMAL=y
84
82
CONFIG_WATCHDOG=y
···
87
87
CONFIG_REGULATOR_FIXED_VOLTAGE=y
88
88
CONFIG_REGULATOR_AXP20X=y
89
89
CONFIG_REGULATOR_GPIO=y
90
+
CONFIG_FB=y
91
+
CONFIG_FB_SIMPLE=y
92
+
CONFIG_FRAMEBUFFER_CONSOLE=y
93
+
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
90
94
CONFIG_USB=y
91
95
CONFIG_USB_EHCI_HCD=y
92
96
CONFIG_USB_EHCI_HCD_PLATFORM=y
-1
arch/arm/mach-omap2/dma.c
-1
arch/arm/mach-omap2/dma.c
+1
arch/arm/mach-prima2/Kconfig
+1
arch/arm/mach-prima2/Kconfig
+45
-3
arch/arm/mach-prima2/rtciobrg.c
+45
-3
arch/arm/mach-prima2/rtciobrg.c
···
1
1
/*
2
-
* RTC I/O Bridge interfaces for CSR SiRFprimaII
2
+
* RTC I/O Bridge interfaces for CSR SiRFprimaII/atlas7
3
3
* ARM access the registers of SYSRTC, GPSRTC and PWRC through this module
4
4
*
5
5
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
···
10
10
#include <linux/kernel.h>
11
11
#include <linux/module.h>
12
12
#include <linux/io.h>
13
+
#include <linux/regmap.h>
13
14
#include <linux/of.h>
14
15
#include <linux/of_address.h>
15
16
#include <linux/of_device.h>
···
67
66
{
68
67
unsigned long flags, val;
69
68
69
+
/* TODO: add hwspinlock to sync with M3 */
70
70
spin_lock_irqsave(&rtciobrg_lock, flags);
71
71
72
72
val = __sirfsoc_rtc_iobrg_readl(addr);
···
92
90
{
93
91
unsigned long flags;
94
92
93
+
/* TODO: add hwspinlock to sync with M3 */
95
94
spin_lock_irqsave(&rtciobrg_lock, flags);
96
95
97
96
sirfsoc_rtc_iobrg_pre_writel(val, addr);
···
104
101
spin_unlock_irqrestore(&rtciobrg_lock, flags);
105
102
}
106
103
EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_writel);
104
+
105
+
106
+
static int regmap_iobg_regwrite(void *context, unsigned int reg,
107
+
unsigned int val)
108
+
{
109
+
sirfsoc_rtc_iobrg_writel(val, reg);
110
+
return 0;
111
+
}
112
+
113
+
static int regmap_iobg_regread(void *context, unsigned int reg,
114
+
unsigned int *val)
115
+
{
116
+
*val = (u32)sirfsoc_rtc_iobrg_readl(reg);
117
+
return 0;
118
+
}
119
+
120
+
static struct regmap_bus regmap_iobg = {
121
+
.reg_write = regmap_iobg_regwrite,
122
+
.reg_read = regmap_iobg_regread,
123
+
};
124
+
125
+
/**
126
+
* devm_regmap_init_iobg(): Initialise managed register map
127
+
*
128
+
* @iobg: Device that will be interacted with
129
+
* @config: Configuration for register map
130
+
*
131
+
* The return value will be an ERR_PTR() on error or a valid pointer
132
+
* to a struct regmap. The regmap will be automatically freed by the
133
+
* device management code.
134
+
*/
135
+
struct regmap *devm_regmap_init_iobg(struct device *dev,
136
+
const struct regmap_config *config)
137
+
{
138
+
const struct regmap_bus *bus = ®map_iobg;
139
+
140
+
return devm_regmap_init(dev, bus, dev, config);
141
+
}
142
+
EXPORT_SYMBOL_GPL(devm_regmap_init_iobg);
107
143
108
144
static const struct of_device_id rtciobrg_ids[] = {
109
145
{ .compatible = "sirf,prima2-rtciobg" },
···
174
132
}
175
133
postcore_initcall(sirfsoc_rtciobrg_init);
176
134
177
-
MODULE_AUTHOR("Zhiwu Song <zhiwu.song@csr.com>, "
178
-
"Barry Song <baohua.song@csr.com>");
135
+
MODULE_AUTHOR("Zhiwu Song <zhiwu.song@csr.com>");
136
+
MODULE_AUTHOR("Barry Song <baohua.song@csr.com>");
179
137
MODULE_DESCRIPTION("CSR SiRFprimaII rtc io bridge");
180
138
MODULE_LICENSE("GPL v2");
+1
-1
arch/arm/mach-sunxi/Kconfig
+1
-1
arch/arm/mach-sunxi/Kconfig
+4
-1
arch/arm/mach-sunxi/sunxi.c
+4
-1
arch/arm/mach-sunxi/sunxi.c
···
67
67
68
68
static const char * const sun8i_board_dt_compat[] = {
69
69
"allwinner,sun8i-a23",
70
+
"allwinner,sun8i-a33",
71
+
"allwinner,sun8i-h3",
70
72
NULL,
71
73
};
72
74
73
-
DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i (A23) Family")
75
+
DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
76
+
.init_time = sun6i_timer_init,
74
77
.dt_compat = sun8i_board_dt_compat,
75
78
.init_late = sunxi_dt_cpufreq_init,
76
79
MACHINE_END
+10
arch/arm64/boot/dts/apm/apm-mustang.dts
+10
arch/arm64/boot/dts/apm/apm-mustang.dts
···
23
23
device_type = "memory";
24
24
reg = < 0x1 0x00000000 0x0 0x80000000 >; /* Updated by bootloader */
25
25
};
26
+
27
+
gpio-keys {
28
+
compatible = "gpio-keys";
29
+
button@1 {
30
+
label = "POWER";
31
+
linux,code = <116>;
32
+
linux,input-type = <0x1>;
33
+
interrupts = <0x0 0x2d 0x1>;
34
+
};
35
+
};
26
36
};
27
37
28
38
&pcie0clk {
+1
arch/arm64/boot/dts/arm/Makefile
+1
arch/arm64/boot/dts/arm/Makefile
+191
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
+191
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
···
1
+
/*
2
+
* ARM Ltd. Versatile Express
3
+
*
4
+
* LogicTile Express 20MG
5
+
* V2F-1XV7
6
+
*
7
+
* Cortex-A53 (2 cores) Soft Macrocell Model
8
+
*
9
+
* HBI-0247C
10
+
*/
11
+
12
+
/dts-v1/;
13
+
14
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
15
+
16
+
/ {
17
+
model = "V2F-1XV7 Cortex-A53x2 SMM";
18
+
arm,hbi = <0x247>;
19
+
arm,vexpress,site = <0xf>;
20
+
compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
21
+
interrupt-parent = <&gic>;
22
+
#address-cells = <2>;
23
+
#size-cells = <2>;
24
+
25
+
chosen {
26
+
stdout-path = "serial0:38400n8";
27
+
};
28
+
29
+
aliases {
30
+
serial0 = &v2m_serial0;
31
+
serial1 = &v2m_serial1;
32
+
serial2 = &v2m_serial2;
33
+
serial3 = &v2m_serial3;
34
+
i2c0 = &v2m_i2c_dvi;
35
+
i2c1 = &v2m_i2c_pcie;
36
+
};
37
+
38
+
cpus {
39
+
#address-cells = <2>;
40
+
#size-cells = <0>;
41
+
42
+
cpu@0 {
43
+
device_type = "cpu";
44
+
compatible = "arm,cortex-a53", "arm,armv8";
45
+
reg = <0 0>;
46
+
next-level-cache = <&L2_0>;
47
+
};
48
+
49
+
cpu@1 {
50
+
device_type = "cpu";
51
+
compatible = "arm,cortex-a53", "arm,armv8";
52
+
reg = <0 1>;
53
+
next-level-cache = <&L2_0>;
54
+
};
55
+
56
+
L2_0: l2-cache0 {
57
+
compatible = "cache";
58
+
};
59
+
};
60
+
61
+
memory@80000000 {
62
+
device_type = "memory";
63
+
reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
64
+
};
65
+
66
+
gic: interrupt-controller@2c001000 {
67
+
compatible = "arm,gic-400";
68
+
#interrupt-cells = <3>;
69
+
#address-cells = <0>;
70
+
interrupt-controller;
71
+
reg = <0 0x2c001000 0 0x1000>,
72
+
<0 0x2c002000 0 0x2000>,
73
+
<0 0x2c004000 0 0x2000>,
74
+
<0 0x2c006000 0 0x2000>;
75
+
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
76
+
};
77
+
78
+
timer {
79
+
compatible = "arm,armv8-timer";
80
+
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
81
+
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
82
+
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
83
+
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
84
+
};
85
+
86
+
pmu {
87
+
compatible = "arm,armv8-pmuv3";
88
+
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
89
+
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
90
+
};
91
+
92
+
dcc {
93
+
compatible = "arm,vexpress,config-bus";
94
+
arm,vexpress,config-bridge = <&v2m_sysreg>;
95
+
96
+
smbclk: osc@4 {
97
+
/* SMC clock */
98
+
compatible = "arm,vexpress-osc";
99
+
arm,vexpress-sysreg,func = <1 4>;
100
+
freq-range = <40000000 40000000>;
101
+
#clock-cells = <0>;
102
+
clock-output-names = "smclk";
103
+
};
104
+
105
+
volt@0 {
106
+
/* VIO to expansion board above */
107
+
compatible = "arm,vexpress-volt";
108
+
arm,vexpress-sysreg,func = <2 0>;
109
+
regulator-name = "VIO_UP";
110
+
regulator-min-microvolt = <800000>;
111
+
regulator-max-microvolt = <1800000>;
112
+
regulator-always-on;
113
+
};
114
+
115
+
volt@1 {
116
+
/* 12V from power connector J6 */
117
+
compatible = "arm,vexpress-volt";
118
+
arm,vexpress-sysreg,func = <2 1>;
119
+
regulator-name = "12";
120
+
regulator-always-on;
121
+
};
122
+
123
+
temp@0 {
124
+
/* FPGA temperature */
125
+
compatible = "arm,vexpress-temp";
126
+
arm,vexpress-sysreg,func = <4 0>;
127
+
label = "FPGA";
128
+
};
129
+
};
130
+
131
+
smb {
132
+
compatible = "simple-bus";
133
+
134
+
#address-cells = <2>;
135
+
#size-cells = <1>;
136
+
ranges = <0 0 0 0x08000000 0x04000000>,
137
+
<1 0 0 0x14000000 0x04000000>,
138
+
<2 0 0 0x18000000 0x04000000>,
139
+
<3 0 0 0x1c000000 0x04000000>,
140
+
<4 0 0 0x0c000000 0x04000000>,
141
+
<5 0 0 0x10000000 0x04000000>;
142
+
143
+
#interrupt-cells = <1>;
144
+
interrupt-map-mask = <0 0 63>;
145
+
interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
146
+
<0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
147
+
<0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
148
+
<0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
149
+
<0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
150
+
<0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
151
+
<0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
152
+
<0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
153
+
<0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
154
+
<0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
155
+
<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
156
+
<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
157
+
<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
158
+
<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
159
+
<0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
160
+
<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
161
+
<0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
162
+
<0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
163
+
<0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
164
+
<0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
165
+
<0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
166
+
<0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
167
+
<0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
168
+
<0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
169
+
<0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
170
+
<0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
171
+
<0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
172
+
<0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
173
+
<0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
174
+
<0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
175
+
<0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
176
+
<0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
177
+
<0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
178
+
<0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
179
+
<0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
180
+
<0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
181
+
<0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
182
+
<0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
183
+
<0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
184
+
<0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
185
+
<0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
186
+
<0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
187
+
<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
188
+
189
+
/include/ "../../../../arm/boot/dts/vexpress-v2m-rs1.dtsi"
190
+
};
191
+
};
+9
arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
+9
arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
···
376
376
gic0: interrupt-controller@8010,00000000 {
377
377
compatible = "arm,gic-v3";
378
378
#interrupt-cells = <3>;
379
+
#address-cells = <2>;
380
+
#size-cells = <2>;
381
+
ranges;
379
382
interrupt-controller;
380
383
reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */
381
384
<0x8010 0x80000000 0x0 0x600000>; /* GICR */
382
385
interrupts = <1 9 0xf04>;
386
+
387
+
its: gic-its@8010,00020000 {
388
+
compatible = "arm,gic-v3-its";
389
+
msi-controller;
390
+
reg = <0x8010 0x20000 0x0 0x200000>;
391
+
};
383
392
};
384
393
385
394
uaa0: serial@87e0,24000000 {
+1
drivers/clk/sunxi/clk-sunxi.c
+1
drivers/clk/sunxi/clk-sunxi.c
···
1391
1391
CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
1392
1392
CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
1393
1393
CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
1394
+
CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
1394
1395
1395
1396
static void __init sun9i_init_clocks(struct device_node *node)
1396
1397
{
+1
-7
drivers/memory/omap-gpmc.c
+1
-7
drivers/memory/omap-gpmc.c
···
2074
2074
ret = gpmc_probe_nand_child(pdev, child);
2075
2075
else if (of_node_cmp(child->name, "onenand") == 0)
2076
2076
ret = gpmc_probe_onenand_child(pdev, child);
2077
-
else if (of_node_cmp(child->name, "ethernet") == 0 ||
2078
-
of_node_cmp(child->name, "nor") == 0 ||
2079
-
of_node_cmp(child->name, "uart") == 0)
2077
+
else
2080
2078
ret = gpmc_probe_generic_child(pdev, child);
2081
-
2082
-
if (WARN(ret < 0, "%s: probing gpmc child %s failed\n",
2083
-
__func__, child->full_name))
2084
-
of_node_put(child);
2085
2079
}
2086
2080
2087
2081
return 0;
+4
include/linux/rtc/sirfsoc_rtciobrg.h
+4
include/linux/rtc/sirfsoc_rtciobrg.h
···
9
9
#ifndef _SIRFSOC_RTC_IOBRG_H_
10
10
#define _SIRFSOC_RTC_IOBRG_H_
11
11
12
+
struct regmap_config;
13
+
12
14
extern void sirfsoc_rtc_iobrg_besyncing(void);
13
15
14
16
extern u32 sirfsoc_rtc_iobrg_readl(u32 addr);
15
17
16
18
extern void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr);
19
+
struct regmap *devm_regmap_init_iobg(struct device *dev,
20
+
const struct regmap_config *config);
17
21
18
22
#endif