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x86/resctrl: Add data structures and definitions for ABMC assignment

The ABMC feature allows users to assign a hardware counter to an RMID,
event pair and monitor bandwidth usage as long as it is assigned. The
hardware continues to track the assigned counter until it is explicitly
unassigned by the user.

The ABMC feature implements an MSR L3_QOS_ABMC_CFG (C000_03FDh).
ABMC counter assignment is done by setting the counter id, bandwidth
source (RMID) and bandwidth configuration.

Attempts to read or write the MSR when ABMC is not enabled will result
in a #GP(0) exception.

Introduce the data structures and definitions for MSR L3_QOS_ABMC_CFG
(0xC000_03FDh):
=========================================================================
Bits Mnemonic Description Access Reset
Type Value
=========================================================================
63 CfgEn Configuration Enable R/W 0

62 CtrEn Enable/disable counting R/W 0

61:53 – Reserved MBZ 0

52:48 CtrID Counter Identifier R/W 0

47 IsCOS BwSrc field is a CLOSID R/W 0
(not an RMID)

46:44 – Reserved MBZ 0

43:32 BwSrc Bandwidth Source R/W 0
(RMID or CLOSID)

31:0 BwType Bandwidth configuration R/W 0
tracked by the CtrID
==========================================================================

The ABMC feature details are documented in APM [1] available from [2].
[1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth
Monitoring (ABMC).

[ bp: Touchups. ]

Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 # [2]

authored by

Babu Moger and committed by
Borislav Petkov (AMD) 84ecefb7 16ff6b03

+37
+1
arch/x86/include/asm/msr-index.h
··· 1223 1223 /* - AMD: */ 1224 1224 #define MSR_IA32_MBA_BW_BASE 0xc0000200 1225 1225 #define MSR_IA32_SMBA_BW_BASE 0xc0000280 1226 + #define MSR_IA32_L3_QOS_ABMC_CFG 0xc00003fd 1226 1227 #define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff 1227 1228 #define MSR_IA32_EVT_CFG_BASE 0xc0000400 1228 1229
+36
arch/x86/kernel/cpu/resctrl/internal.h
··· 164 164 unsigned int full; 165 165 }; 166 166 167 + /* 168 + * ABMC counters are configured by writing to MSR_IA32_L3_QOS_ABMC_CFG. 169 + * 170 + * @bw_type : Event configuration that represents the memory 171 + * transactions being tracked by the @cntr_id. 172 + * @bw_src : Bandwidth source (RMID or CLOSID). 173 + * @reserved1 : Reserved. 174 + * @is_clos : @bw_src field is a CLOSID (not an RMID). 175 + * @cntr_id : Counter identifier. 176 + * @reserved : Reserved. 177 + * @cntr_en : Counting enable bit. 178 + * @cfg_en : Configuration enable bit. 179 + * 180 + * Configuration and counting: 181 + * Counter can be configured across multiple writes to MSR. Configuration 182 + * is applied only when @cfg_en = 1. Counter @cntr_id is reset when the 183 + * configuration is applied. 184 + * @cfg_en = 1, @cntr_en = 0 : Apply @cntr_id configuration but do not 185 + * count events. 186 + * @cfg_en = 1, @cntr_en = 1 : Apply @cntr_id configuration and start 187 + * counting events. 188 + */ 189 + union l3_qos_abmc_cfg { 190 + struct { 191 + unsigned long bw_type :32, 192 + bw_src :12, 193 + reserved1: 3, 194 + is_clos : 1, 195 + cntr_id : 5, 196 + reserved : 9, 197 + cntr_en : 1, 198 + cfg_en : 1; 199 + } split; 200 + unsigned long full; 201 + }; 202 + 167 203 void rdt_ctrl_update(void *arg); 168 204 169 205 int rdt_get_mon_l3_config(struct rdt_resource *r);