Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'soc-fixes-6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Arnd Bergmann:
"These are a couple of build fixes from randconfig testing, plus a set
of Mediatek SoC specific fixes, all trivial"
* tag 'soc-fixes-6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
soc: tegra: fix CPU_BIG_ENDIAN dependencies
ARM: disallow pre-ARMv5 builds with ld.lld
ARM: pxa: fix building with clang
MAINTAINERS: add related dts to IXP4xx
ARM: dts: spear: drop 0x from unit address
arm64: dts: mt8183: Fix Mali GPU clock
arm64: dts: mediatek: mt8195-demo: fix the memory size of node secmon
soc: mediatek: pm-domains: Fix the power glitch issue
+29
-7
+1
MAINTAINERS
+1
MAINTAINERS
···
2330
2330
F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt
2331
2331
F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
2332
2332
F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml
2333
+
F: arch/arm/boot/dts/intel-ixp*
2333
2334
F: arch/arm/mach-ixp4xx/
2334
2335
F: drivers/bus/intel-ixp4xx-eb.c
2335
2336
F: drivers/clocksource/timer-ixp4xx.c
+2
arch/arm/Kconfig
+2
arch/arm/Kconfig
···
345
345
config ARCH_MULTI_V4
346
346
bool "ARMv4 based platforms (FA526, StrongARM)"
347
347
depends on !ARCH_MULTI_V6_V7
348
+
depends on !LD_IS_LLD
348
349
select ARCH_MULTI_V4_V5
349
350
select CPU_FA526 if !(CPU_SA110 || CPU_SA1100)
350
351
351
352
config ARCH_MULTI_V4T
352
353
bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
353
354
depends on !ARCH_MULTI_V6_V7
355
+
depends on !LD_IS_LLD
354
356
select ARCH_MULTI_V4_V5
355
357
select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
356
358
CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
+1
-1
arch/arm/boot/dts/spear300.dtsi
+1
-1
arch/arm/boot/dts/spear300.dtsi
+1
-1
arch/arm/boot/dts/spear310.dtsi
+1
-1
arch/arm/boot/dts/spear310.dtsi
+1
-1
arch/arm/boot/dts/spear320.dtsi
+1
-1
arch/arm/boot/dts/spear320.dtsi
+8
arch/arm/mach-pxa/pxa27x.c
+8
arch/arm/mach-pxa/pxa27x.c
···
133
133
#ifndef CONFIG_IWMMXT
134
134
u64 acc0;
135
135
136
+
#ifndef CONFIG_AS_IS_LLVM
136
137
asm volatile(".arch_extension xscale\n\t"
137
138
"mra %Q0, %R0, acc0" : "=r" (acc0));
139
+
#else
140
+
asm volatile("mrrc p0, 0, %Q0, %R0, c0" : "=r" (acc0));
141
+
#endif
138
142
#endif
139
143
140
144
/* ensure voltage-change sequencer not initiated, which hangs */
···
157
153
case PM_SUSPEND_MEM:
158
154
cpu_suspend(pwrmode, pxa27x_finish_suspend);
159
155
#ifndef CONFIG_IWMMXT
156
+
#ifndef CONFIG_AS_IS_LLVM
160
157
asm volatile(".arch_extension xscale\n\t"
161
158
"mar acc0, %Q0, %R0" : "=r" (acc0));
159
+
#else
160
+
asm volatile("mcrr p0, 0, %Q0, %R0, c0" :: "r" (acc0));
161
+
#endif
162
162
#endif
163
163
break;
164
164
}
+8
arch/arm/mach-pxa/pxa3xx.c
+8
arch/arm/mach-pxa/pxa3xx.c
···
108
108
#ifndef CONFIG_IWMMXT
109
109
u64 acc0;
110
110
111
+
#ifdef CONFIG_CC_IS_GCC
111
112
asm volatile(".arch_extension xscale\n\t"
112
113
"mra %Q0, %R0, acc0" : "=r" (acc0));
114
+
#else
115
+
asm volatile("mrrc p0, 0, %Q0, %R0, c0" : "=r" (acc0));
116
+
#endif
113
117
#endif
114
118
115
119
/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
···
141
137
AD3ER = 0;
142
138
143
139
#ifndef CONFIG_IWMMXT
140
+
#ifndef CONFIG_AS_IS_LLVM
144
141
asm volatile(".arch_extension xscale\n\t"
145
142
"mar acc0, %Q0, %R0" : "=r" (acc0));
143
+
#else
144
+
asm volatile("mcrr p0, 0, %Q0, %R0, c0" :: "r" (acc0));
145
+
#endif
146
146
#endif
147
147
}
148
148
+1
-1
arch/arm64/boot/dts/mediatek/mt8183.dtsi
+1
-1
arch/arm64/boot/dts/mediatek/mt8183.dtsi
+2
-2
arch/arm64/boot/dts/mediatek/mt8195-demo.dts
+2
-2
arch/arm64/boot/dts/mediatek/mt8195-demo.dts
···
56
56
#size-cells = <2>;
57
57
ranges;
58
58
59
-
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
59
+
/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
60
60
bl31_secmon_reserved: secmon@54600000 {
61
61
no-map;
62
-
reg = <0 0x54600000 0x0 0x30000>;
62
+
reg = <0 0x54600000 0x0 0x200000>;
63
63
};
64
64
65
65
/* 12 MiB reserved for OP-TEE (BL32)
+1
-1
drivers/soc/mediatek/mtk-pm-domains.c
+1
-1
drivers/soc/mediatek/mtk-pm-domains.c
···
275
275
clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
276
276
277
277
/* subsys power off */
278
-
regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
279
278
regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);
280
279
regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT);
280
+
regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
281
281
regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT);
282
282
regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT);
283
283
+3
drivers/soc/tegra/Kconfig
+3
drivers/soc/tegra/Kconfig
···
95
95
96
96
config ARCH_TEGRA_186_SOC
97
97
bool "NVIDIA Tegra186 SoC"
98
+
depends on !CPU_BIG_ENDIAN
98
99
select MAILBOX
99
100
select TEGRA_BPMP
100
101
select TEGRA_HSP_MBOX
···
111
110
112
111
config ARCH_TEGRA_194_SOC
113
112
bool "NVIDIA Tegra194 SoC"
113
+
depends on !CPU_BIG_ENDIAN
114
114
select MAILBOX
115
115
select PINCTRL_TEGRA194
116
116
select TEGRA_BPMP
···
123
121
124
122
config ARCH_TEGRA_234_SOC
125
123
bool "NVIDIA Tegra234 SoC"
124
+
depends on !CPU_BIG_ENDIAN
126
125
select MAILBOX
127
126
select TEGRA_BPMP
128
127
select TEGRA_HSP_MBOX