Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-next-2025-02-01' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie:
"This is only AMD fixes:
amdgpu:
- GC 12 fix
- Aldebaran fix
- DCN 3.5 fix
- Freesync fix
amdkfd:
- Per queue reset fix
- MES fix"
* tag 'drm-next-2025-02-01' of https://gitlab.freedesktop.org/drm/kernel:
drm/amd/display: restore invalid MSA timing check for freesync
drm/amdkfd: only flush the validate MES contex
drm/amd/display: Correct register address in dcn35
drm/amd/pm: Mark MM activity as unsupported
drm/amd/amdgpu: change the config of cgcg on gfx12
drm/amdkfd: Block per-queue reset when halt_if_hws_hang=1
+16
-21
-11
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
-11
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
···
4021
4021
4022
4022
if (def != data)
4023
4023
WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4024
-
4025
-
data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
4026
-
data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
4027
-
WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
4028
-
4029
-
/* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
4030
-
if (adev->sdma.num_instances > 1) {
4031
-
data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
4032
-
data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
4033
-
WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
4034
-
}
4035
4024
}
4036
4025
}
4037
4026
+2
-2
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+2
-2
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
···
2325
2325
*/
2326
2326
mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ];
2327
2327
if (mqd_mgr->check_preemption_failed(mqd_mgr, dqm->packet_mgr.priv_queue->queue->mqd)) {
2328
+
while (halt_if_hws_hang)
2329
+
schedule();
2328
2330
if (reset_queues_on_hws_hang(dqm)) {
2329
-
while (halt_if_hws_hang)
2330
-
schedule();
2331
2331
dqm->is_hws_hang = true;
2332
2332
kfd_hws_hang(dqm);
2333
2333
retval = -ETIME;
+5
-2
drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+5
-2
drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
···
86
86
87
87
if (pdd->already_dequeued)
88
88
return;
89
-
89
+
/* The MES context flush needs to filter out the case which the
90
+
* KFD process is created without setting up the MES context and
91
+
* queue for creating a compute queue.
92
+
*/
90
93
dev->dqm->ops.process_termination(dev->dqm, &pdd->qpd);
91
-
if (dev->kfd->shared_resources.enable_mes &&
94
+
if (dev->kfd->shared_resources.enable_mes && !!pdd->proc_ctx_gpu_addr &&
92
95
down_read_trylock(&dev->adev->reset_domain->sem)) {
93
96
amdgpu_mes_flush_shader_debugger(dev->adev,
94
97
pdd->proc_ctx_gpu_addr);
+8
-4
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+8
-4
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
12326
12326
12327
12327
if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
12328
12328
sink->sink_signal == SIGNAL_TYPE_EDP)) {
12329
-
amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq;
12330
-
amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq;
12331
-
if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
12332
-
freesync_capable = true;
12329
+
if (amdgpu_dm_connector->dc_link &&
12330
+
amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) {
12331
+
amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq;
12332
+
amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq;
12333
+
if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
12334
+
freesync_capable = true;
12335
+
}
12336
+
12333
12337
parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
12334
12338
12335
12339
if (vsdb_info.replay_mode) {
+1
-1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+1
-1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
···
89
89
#define mmCLK1_CLK4_ALLOW_DS 0x16EA8
90
90
#define mmCLK1_CLK5_ALLOW_DS 0x16EB1
91
91
92
-
#define mmCLK5_spll_field_8 0x1B04B
92
+
#define mmCLK5_spll_field_8 0x1B24B
93
93
#define mmDENTIST_DISPCLK_CNTL 0x0124
94
94
#define regDENTIST_DISPCLK_CNTL 0x0064
95
95
#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1
-1
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
-1
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
···
1732
1732
1733
1733
gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1734
1734
gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
1735
-
gpu_metrics->average_mm_activity = 0;
1736
1735
1737
1736
/* Valid power data is available only from primary die */
1738
1737
if (aldebaran_is_primary(smu)) {