Merge tag 'mmc-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

+1

Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml

··· 16 16 - amd,pensando-elba-sd4hc 17 17 - microchip,mpfs-sd4hc 18 18 - microchip,pic64gx-sd4hc 19 + - mobileye,eyeq-sd4hc 19 20 - socionext,uniphier-sd4hc 20 21 - const: cdns,sd4hc 21 22

+112

Documentation/devicetree/bindings/mmc/loongson,ls2k0500-mmc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mmc/loongson,ls2k0500-mmc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: The SD/SDIO/eMMC host controller for Loongson-2K family SoCs 8 + 9 + description: 10 + The MMC host controller on the Loongson-2K0500/2K1000 (using an externally 11 + shared apbdma controller) provides the SD and SDIO device interfaces. 12 + The two MMC host controllers on the Loongson-2K2000 are similar, 13 + except that they use internal exclusive DMA. one controller provides 14 + the eMMC interface and the other provides the SD/SDIO interface. 15 + 16 + maintainers: 17 + - Binbin Zhou <zhoubinbin@loongson.cn> 18 + 19 + allOf: 20 + - $ref: mmc-controller.yaml# 21 + 22 + properties: 23 + compatible: 24 + enum: 25 + - loongson,ls2k0500-mmc 26 + - loongson,ls2k1000-mmc 27 + - loongson,ls2k2000-mmc 28 + 29 + reg: 30 + minItems: 1 31 + items: 32 + - description: Loongson-2K MMC controller registers. 33 + - description: APB DMA config register for Loongson-2K MMC controller. 34 + 35 + interrupts: 36 + maxItems: 1 37 + 38 + clocks: 39 + maxItems: 1 40 + 41 + dmas: 42 + maxItems: 1 43 + 44 + dma-names: 45 + const: rx-tx 46 + 47 + required: 48 + - compatible 49 + - reg 50 + - interrupts 51 + - clocks 52 + 53 + unevaluatedProperties: false 54 + 55 + if: 56 + properties: 57 + compatible: 58 + contains: 59 + enum: 60 + - loongson,ls2k0500-mmc 61 + - loongson,ls2k1000-mmc 62 + 63 + then: 64 + properties: 65 + reg: 66 + minItems: 2 67 + 68 + required: 69 + - dmas 70 + - dma-names 71 + 72 + else: 73 + properties: 74 + reg: 75 + maxItems: 1 76 + 77 + examples: 78 + - | 79 + #include <dt-bindings/gpio/gpio.h> 80 + #include <dt-bindings/interrupt-controller/irq.h> 81 + #include <dt-bindings/clock/loongson,ls2k-clk.h> 82 + 83 + mmc@1fe2c000 { 84 + compatible = "loongson,ls2k1000-mmc"; 85 + reg = <0x1fe2c000 0x68>, 86 + <0x1fe00438 0x8>; 87 + interrupt-parent = <&liointc0>; 88 + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; 89 + clocks = <&clk LOONGSON2_APB_CLK>; 90 + dmas = <&apbdma1 0>; 91 + dma-names = "rx-tx"; 92 + bus-width = <4>; 93 + cd-gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; 94 + }; 95 + 96 + - | 97 + #include <dt-bindings/interrupt-controller/irq.h> 98 + #include <dt-bindings/clock/loongson,ls2k-clk.h> 99 + 100 + mmc@79990000 { 101 + compatible = "loongson,ls2k2000-mmc"; 102 + reg = <0x79990000 0x1000>; 103 + interrupt-parent = <&pic>; 104 + interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; 105 + clocks = <&clk LOONGSON2_EMMC_CLK>; 106 + bus-width = <8>; 107 + non-removable; 108 + cap-mmc-highspeed; 109 + mmc-hs200-1_8v; 110 + no-sd; 111 + no-sdio; 112 + };

+6 -1

Documentation/devicetree/bindings/mmc/mxs-mmc.yaml

··· 17 17 and the properties used by the mxsmmc driver. 18 18 19 19 allOf: 20 - - $ref: mmc-controller.yaml 20 + - $ref: mmc-controller-common.yaml# 21 21 22 22 properties: 23 23 compatible: ··· 31 31 interrupts: 32 32 maxItems: 1 33 33 34 + clocks: 35 + maxItems: 1 36 + 34 37 dmas: 35 38 maxItems: 1 36 39 ··· 44 41 - compatible 45 42 - reg 46 43 - interrupts 44 + - clocks 47 45 - dmas 48 46 - dma-names 49 47 ··· 56 52 compatible = "fsl,imx28-mmc"; 57 53 reg = <0x80010000 2000>; 58 54 interrupts = <96>; 55 + clocks = <&clks 46>; 59 56 dmas = <&dma_apbh 0>; 60 57 dma-names = "rx-tx"; 61 58 bus-width = <8>;

+53 -32

Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml

··· 72 72 - enum: 73 73 - renesas,sdhi-r9a09g047 # RZ/G3E 74 74 - renesas,sdhi-r9a09g056 # RZ/V2N 75 + - renesas,sdhi-r9a09g077 # RZ/T2H 76 + - renesas,sdhi-r9a09g087 # RZ/N2H 75 77 - const: renesas,sdhi-r9a09g057 # RZ/V2H(P) 76 78 77 79 reg: ··· 131 129 compatible: 132 130 contains: 133 131 enum: 134 - - renesas,sdhi-r9a09g057 135 - - renesas,rzg2l-sdhi 132 + - renesas,sdhi-r9a09g077 133 + - renesas,sdhi-r9a09g087 136 134 then: 137 135 properties: 136 + resets: false 138 137 clocks: 139 138 items: 140 - - description: IMCLK, SDHI channel main clock1. 141 - - description: CLK_HS, SDHI channel High speed clock which operates 142 - 4 times that of SDHI channel main clock1. 143 - - description: IMCLK2, SDHI channel main clock2. When this clock is 144 - turned off, external SD card detection cannot be 145 - detected. 146 - - description: ACLK, SDHI channel bus clock. 139 + - description: ACLK, IMCLK, SDHI channel bus and main clocks. 140 + - description: CLK_HS, SDHI channel High speed clock. 147 141 clock-names: 148 142 items: 149 - - const: core 150 - - const: clkh 151 - - const: cd 152 143 - const: aclk 153 - required: 154 - - clock-names 155 - - resets 144 + - const: clkh 156 145 else: 157 146 if: 158 147 properties: 159 148 compatible: 160 149 contains: 161 150 enum: 162 - - renesas,rcar-gen2-sdhi 163 - - renesas,rcar-gen3-sdhi 164 - - renesas,rcar-gen4-sdhi 151 + - renesas,sdhi-r9a09g057 152 + - renesas,rzg2l-sdhi 165 153 then: 166 154 properties: 167 155 clocks: 168 - minItems: 1 169 - maxItems: 3 156 + items: 157 + - description: IMCLK, SDHI channel main clock1. 158 + - description: CLK_HS, SDHI channel High speed clock which operates 159 + 4 times that of SDHI channel main clock1. 160 + - description: IMCLK2, SDHI channel main clock2. When this clock is 161 + turned off, external SD card detection cannot be 162 + detected. 163 + - description: ACLK, SDHI channel bus clock. 170 164 clock-names: 171 - minItems: 1 172 - uniqueItems: true 173 165 items: 174 166 - const: core 175 - - enum: [ clkh, cd ] 167 + - const: clkh 176 168 - const: cd 169 + - const: aclk 170 + required: 171 + - clock-names 172 + - resets 177 173 else: 178 - properties: 179 - clocks: 180 - minItems: 1 181 - maxItems: 2 182 - clock-names: 183 - minItems: 1 184 - items: 185 - - const: core 186 - - const: cd 174 + if: 175 + properties: 176 + compatible: 177 + contains: 178 + enum: 179 + - renesas,rcar-gen2-sdhi 180 + - renesas,rcar-gen3-sdhi 181 + - renesas,rcar-gen4-sdhi 182 + then: 183 + properties: 184 + clocks: 185 + minItems: 1 186 + maxItems: 3 187 + clock-names: 188 + minItems: 1 189 + uniqueItems: true 190 + items: 191 + - const: core 192 + - enum: [ clkh, cd ] 193 + - const: cd 194 + else: 195 + properties: 196 + clocks: 197 + minItems: 1 198 + maxItems: 2 199 + clock-names: 200 + minItems: 1 201 + items: 202 + - const: core 203 + - const: cd 187 204 188 205 - if: 189 206 properties:

+2

Documentation/devicetree/bindings/mmc/sdhci-msm.yaml

··· 42 42 - qcom,ipq5424-sdhci 43 43 - qcom,ipq6018-sdhci 44 44 - qcom,ipq9574-sdhci 45 + - qcom,milos-sdhci 45 46 - qcom,qcm2290-sdhci 46 47 - qcom,qcs404-sdhci 47 48 - qcom,qcs615-sdhci 49 + - qcom,qcs8300-sdhci 48 50 - qcom,qdu1000-sdhci 49 51 - qcom,sar2130p-sdhci 50 52 - qcom,sc7180-sdhci

+7

MAINTAINERS

··· 14268 14268 F: Documentation/devicetree/bindings/hwinfo/loongson,ls2k-chipid.yaml 14269 14269 F: drivers/soc/loongson/loongson2_guts.c 14270 14270 14271 + LOONGSON-2 SOC SERIES MMC/SD/SDIO CONTROLLER DRIVER 14272 + M: Binbin Zhou <zhoubinbin@loongson.cn> 14273 + L: linux-mmc@vger.kernel.org 14274 + S: Maintained 14275 + F: Documentation/devicetree/bindings/mmc/loongson,ls2k0500-mmc.yaml 14276 + F: drivers/mmc/host/loongson2-mmc.c 14277 + 14271 14278 LOONGSON-2 SOC SERIES PM DRIVER 14272 14279 M: Yinbo Zhu <zhuyinbo@loongson.cn> 14273 14280 L: linux-pm@vger.kernel.org

-1

drivers/mmc/core/core.c

··· 882 882 WARN_ON(ctx && host->claimer != ctx); 883 883 884 884 mmc_release_host(host); 885 - pm_runtime_mark_last_busy(&card->dev); 886 885 pm_runtime_put_autosuspend(&card->dev); 887 886 } 888 887 EXPORT_SYMBOL(mmc_put_card);

+13

drivers/mmc/host/Kconfig

··· 1111 1111 This selects support for the SD/MMC Host Controller on 1112 1112 Actions Semi Owl SoCs. 1113 1113 1114 + config MMC_LOONGSON2 1115 + tristate "Loongson-2K SD/SDIO/eMMC Host Interface support" 1116 + depends on LOONGARCH || COMPILE_TEST 1117 + depends on HAS_DMA 1118 + help 1119 + This selects support for the SD/SDIO/eMMC Host Controller on 1120 + Loongson-2K series CPUs. 1121 + 1122 + To compile this driver as a module, choose M here: the 1123 + module will be called mmc_loongson2. 1124 + 1125 + If unsure, say N. 1126 + 1114 1127 config MMC_SDHCI_EXTERNAL_DMA 1115 1128 bool 1116 1129

+1

drivers/mmc/host/Makefile

··· 72 72 obj-$(CONFIG_MMC_TOSHIBA_PCI) += toshsd.o 73 73 obj-$(CONFIG_MMC_BCM2835) += bcm2835.o 74 74 obj-$(CONFIG_MMC_OWL) += owl-mmc.o 75 + obj-$(CONFIG_MMC_LOONGSON2) += loongson2-mmc.o 75 76 76 77 obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o 77 78 obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o

+5 -15

drivers/mmc/host/alcor.c

··· 1084 1084 struct alcor_sdmmc_host *host; 1085 1085 int ret; 1086 1086 1087 - mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1087 + mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(*host)); 1088 1088 if (!mmc) { 1089 1089 dev_err(&pdev->dev, "Can't allocate MMC\n"); 1090 1090 return -ENOMEM; ··· 1102 1102 ret = devm_request_threaded_irq(&pdev->dev, priv->irq, 1103 1103 alcor_irq, alcor_irq_thread, IRQF_SHARED, 1104 1104 DRV_NAME_ALCOR_PCI_SDMMC, host); 1105 - 1106 - if (ret) { 1107 - dev_err(&pdev->dev, "Failed to get irq for data line\n"); 1108 - goto free_host; 1109 - } 1105 + if (ret) 1106 + return dev_err_probe(&pdev->dev, ret, 1107 + "Failed to get irq for data line\n"); 1110 1108 1111 1109 mutex_init(&host->cmd_mutex); 1112 1110 INIT_DELAYED_WORK(&host->timeout_work, alcor_timeout_timer); ··· 1113 1115 alcor_hw_init(host); 1114 1116 1115 1117 dev_set_drvdata(&pdev->dev, host); 1116 - ret = mmc_add_host(mmc); 1117 - if (ret) 1118 - goto free_host; 1119 1118 1120 - return 0; 1121 - 1122 - free_host: 1123 - mmc_free_host(mmc); 1124 - return ret; 1119 + return mmc_add_host(mmc); 1125 1120 } 1126 1121 1127 1122 static void alcor_pci_sdmmc_drv_remove(struct platform_device *pdev) ··· 1127 1136 1128 1137 alcor_hw_uninit(host); 1129 1138 mmc_remove_host(mmc); 1130 - mmc_free_host(mmc); 1131 1139 } 1132 1140 1133 1141 #ifdef CONFIG_PM_SLEEP

+4 -8

drivers/mmc/host/atmel-mci.c

··· 38 38 #include <asm/cacheflush.h> 39 39 #include <asm/io.h> 40 40 #include <linux/unaligned.h> 41 + #include <linux/string_choices.h> 41 42 42 43 #define ATMCI_MAX_NR_SLOTS 2 43 44 ··· 542 541 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE); 543 542 spin_unlock_bh(&host->lock); 544 543 545 - pm_runtime_mark_last_busy(dev); 546 544 pm_runtime_put_autosuspend(dev); 547 545 548 546 seq_printf(s, "MR:\t0x%08x%s%s ", ··· 2248 2248 struct atmel_mci_slot *slot; 2249 2249 int ret; 2250 2250 2251 - mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), dev); 2251 + mmc = devm_mmc_alloc_host(dev, sizeof(*slot)); 2252 2252 if (!mmc) 2253 2253 return -ENOMEM; 2254 2254 ··· 2264 2264 "slot[%u]: bus_width=%u, detect_pin=%d, " 2265 2265 "detect_is_active_high=%s, wp_pin=%d\n", 2266 2266 id, slot_data->bus_width, desc_to_gpio(slot_data->detect_pin), 2267 - !gpiod_is_active_low(slot_data->detect_pin) ? "true" : "false", 2267 + str_true_false(!gpiod_is_active_low(slot_data->detect_pin)), 2268 2268 desc_to_gpio(slot_data->wp_pin)); 2269 2269 2270 2270 mmc->ops = &atmci_ops; ··· 2321 2321 host->slot[id] = slot; 2322 2322 mmc_regulator_get_supply(mmc); 2323 2323 ret = mmc_add_host(mmc); 2324 - if (ret) { 2325 - mmc_free_host(mmc); 2324 + if (ret) 2326 2325 return ret; 2327 - } 2328 2326 2329 2327 if (slot->detect_pin) { 2330 2328 timer_setup(&slot->detect_timer, atmci_detect_change, 0); ··· 2360 2362 } 2361 2363 2362 2364 slot->host->slot[id] = NULL; 2363 - mmc_free_host(slot->mmc); 2364 2365 } 2365 2366 2366 2367 static int atmci_configure_dma(struct atmel_mci *host) ··· 2567 2570 dev_info(dev, "Atmel MCI controller at 0x%08lx irq %d, %u slots\n", 2568 2571 host->mapbase, irq, nr_slots); 2569 2572 2570 - pm_runtime_mark_last_busy(dev); 2571 2573 pm_runtime_put_autosuspend(dev); 2572 2574 2573 2575 return 0;

+4 -10

drivers/mmc/host/au1xmmc.c

··· 937 937 struct resource *r; 938 938 int ret, iflag; 939 939 940 - mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev); 940 + mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(*host)); 941 941 if (!mmc) { 942 942 dev_err(&pdev->dev, "no memory for mmc_host\n"); 943 - ret = -ENOMEM; 944 - goto out0; 943 + return -ENOMEM; 945 944 } 946 945 947 946 host = mmc_priv(mmc); ··· 952 953 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 953 954 if (!r) { 954 955 dev_err(&pdev->dev, "no mmio defined\n"); 955 - goto out1; 956 + return ret; 956 957 } 957 958 958 959 host->ioarea = request_mem_region(r->start, resource_size(r), 959 960 pdev->name); 960 961 if (!host->ioarea) { 961 962 dev_err(&pdev->dev, "mmio already in use\n"); 962 - goto out1; 963 + return ret; 963 964 } 964 965 965 966 host->iobase = ioremap(r->start, 0x3c); ··· 1108 1109 out2: 1109 1110 release_resource(host->ioarea); 1110 1111 kfree(host->ioarea); 1111 - out1: 1112 - mmc_free_host(mmc); 1113 - out0: 1114 1112 return ret; 1115 1113 } 1116 1114 ··· 1147 1151 iounmap((void *)host->iobase); 1148 1152 release_resource(host->ioarea); 1149 1153 kfree(host->ioarea); 1150 - 1151 - mmc_free_host(host->mmc); 1152 1154 } 1153 1155 } 1154 1156

+1 -4

drivers/mmc/host/bcm2835.c

··· 1372 1372 int ret; 1373 1373 1374 1374 dev_dbg(dev, "%s\n", __func__); 1375 - mmc = mmc_alloc_host(sizeof(*host), dev); 1375 + mmc = devm_mmc_alloc_host(dev, sizeof(*host)); 1376 1376 if (!mmc) 1377 1377 return -ENOMEM; 1378 1378 ··· 1451 1451 dev_dbg(dev, "%s -> err %d\n", __func__, ret); 1452 1452 if (host->dma_chan_rxtx) 1453 1453 dma_release_channel(host->dma_chan_rxtx); 1454 - mmc_free_host(mmc); 1455 1454 1456 1455 return ret; 1457 1456 } ··· 1473 1474 1474 1475 if (host->dma_chan_rxtx) 1475 1476 dma_release_channel(host->dma_chan_rxtx); 1476 - 1477 - mmc_free_host(mmc); 1478 1477 } 1479 1478 1480 1479 static const struct of_device_id bcm2835_match[] = {

+2 -8

drivers/mmc/host/cavium.c

··· 1012 1012 struct mmc_host *mmc; 1013 1013 int ret, id; 1014 1014 1015 - mmc = mmc_alloc_host(sizeof(struct cvm_mmc_slot), dev); 1015 + mmc = devm_mmc_alloc_host(dev, sizeof(*slot)); 1016 1016 if (!mmc) 1017 1017 return -ENOMEM; 1018 1018 ··· 1022 1022 1023 1023 ret = cvm_mmc_of_parse(dev, slot); 1024 1024 if (ret < 0) 1025 - goto error; 1025 + return ret; 1026 1026 id = ret; 1027 1027 1028 1028 /* Set up host parameters */ ··· 1066 1066 if (ret) { 1067 1067 dev_err(dev, "mmc_add_host() returned %d\n", ret); 1068 1068 slot->host->slot[id] = NULL; 1069 - goto error; 1070 1069 } 1071 - return 0; 1072 - 1073 - error: 1074 - mmc_free_host(slot->mmc); 1075 1070 return ret; 1076 1071 } 1077 1072 ··· 1074 1079 { 1075 1080 mmc_remove_host(slot->mmc); 1076 1081 slot->host->slot[slot->bus_id] = NULL; 1077 - mmc_free_host(slot->mmc); 1078 1082 return 0; 1079 1083 }

+3 -5

drivers/mmc/host/cb710-mmc.c

··· 8 8 #include <linux/module.h> 9 9 #include <linux/pci.h> 10 10 #include <linux/delay.h> 11 + #include <linux/string_choices.h> 11 12 #include "cb710-mmc.h" 12 13 13 14 #define CB710_MMC_REQ_TIMEOUT_MS 2000 ··· 216 215 ((count - 1) << 16)|(blocksize - 1)); 217 216 218 217 dev_vdbg(cb710_slot_dev(slot), "set up for %zu block%s of %zu bytes\n", 219 - count, count == 1 ? "" : "s", blocksize); 218 + count, str_plural(count), blocksize); 220 219 } 221 220 222 221 static void cb710_mmc_fifo_hack(struct cb710_slot *slot) ··· 693 692 int err; 694 693 u32 val; 695 694 696 - mmc = mmc_alloc_host(sizeof(*reader), cb710_slot_dev(slot)); 695 + mmc = devm_mmc_alloc_host(cb710_slot_dev(slot), sizeof(*reader)); 697 696 if (!mmc) 698 697 return -ENOMEM; 699 698 ··· 742 741 dev_dbg(cb710_slot_dev(slot), "mmc_add_host() failed: %d\n", err); 743 742 744 743 cb710_set_irq_handler(slot, NULL); 745 - mmc_free_host(mmc); 746 744 return err; 747 745 } 748 746 ··· 764 764 cb710_write_port_16(slot, CB710_MMC_CONFIGB_PORT, 0); 765 765 766 766 cancel_work_sync(&reader->finish_req_bh_work); 767 - 768 - mmc_free_host(mmc); 769 767 } 770 768 771 769 static struct platform_driver cb710_mmc_driver = {

+7 -15

drivers/mmc/host/davinci_mmc.c

··· 1203 1203 if (!mem) 1204 1204 return -EBUSY; 1205 1205 1206 - mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev); 1206 + mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(*host)); 1207 1207 if (!mmc) 1208 1208 return -ENOMEM; 1209 1209 ··· 1212 1212 1213 1213 host->mem_res = mem; 1214 1214 host->base = devm_ioremap(&pdev->dev, mem->start, mem_size); 1215 - if (!host->base) { 1216 - ret = -ENOMEM; 1217 - goto ioremap_fail; 1218 - } 1215 + if (!host->base) 1216 + return -ENOMEM; 1219 1217 1220 1218 host->clk = devm_clk_get(&pdev->dev, NULL); 1221 - if (IS_ERR(host->clk)) { 1222 - ret = PTR_ERR(host->clk); 1223 - goto clk_get_fail; 1224 - } 1219 + if (IS_ERR(host->clk)) 1220 + return PTR_ERR(host->clk); 1221 + 1225 1222 ret = clk_prepare_enable(host->clk); 1226 1223 if (ret) 1227 - goto clk_prepare_enable_fail; 1224 + return ret; 1228 1225 1229 1226 host->mmc_input_clk = clk_get_rate(host->clk); 1230 1227 ··· 1333 1336 parse_fail: 1334 1337 dma_probe_defer: 1335 1338 clk_disable_unprepare(host->clk); 1336 - clk_prepare_enable_fail: 1337 - clk_get_fail: 1338 - ioremap_fail: 1339 - mmc_free_host(mmc); 1340 1339 1341 1340 return ret; 1342 1341 } ··· 1345 1352 mmc_davinci_cpufreq_deregister(host); 1346 1353 davinci_release_dma_channels(host); 1347 1354 clk_disable_unprepare(host->clk); 1348 - mmc_free_host(host->mmc); 1349 1355 } 1350 1356 1351 1357 #ifdef CONFIG_PM

+5 -10

drivers/mmc/host/dw_mmc.c

··· 3008 3008 struct dw_mci_slot *slot; 3009 3009 int ret; 3010 3010 3011 - mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 3011 + mmc = devm_mmc_alloc_host(host->dev, sizeof(*slot)); 3012 3012 if (!mmc) 3013 3013 return -ENOMEM; 3014 3014 ··· 3024 3024 /*if there are external regulators, get them*/ 3025 3025 ret = mmc_regulator_get_supply(mmc); 3026 3026 if (ret) 3027 - goto err_host_allocated; 3027 + return ret; 3028 3028 3029 3029 if (!mmc->ocr_avail) 3030 3030 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 3031 3031 3032 3032 ret = mmc_of_parse(mmc); 3033 3033 if (ret) 3034 - goto err_host_allocated; 3034 + return ret; 3035 3035 3036 3036 ret = dw_mci_init_slot_caps(slot); 3037 3037 if (ret) 3038 - goto err_host_allocated; 3038 + return ret; 3039 3039 3040 3040 /* Useful defaults if platform data is unset. */ 3041 3041 if (host->use_dma == TRANS_MODE_IDMAC) { ··· 3065 3065 3066 3066 ret = mmc_add_host(mmc); 3067 3067 if (ret) 3068 - goto err_host_allocated; 3068 + return ret; 3069 3069 3070 3070 #if defined(CONFIG_DEBUG_FS) 3071 3071 dw_mci_init_debugfs(slot); 3072 3072 #endif 3073 3073 3074 3074 return 0; 3075 - 3076 - err_host_allocated: 3077 - mmc_free_host(mmc); 3078 - return ret; 3079 3075 } 3080 3076 3081 3077 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot) ··· 3079 3083 /* Debugfs stuff is cleaned up by mmc core */ 3080 3084 mmc_remove_host(slot->mmc); 3081 3085 slot->host->slot = NULL; 3082 - mmc_free_host(slot->mmc); 3083 3086 } 3084 3087 3085 3088 static void dw_mci_init_dma(struct dw_mci *host)

+13 -27

drivers/mmc/host/jz4740_mmc.c

··· 1043 1043 struct mmc_host *mmc; 1044 1044 struct jz4740_mmc_host *host; 1045 1045 1046 - mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev); 1046 + mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(*host)); 1047 1047 if (!mmc) { 1048 1048 dev_err(&pdev->dev, "Failed to alloc mmc host structure\n"); 1049 1049 return -ENOMEM; ··· 1055 1055 host->version = (enum jz4740_mmc_version)device_get_match_data(&pdev->dev); 1056 1056 1057 1057 ret = mmc_of_parse(mmc); 1058 - if (ret) { 1059 - dev_err_probe(&pdev->dev, ret, "could not parse device properties\n"); 1060 - goto err_free_host; 1061 - } 1058 + if (ret) 1059 + return dev_err_probe(&pdev->dev, ret, 1060 + "could not parse device properties\n"); 1062 1061 1063 1062 mmc_regulator_get_supply(mmc); 1064 1063 1065 1064 host->irq = platform_get_irq(pdev, 0); 1066 - if (host->irq < 0) { 1067 - ret = host->irq; 1068 - goto err_free_host; 1069 - } 1065 + if (host->irq < 0) 1066 + return host->irq; 1070 1067 1071 1068 host->clk = devm_clk_get(&pdev->dev, "mmc"); 1072 - if (IS_ERR(host->clk)) { 1073 - ret = PTR_ERR(host->clk); 1074 - dev_err(&pdev->dev, "Failed to get mmc clock\n"); 1075 - goto err_free_host; 1076 - } 1069 + if (IS_ERR(host->clk)) 1070 + return dev_err_probe(&pdev->dev, PTR_ERR(host->clk), 1071 + "Failed to get mmc clock\n"); 1077 1072 1078 1073 host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &host->mem_res); 1079 - if (IS_ERR(host->base)) { 1080 - ret = PTR_ERR(host->base); 1081 - goto err_free_host; 1082 - } 1074 + if (IS_ERR(host->base)) 1075 + return PTR_ERR(host->base); 1083 1076 1084 1077 mmc->ops = &jz4740_mmc_ops; 1085 1078 if (!mmc->f_max) ··· 1112 1119 1113 1120 ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0, 1114 1121 dev_name(&pdev->dev), host); 1115 - if (ret) { 1116 - dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); 1117 - goto err_free_host; 1118 - } 1122 + if (ret) 1123 + return dev_err_probe(&pdev->dev, ret, "Failed to request irq\n"); 1119 1124 1120 1125 jz4740_mmc_clock_disable(host); 1121 1126 timer_setup(&host->timeout_timer, jz4740_mmc_timeout, 0); ··· 1144 1153 jz4740_mmc_release_dma_channels(host); 1145 1154 err_free_irq: 1146 1155 free_irq(host->irq, host); 1147 - err_free_host: 1148 - mmc_free_host(mmc); 1149 - 1150 1156 return ret; 1151 1157 } 1152 1158 ··· 1161 1173 1162 1174 if (host->use_dma) 1163 1175 jz4740_mmc_release_dma_channels(host); 1164 - 1165 - mmc_free_host(host->mmc); 1166 1176 } 1167 1177 1168 1178 static int jz4740_mmc_suspend(struct device *dev)

+1 -11

drivers/mmc/host/litex_mmc.c

··· 506 506 return 0; 507 507 } 508 508 509 - static void litex_mmc_free_host_wrapper(void *mmc) 510 - { 511 - mmc_free_host(mmc); 512 - } 513 - 514 509 static int litex_mmc_probe(struct platform_device *pdev) 515 510 { 516 511 struct device *dev = &pdev->dev; ··· 520 525 * If for some reason we need to modify max_blk_count, we must also 521 526 * re-calculate `max_[req,seg]_size = max_blk_size * max_blk_count;` 522 527 */ 523 - mmc = mmc_alloc_host(sizeof(struct litex_mmc_host), dev); 528 + mmc = devm_mmc_alloc_host(dev, sizeof(*host)); 524 529 if (!mmc) 525 530 return -ENOMEM; 526 - 527 - ret = devm_add_action_or_reset(dev, litex_mmc_free_host_wrapper, mmc); 528 - if (ret) 529 - return dev_err_probe(dev, ret, 530 - "Can't register mmc_free_host action\n"); 531 531 532 532 host = mmc_priv(mmc); 533 533 host->mmc = mmc;

+1030

drivers/mmc/host/loongson2-mmc.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Loongson-2K MMC/SDIO controller driver 4 + * 5 + * Copyright (C) 2018-2025 Loongson Technology Corporation Limited. 6 + * 7 + */ 8 + 9 + #include <linux/bitfield.h> 10 + #include <linux/bitrev.h> 11 + #include <linux/clk.h> 12 + #include <linux/delay.h> 13 + #include <linux/dmaengine.h> 14 + #include <linux/dma-mapping.h> 15 + #include <linux/interrupt.h> 16 + #include <linux/io.h> 17 + #include <linux/mmc/core.h> 18 + #include <linux/mmc/host.h> 19 + #include <linux/mmc/mmc.h> 20 + #include <linux/mmc/sd.h> 21 + #include <linux/mmc/sdio.h> 22 + #include <linux/mmc/slot-gpio.h> 23 + #include <linux/module.h> 24 + #include <linux/of.h> 25 + #include <linux/platform_device.h> 26 + #include <linux/regmap.h> 27 + 28 + #define LOONGSON2_MMC_REG_CTL 0x00 /* Control Register */ 29 + #define LOONGSON2_MMC_REG_PRE 0x04 /* Prescaler Register */ 30 + #define LOONGSON2_MMC_REG_CARG 0x08 /* Command Register */ 31 + #define LOONGSON2_MMC_REG_CCTL 0x0c /* Command Control Register */ 32 + #define LOONGSON2_MMC_REG_CSTS 0x10 /* Command Status Register */ 33 + #define LOONGSON2_MMC_REG_RSP0 0x14 /* Command Response Register 0 */ 34 + #define LOONGSON2_MMC_REG_RSP1 0x18 /* Command Response Register 1 */ 35 + #define LOONGSON2_MMC_REG_RSP2 0x1c /* Command Response Register 2 */ 36 + #define LOONGSON2_MMC_REG_RSP3 0x20 /* Command Response Register 3 */ 37 + #define LOONGSON2_MMC_REG_TIMER 0x24 /* Data Timeout Register */ 38 + #define LOONGSON2_MMC_REG_BSIZE 0x28 /* Block Size Register */ 39 + #define LOONGSON2_MMC_REG_DCTL 0x2c /* Data Control Register */ 40 + #define LOONGSON2_MMC_REG_DCNT 0x30 /* Data Counter Register */ 41 + #define LOONGSON2_MMC_REG_DSTS 0x34 /* Data Status Register */ 42 + #define LOONGSON2_MMC_REG_FSTS 0x38 /* FIFO Status Register */ 43 + #define LOONGSON2_MMC_REG_INT 0x3c /* Interrupt Register */ 44 + #define LOONGSON2_MMC_REG_DATA 0x40 /* Data Register */ 45 + #define LOONGSON2_MMC_REG_IEN 0x64 /* Interrupt Enable Register */ 46 + 47 + /* EMMC DLL Mode Registers */ 48 + #define LOONGSON2_MMC_REG_DLLVAL 0xf0 /* DLL Master Lock-value Register */ 49 + #define LOONGSON2_MMC_REG_DLLCTL 0xf4 /* DLL Control Register */ 50 + #define LOONGSON2_MMC_REG_DELAY 0xf8 /* DLL Delayed Parameter Register */ 51 + #define LOONGSON2_MMC_REG_SEL 0xfc /* Bus Mode Selection Register */ 52 + 53 + /* Exclusive DMA R/W Registers */ 54 + #define LOONGSON2_MMC_REG_WDMA_LO 0x400 55 + #define LOONGSON2_MMC_REG_WDMA_HI 0x404 56 + #define LOONGSON2_MMC_REG_RDMA_LO 0x800 57 + #define LOONGSON2_MMC_REG_RDMA_HI 0x804 58 + 59 + /* Bitfields of control register */ 60 + #define LOONGSON2_MMC_CTL_ENCLK BIT(0) 61 + #define LOONGSON2_MMC_CTL_EXTCLK BIT(1) 62 + #define LOONGSON2_MMC_CTL_RESET BIT(8) 63 + 64 + /* Bitfields of prescaler register */ 65 + #define LOONGSON2_MMC_PRE GENMASK(9, 0) 66 + #define LOONGSON2_MMC_PRE_EN BIT(31) 67 + 68 + /* Bitfields of command control register */ 69 + #define LOONGSON2_MMC_CCTL_INDEX GENMASK(5, 0) 70 + #define LOONGSON2_MMC_CCTL_HOST BIT(6) 71 + #define LOONGSON2_MMC_CCTL_START BIT(8) 72 + #define LOONGSON2_MMC_CCTL_WAIT_RSP BIT(9) 73 + #define LOONGSON2_MMC_CCTL_LONG_RSP BIT(10) 74 + #define LOONGSON2_MMC_CCTL_ABORT BIT(12) 75 + #define LOONGSON2_MMC_CCTL_CHECK BIT(13) 76 + #define LOONGSON2_MMC_CCTL_SDIO BIT(14) 77 + #define LOONGSON2_MMC_CCTL_CMD6 BIT(18) 78 + 79 + /* Bitfields of command status register */ 80 + #define LOONGSON2_MMC_CSTS_INDEX GENMASK(7, 0) 81 + #define LOONGSON2_MMC_CSTS_ON BIT(8) 82 + #define LOONGSON2_MMC_CSTS_RSP BIT(9) 83 + #define LOONGSON2_MMC_CSTS_TIMEOUT BIT(10) 84 + #define LOONGSON2_MMC_CSTS_END BIT(11) 85 + #define LOONGSON2_MMC_CSTS_CRC_ERR BIT(12) 86 + #define LOONGSON2_MMC_CSTS_AUTO_STOP BIT(13) 87 + #define LOONGSON2_MMC_CSTS_FIN BIT(14) 88 + 89 + /* Bitfields of data timeout register */ 90 + #define LOONGSON2_MMC_DTIMR GENMASK(23, 0) 91 + 92 + /* Bitfields of block size register */ 93 + #define LOONGSON2_MMC_BSIZE GENMASK(11, 0) 94 + 95 + /* Bitfields of data control register */ 96 + #define LOONGSON2_MMC_DCTL_BNUM GENMASK(11, 0) 97 + #define LOONGSON2_MMC_DCTL_START BIT(14) 98 + #define LOONGSON2_MMC_DCTL_ENDMA BIT(15) 99 + #define LOONGSON2_MMC_DCTL_WIDE BIT(16) 100 + #define LOONGSON2_MMC_DCTL_RWAIT BIT(17) 101 + #define LOONGSON2_MMC_DCTL_IO_SUSPEND BIT(18) 102 + #define LOONGSON2_MMC_DCTL_IO_RESUME BIT(19) 103 + #define LOONGSON2_MMC_DCTL_RW_RESUME BIT(20) 104 + #define LOONGSON2_MMC_DCTL_8BIT_BUS BIT(26) 105 + 106 + /* Bitfields of sata counter register */ 107 + #define LOONGSON2_MMC_DCNT_BNUM GENMASK(11, 0) 108 + #define LOONGSON2_MMC_DCNT_BYTE GENMASK(23, 12) 109 + 110 + /* Bitfields of command status register */ 111 + #define LOONGSON2_MMC_DSTS_RXON BIT(0) 112 + #define LOONGSON2_MMC_DSTS_TXON BIT(1) 113 + #define LOONGSON2_MMC_DSTS_SBITERR BIT(2) 114 + #define LOONGSON2_MMC_DSTS_BUSYFIN BIT(3) 115 + #define LOONGSON2_MMC_DSTS_XFERFIN BIT(4) 116 + #define LOONGSON2_MMC_DSTS_DTIMEOUT BIT(5) 117 + #define LOONGSON2_MMC_DSTS_RXCRC BIT(6) 118 + #define LOONGSON2_MMC_DSTS_TXCRC BIT(7) 119 + #define LOONGSON2_MMC_DSTS_IRQ BIT(8) 120 + #define LOONGSON2_MMC_DSTS_START BIT(13) 121 + #define LOONGSON2_MMC_DSTS_RESUME BIT(15) 122 + #define LOONGSON2_MMC_DSTS_SUSPEND BIT(16) 123 + 124 + /* Bitfields of FIFO Status Register */ 125 + #define LOONGSON2_MMC_FSTS_TXFULL BIT(11) 126 + 127 + /* Bitfields of interrupt register */ 128 + #define LOONGSON2_MMC_INT_DFIN BIT(0) 129 + #define LOONGSON2_MMC_INT_DTIMEOUT BIT(1) 130 + #define LOONGSON2_MMC_INT_RXCRC BIT(2) 131 + #define LOONGSON2_MMC_INT_TXCRC BIT(3) 132 + #define LOONGSON2_MMC_INT_PROGERR BIT(4) 133 + #define LOONGSON2_MMC_INT_SDIOIRQ BIT(5) 134 + #define LOONGSON2_MMC_INT_CSENT BIT(6) 135 + #define LOONGSON2_MMC_INT_CTIMEOUT BIT(7) 136 + #define LOONGSON2_MMC_INT_RESPCRC BIT(8) 137 + #define LOONGSON2_MMC_INT_BUSYEND BIT(9) 138 + 139 + /* Bitfields of interrupt enable register */ 140 + #define LOONGSON2_MMC_IEN_DFIN BIT(0) 141 + #define LOONGSON2_MMC_IEN_DTIMEOUT BIT(1) 142 + #define LOONGSON2_MMC_IEN_RXCRC BIT(2) 143 + #define LOONGSON2_MMC_IEN_TXCRC BIT(3) 144 + #define LOONGSON2_MMC_IEN_PROGERR BIT(4) 145 + #define LOONGSON2_MMC_IEN_SDIOIRQ BIT(5) 146 + #define LOONGSON2_MMC_IEN_CSENT BIT(6) 147 + #define LOONGSON2_MMC_IEN_CTIMEOUT BIT(7) 148 + #define LOONGSON2_MMC_IEN_RESPCRC BIT(8) 149 + #define LOONGSON2_MMC_IEN_BUSYEND BIT(9) 150 + 151 + #define LOONGSON2_MMC_IEN_ALL GENMASK(9, 0) 152 + #define LOONGSON2_MMC_INT_CLEAR GENMASK(9, 0) 153 + 154 + /* Bitfields of DLL master lock-value register */ 155 + #define LOONGSON2_MMC_DLLVAL_DONE BIT(8) 156 + 157 + /* Bitfields of DLL control register */ 158 + #define LOONGSON2_MMC_DLLCTL_TIME GENMASK(7, 0) 159 + #define LOONGSON2_MMC_DLLCTL_INCRE GENMASK(15, 8) 160 + #define LOONGSON2_MMC_DLLCTL_START GENMASK(23, 16) 161 + #define LOONGSON2_MMC_DLLCTL_CLK_MODE BIT(24) 162 + #define LOONGSON2_MMC_DLLCTL_START_BIT BIT(25) 163 + #define LOONGSON2_MMC_DLLCTL_TIME_BPASS GENMASK(29, 26) 164 + 165 + #define LOONGSON2_MMC_DELAY_PAD GENMASK(7, 0) 166 + #define LOONGSON2_MMC_DELAY_RD GENMASK(15, 8) 167 + 168 + #define LOONGSON2_MMC_SEL_DATA BIT(0) /* 0: SDR, 1: DDR */ 169 + #define LOONGSON2_MMC_SEL_BUS BIT(0) /* 0: EMMC, 1: SDIO */ 170 + 171 + /* Internal dma controller registers */ 172 + 173 + /* Bitfields of Global Configuration Register */ 174 + #define LOONGSON2_MMC_DMA_64BIT_EN BIT(0) /* 1: 64 bit support */ 175 + #define LOONGSON2_MMC_DMA_UNCOHERENT_EN BIT(1) /* 0: cache, 1: uncache */ 176 + #define LOONGSON2_MMC_DMA_ASK_VALID BIT(2) 177 + #define LOONGSON2_MMC_DMA_START BIT(3) /* DMA start operation */ 178 + #define LOONGSON2_MMC_DMA_STOP BIT(4) /* DMA stop operation */ 179 + #define LOONGSON2_MMC_DMA_CONFIG_MASK GENMASK_ULL(4, 0) /* DMA controller config bits mask */ 180 + 181 + /* Bitfields of ndesc_addr field of HW descriptor */ 182 + #define LOONGSON2_MMC_DMA_DESC_EN BIT(0) /*1: The next descriptor is valid */ 183 + #define LOONGSON2_MMC_DMA_DESC_ADDR_LOW GENMASK(31, 1) 184 + 185 + /* Bitfields of cmd field of HW descriptor */ 186 + #define LOONGSON2_MMC_DMA_INT BIT(1) /* Enable DMA interrupts */ 187 + #define LOONGSON2_MMC_DMA_DATA_DIR BIT(12) /* 1: write to device, 0: read from device */ 188 + 189 + #define LOONGSON2_MMC_DLLVAL_TIMEOUT_US 4000 190 + #define LOONGSON2_MMC_TXFULL_TIMEOUT_US 500 191 + 192 + /* Loongson-2K1000 SDIO2 DMA routing register */ 193 + #define LS2K1000_SDIO_DMA_MASK GENMASK(17, 15) 194 + #define LS2K1000_DMA0_CONF 0x0 195 + #define LS2K1000_DMA1_CONF 0x1 196 + #define LS2K1000_DMA2_CONF 0x2 197 + #define LS2K1000_DMA3_CONF 0x3 198 + #define LS2K1000_DMA4_CONF 0x4 199 + 200 + /* Loongson-2K0500 SDIO2 DMA routing register */ 201 + #define LS2K0500_SDIO_DMA_MASK GENMASK(15, 14) 202 + #define LS2K0500_DMA0_CONF 0x1 203 + #define LS2K0500_DMA1_CONF 0x2 204 + #define LS2K0500_DMA2_CONF 0x3 205 + 206 + enum loongson2_mmc_state { 207 + STATE_NONE, 208 + STATE_FINALIZE, 209 + STATE_CMDSENT, 210 + STATE_RSPFIN, 211 + STATE_XFERFINISH, 212 + STATE_XFERFINISH_RSPFIN, 213 + }; 214 + 215 + struct loongson2_dma_desc { 216 + u32 ndesc_addr; 217 + u32 mem_addr; 218 + u32 apb_addr; 219 + u32 len; 220 + u32 step_len; 221 + u32 step_times; 222 + u32 cmd; 223 + u32 stats; 224 + u32 high_ndesc_addr; 225 + u32 high_mem_addr; 226 + u32 reserved[2]; 227 + } __packed; 228 + 229 + struct loongson2_mmc_host { 230 + struct device *dev; 231 + struct mmc_request *mrq; 232 + struct regmap *regmap; 233 + struct resource *res; 234 + struct clk *clk; 235 + u32 current_clk; 236 + void *sg_cpu; 237 + dma_addr_t sg_dma; 238 + int dma_complete; 239 + struct dma_chan *chan; 240 + int cmd_is_stop; 241 + int bus_width; 242 + spinlock_t lock; /* Prevent races with irq handler */ 243 + enum loongson2_mmc_state state; 244 + const struct loongson2_mmc_pdata *pdata; 245 + }; 246 + 247 + struct loongson2_mmc_pdata { 248 + const struct regmap_config *regmap_config; 249 + void (*reorder_cmd_data)(struct loongson2_mmc_host *host, struct mmc_command *cmd); 250 + void (*fix_data_timeout)(struct loongson2_mmc_host *host, struct mmc_command *cmd); 251 + int (*setting_dma)(struct loongson2_mmc_host *host, struct platform_device *pdev); 252 + int (*prepare_dma)(struct loongson2_mmc_host *host, struct mmc_data *data); 253 + void (*release_dma)(struct loongson2_mmc_host *host, struct device *dev); 254 + }; 255 + 256 + static void loongson2_mmc_send_command(struct loongson2_mmc_host *host, 257 + struct mmc_command *cmd) 258 + { 259 + u32 cctrl; 260 + 261 + if (cmd->data) 262 + host->state = STATE_XFERFINISH_RSPFIN; 263 + else if (cmd->flags & MMC_RSP_PRESENT) 264 + host->state = STATE_RSPFIN; 265 + else 266 + host->state = STATE_CMDSENT; 267 + 268 + regmap_write(host->regmap, LOONGSON2_MMC_REG_CARG, cmd->arg); 269 + 270 + cctrl = FIELD_PREP(LOONGSON2_MMC_CCTL_INDEX, cmd->opcode); 271 + cctrl |= LOONGSON2_MMC_CCTL_HOST | LOONGSON2_MMC_CCTL_START; 272 + 273 + if (cmd->opcode == SD_SWITCH && cmd->data) 274 + cctrl |= LOONGSON2_MMC_CCTL_CMD6; 275 + 276 + if (cmd->flags & MMC_RSP_PRESENT) 277 + cctrl |= LOONGSON2_MMC_CCTL_WAIT_RSP; 278 + 279 + if (cmd->flags & MMC_RSP_136) 280 + cctrl |= LOONGSON2_MMC_CCTL_LONG_RSP; 281 + 282 + regmap_write(host->regmap, LOONGSON2_MMC_REG_CCTL, cctrl); 283 + } 284 + 285 + static int loongson2_mmc_setup_data(struct loongson2_mmc_host *host, 286 + struct mmc_data *data) 287 + { 288 + u32 dctrl; 289 + 290 + if ((data->blksz & 3) != 0) 291 + return -EINVAL; 292 + 293 + dctrl = FIELD_PREP(LOONGSON2_MMC_DCTL_BNUM, data->blocks); 294 + dctrl |= LOONGSON2_MMC_DCTL_START | LOONGSON2_MMC_DCTL_ENDMA; 295 + 296 + if (host->bus_width == MMC_BUS_WIDTH_4) 297 + dctrl |= LOONGSON2_MMC_DCTL_WIDE; 298 + else if (host->bus_width == MMC_BUS_WIDTH_8) 299 + dctrl |= LOONGSON2_MMC_DCTL_8BIT_BUS; 300 + 301 + regmap_write(host->regmap, LOONGSON2_MMC_REG_DCTL, dctrl); 302 + regmap_write(host->regmap, LOONGSON2_MMC_REG_BSIZE, data->blksz); 303 + regmap_write(host->regmap, LOONGSON2_MMC_REG_TIMER, U32_MAX); 304 + 305 + return 0; 306 + } 307 + 308 + static int loongson2_mmc_prepare_dma(struct loongson2_mmc_host *host, 309 + struct mmc_data *data) 310 + { 311 + int ret; 312 + 313 + if (!data) 314 + return 0; 315 + 316 + ret = loongson2_mmc_setup_data(host, data); 317 + if (ret) 318 + return ret; 319 + 320 + host->dma_complete = 0; 321 + 322 + return host->pdata->prepare_dma(host, data); 323 + } 324 + 325 + static void loongson2_mmc_send_request(struct mmc_host *mmc) 326 + { 327 + int ret; 328 + struct loongson2_mmc_host *host = mmc_priv(mmc); 329 + struct mmc_request *mrq = host->mrq; 330 + struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd; 331 + 332 + ret = loongson2_mmc_prepare_dma(host, cmd->data); 333 + if (ret) { 334 + dev_err(host->dev, "DMA data prepared failed with %d\n", ret); 335 + cmd->error = ret; 336 + cmd->data->error = ret; 337 + mmc_request_done(mmc, mrq); 338 + return; 339 + } 340 + 341 + if (host->pdata->fix_data_timeout) 342 + host->pdata->fix_data_timeout(host, cmd); 343 + 344 + loongson2_mmc_send_command(host, cmd); 345 + 346 + /* Fix deselect card */ 347 + if (cmd->opcode == MMC_SELECT_CARD && cmd->arg == 0) { 348 + cmd->error = 0; 349 + mmc_request_done(mmc, mrq); 350 + } 351 + } 352 + 353 + static irqreturn_t loongson2_mmc_irq_worker(int irq, void *devid) 354 + { 355 + struct loongson2_mmc_host *host = (struct loongson2_mmc_host *)devid; 356 + struct mmc_host *mmc = mmc_from_priv(host); 357 + struct mmc_request *mrq = host->mrq; 358 + struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd; 359 + 360 + if (cmd->data) 361 + dma_unmap_sg(mmc_dev(mmc), cmd->data->sg, cmd->data->sg_len, 362 + mmc_get_dma_dir(cmd->data)); 363 + 364 + if (cmd->data && !cmd->error && 365 + !cmd->data->error && !host->dma_complete) 366 + return IRQ_HANDLED; 367 + 368 + /* Read response from controller. */ 369 + regmap_read(host->regmap, LOONGSON2_MMC_REG_RSP0, &cmd->resp[0]); 370 + regmap_read(host->regmap, LOONGSON2_MMC_REG_RSP1, &cmd->resp[1]); 371 + regmap_read(host->regmap, LOONGSON2_MMC_REG_RSP2, &cmd->resp[2]); 372 + regmap_read(host->regmap, LOONGSON2_MMC_REG_RSP3, &cmd->resp[3]); 373 + 374 + /* Cleanup controller */ 375 + regmap_write(host->regmap, LOONGSON2_MMC_REG_CARG, 0); 376 + regmap_write(host->regmap, LOONGSON2_MMC_REG_CCTL, 0); 377 + 378 + if (cmd->data && cmd->error) 379 + cmd->data->error = cmd->error; 380 + 381 + if (cmd->data && cmd->data->stop && !host->cmd_is_stop) { 382 + host->cmd_is_stop = 1; 383 + loongson2_mmc_send_request(mmc); 384 + return IRQ_HANDLED; 385 + } 386 + 387 + /* If we have no data transfer we are finished here */ 388 + if (!mrq->data) 389 + goto request_done; 390 + 391 + /* Calculate the amount of bytes transfer if there was no error */ 392 + if (mrq->data->error == 0) { 393 + mrq->data->bytes_xfered = 394 + (mrq->data->blocks * mrq->data->blksz); 395 + } else { 396 + mrq->data->bytes_xfered = 0; 397 + } 398 + 399 + request_done: 400 + host->state = STATE_NONE; 401 + host->mrq = NULL; 402 + mmc_request_done(mmc, mrq); 403 + return IRQ_HANDLED; 404 + } 405 + 406 + static irqreturn_t loongson2_mmc_irq(int irq, void *devid) 407 + { 408 + struct loongson2_mmc_host *host = (struct loongson2_mmc_host *)devid; 409 + struct mmc_host *mmc = mmc_from_priv(host); 410 + struct mmc_command *cmd; 411 + unsigned long iflags; 412 + u32 dsts, imsk; 413 + 414 + regmap_read(host->regmap, LOONGSON2_MMC_REG_INT, &imsk); 415 + regmap_read(host->regmap, LOONGSON2_MMC_REG_DSTS, &dsts); 416 + 417 + if ((dsts & LOONGSON2_MMC_DSTS_IRQ) && 418 + (imsk & LOONGSON2_MMC_INT_SDIOIRQ)) { 419 + regmap_update_bits(host->regmap, LOONGSON2_MMC_REG_INT, 420 + LOONGSON2_MMC_INT_SDIOIRQ, LOONGSON2_MMC_INT_SDIOIRQ); 421 + 422 + sdio_signal_irq(mmc); 423 + return IRQ_HANDLED; 424 + } 425 + 426 + spin_lock_irqsave(&host->lock, iflags); 427 + 428 + if (host->state == STATE_NONE || host->state == STATE_FINALIZE || !host->mrq) 429 + goto irq_out; 430 + 431 + cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd; 432 + if (!cmd) 433 + goto irq_out; 434 + 435 + cmd->error = 0; 436 + 437 + if (imsk & LOONGSON2_MMC_INT_CTIMEOUT) { 438 + cmd->error = -ETIMEDOUT; 439 + goto close_transfer; 440 + } 441 + 442 + if (imsk & LOONGSON2_MMC_INT_CSENT) { 443 + if (host->state == STATE_RSPFIN || host->state == STATE_CMDSENT) 444 + goto close_transfer; 445 + 446 + if (host->state == STATE_XFERFINISH_RSPFIN) 447 + host->state = STATE_XFERFINISH; 448 + } 449 + 450 + if (!cmd->data) 451 + goto irq_out; 452 + 453 + if (imsk & (LOONGSON2_MMC_INT_RXCRC | LOONGSON2_MMC_INT_TXCRC)) { 454 + cmd->data->error = -EILSEQ; 455 + goto close_transfer; 456 + } 457 + 458 + if (imsk & LOONGSON2_MMC_INT_DTIMEOUT) { 459 + cmd->data->error = -ETIMEDOUT; 460 + goto close_transfer; 461 + } 462 + 463 + if (imsk & LOONGSON2_MMC_INT_DFIN) { 464 + if (host->state == STATE_XFERFINISH) { 465 + host->dma_complete = 1; 466 + goto close_transfer; 467 + } 468 + 469 + if (host->state == STATE_XFERFINISH_RSPFIN) 470 + host->state = STATE_RSPFIN; 471 + } 472 + 473 + irq_out: 474 + regmap_write(host->regmap, LOONGSON2_MMC_REG_INT, imsk); 475 + spin_unlock_irqrestore(&host->lock, iflags); 476 + return IRQ_HANDLED; 477 + 478 + close_transfer: 479 + host->state = STATE_FINALIZE; 480 + host->pdata->reorder_cmd_data(host, cmd); 481 + regmap_write(host->regmap, LOONGSON2_MMC_REG_INT, imsk); 482 + spin_unlock_irqrestore(&host->lock, iflags); 483 + return IRQ_WAKE_THREAD; 484 + } 485 + 486 + static void loongson2_mmc_dll_mode_init(struct loongson2_mmc_host *host) 487 + { 488 + u32 val, pad_delay, delay; 489 + int ret; 490 + 491 + regmap_update_bits(host->regmap, LOONGSON2_MMC_REG_SEL, 492 + LOONGSON2_MMC_SEL_DATA, LOONGSON2_MMC_SEL_DATA); 493 + 494 + val = FIELD_PREP(LOONGSON2_MMC_DLLCTL_TIME, 0xc8) 495 + | FIELD_PREP(LOONGSON2_MMC_DLLCTL_INCRE, 0x1) 496 + | FIELD_PREP(LOONGSON2_MMC_DLLCTL_START, 0x1) 497 + | FIELD_PREP(LOONGSON2_MMC_DLLCTL_CLK_MODE, 0x1) 498 + | FIELD_PREP(LOONGSON2_MMC_DLLCTL_START_BIT, 0x1) 499 + | FIELD_PREP(LOONGSON2_MMC_DLLCTL_TIME_BPASS, 0xf); 500 + 501 + regmap_write(host->regmap, LOONGSON2_MMC_REG_DLLCTL, val); 502 + 503 + ret = regmap_read_poll_timeout(host->regmap, LOONGSON2_MMC_REG_DLLVAL, val, 504 + (val & LOONGSON2_MMC_DLLVAL_DONE), 0, 505 + LOONGSON2_MMC_DLLVAL_TIMEOUT_US); 506 + if (ret < 0) 507 + return; 508 + 509 + regmap_read(host->regmap, LOONGSON2_MMC_REG_DLLVAL, &val); 510 + pad_delay = FIELD_GET(GENMASK(7, 1), val); 511 + 512 + delay = FIELD_PREP(LOONGSON2_MMC_DELAY_PAD, pad_delay) 513 + | FIELD_PREP(LOONGSON2_MMC_DELAY_RD, pad_delay + 1); 514 + 515 + regmap_write(host->regmap, LOONGSON2_MMC_REG_DELAY, delay); 516 + } 517 + 518 + static void loongson2_mmc_set_clk(struct loongson2_mmc_host *host, struct mmc_ios *ios) 519 + { 520 + u32 pre; 521 + 522 + pre = DIV_ROUND_UP(host->current_clk, ios->clock); 523 + if (pre > 255) 524 + pre = 255; 525 + 526 + regmap_write(host->regmap, LOONGSON2_MMC_REG_PRE, pre | LOONGSON2_MMC_PRE_EN); 527 + 528 + regmap_update_bits(host->regmap, LOONGSON2_MMC_REG_CTL, 529 + LOONGSON2_MMC_CTL_ENCLK, LOONGSON2_MMC_CTL_ENCLK); 530 + 531 + /* EMMC DLL mode setting */ 532 + if (ios->timing == MMC_TIMING_UHS_DDR50 || ios->timing == MMC_TIMING_MMC_DDR52) 533 + loongson2_mmc_dll_mode_init(host); 534 + } 535 + 536 + static void loongson2_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 537 + { 538 + struct loongson2_mmc_host *host = mmc_priv(mmc); 539 + int ret; 540 + 541 + if (ios->power_mode == MMC_POWER_UP) { 542 + if (!IS_ERR(mmc->supply.vmmc)) { 543 + ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 544 + if (ret) { 545 + dev_err(host->dev, "failed to enable vmmc regulator\n"); 546 + return; /* return, if failed turn on vmmc */ 547 + } 548 + } 549 + regmap_write(host->regmap, LOONGSON2_MMC_REG_CTL, LOONGSON2_MMC_CTL_RESET); 550 + mdelay(10); 551 + regmap_write(host->regmap, LOONGSON2_MMC_REG_CTL, LOONGSON2_MMC_CTL_EXTCLK); 552 + regmap_write(host->regmap, LOONGSON2_MMC_REG_INT, LOONGSON2_MMC_IEN_ALL); 553 + regmap_write(host->regmap, LOONGSON2_MMC_REG_IEN, LOONGSON2_MMC_INT_CLEAR); 554 + } else if (ios->power_mode == MMC_POWER_OFF) { 555 + regmap_update_bits(host->regmap, LOONGSON2_MMC_REG_CTL, 556 + LOONGSON2_MMC_CTL_RESET, LOONGSON2_MMC_CTL_RESET); 557 + if (!IS_ERR(mmc->supply.vmmc)) 558 + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 559 + return; 560 + } 561 + 562 + loongson2_mmc_set_clk(host, ios); 563 + 564 + host->bus_width = ios->bus_width; 565 + } 566 + 567 + static void loongson2_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 568 + { 569 + struct loongson2_mmc_host *host = mmc_priv(mmc); 570 + 571 + host->cmd_is_stop = 0; 572 + host->mrq = mrq; 573 + loongson2_mmc_send_request(mmc); 574 + } 575 + 576 + static void loongson2_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 577 + { 578 + struct loongson2_mmc_host *host = mmc_priv(mmc); 579 + 580 + regmap_update_bits(host->regmap, LOONGSON2_MMC_REG_IEN, LOONGSON2_MMC_INT_SDIOIRQ, enable); 581 + } 582 + 583 + static void loongson2_mmc_ack_sdio_irq(struct mmc_host *mmc) 584 + { 585 + loongson2_mmc_enable_sdio_irq(mmc, 1); 586 + } 587 + 588 + static struct mmc_host_ops loongson2_mmc_ops = { 589 + .request = loongson2_mmc_request, 590 + .set_ios = loongson2_mmc_set_ios, 591 + .get_ro = mmc_gpio_get_ro, 592 + .get_cd = mmc_gpio_get_cd, 593 + .enable_sdio_irq = loongson2_mmc_enable_sdio_irq, 594 + .ack_sdio_irq = loongson2_mmc_ack_sdio_irq, 595 + }; 596 + 597 + static const struct regmap_config ls2k0500_mmc_regmap_config = { 598 + .reg_bits = 32, 599 + .val_bits = 32, 600 + .reg_stride = 4, 601 + .max_register = LOONGSON2_MMC_REG_IEN, 602 + }; 603 + 604 + static int loongson2_reorder_cmd_list[] = { SD_APP_SEND_SCR, SD_APP_SEND_NUM_WR_BLKS, 605 + SD_APP_SD_STATUS, MMC_SEND_WRITE_PROT, SD_SWITCH }; 606 + 607 + /* 608 + * According to SD spec, ACMD13, ACMD22, ACMD51 and CMD30 609 + * response datas has different byte order with usual data packets. 610 + * However sdio controller will send these datas in usual data format, 611 + * so we need to adjust these datas to a protocol consistent byte order. 612 + */ 613 + static void ls2k0500_mmc_reorder_cmd_data(struct loongson2_mmc_host *host, 614 + struct mmc_command *cmd) 615 + { 616 + struct scatterlist *sg; 617 + u32 *data; 618 + int i, j; 619 + 620 + if (mmc_cmd_type(cmd) != MMC_CMD_ADTC) 621 + return; 622 + 623 + for (i = 0; i < ARRAY_SIZE(loongson2_reorder_cmd_list); i++) 624 + if (cmd->opcode == loongson2_reorder_cmd_list[i]) 625 + break; 626 + 627 + if (i == ARRAY_SIZE(loongson2_reorder_cmd_list)) 628 + return; 629 + 630 + for_each_sg(cmd->data->sg, sg, cmd->data->sg_len, i) { 631 + data = sg_virt(&sg[i]); 632 + for (j = 0; j < (sg_dma_len(&sg[i]) / 4); j++) 633 + if (cmd->opcode == SD_SWITCH) 634 + data[j] = bitrev8x4(data[j]); 635 + else 636 + data[j] = (__force u32)cpu_to_be32(data[j]); 637 + } 638 + } 639 + 640 + static int loongson2_mmc_prepare_external_dma(struct loongson2_mmc_host *host, 641 + struct mmc_data *data) 642 + { 643 + struct mmc_host *mmc = mmc_from_priv(host); 644 + struct dma_slave_config dma_conf = { }; 645 + struct dma_async_tx_descriptor *desc; 646 + int ret; 647 + 648 + ret = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, 649 + mmc_get_dma_dir(data)); 650 + if (!ret) 651 + return -ENOMEM; 652 + 653 + dma_conf.src_addr = host->res->start + LOONGSON2_MMC_REG_DATA, 654 + dma_conf.dst_addr = host->res->start + LOONGSON2_MMC_REG_DATA, 655 + dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 656 + dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 657 + dma_conf.direction = !(data->flags & MMC_DATA_WRITE) ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 658 + 659 + dmaengine_slave_config(host->chan, &dma_conf); 660 + desc = dmaengine_prep_slave_sg(host->chan, data->sg, data->sg_len, 661 + dma_conf.direction, 662 + DMA_CTRL_ACK | DMA_PREP_INTERRUPT); 663 + if (!desc) 664 + goto unmap_exit; 665 + 666 + dmaengine_submit(desc); 667 + dma_async_issue_pending(host->chan); 668 + 669 + return 0; 670 + 671 + unmap_exit: 672 + dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, mmc_get_dma_dir(data)); 673 + return -ENOMEM; 674 + } 675 + 676 + static void loongson2_mmc_release_external_dma(struct loongson2_mmc_host *host, 677 + struct device *dev) 678 + { 679 + dma_release_channel(host->chan); 680 + } 681 + 682 + static int ls2k0500_mmc_set_external_dma(struct loongson2_mmc_host *host, 683 + struct platform_device *pdev) 684 + { 685 + int ret, val; 686 + void __iomem *regs; 687 + 688 + regs = devm_platform_ioremap_resource(pdev, 1); 689 + if (IS_ERR(regs)) 690 + return PTR_ERR(regs); 691 + 692 + val = readl(regs); 693 + val |= FIELD_PREP(LS2K0500_SDIO_DMA_MASK, LS2K0500_DMA2_CONF); 694 + writel(val, regs); 695 + 696 + host->chan = dma_request_chan(&pdev->dev, "rx-tx"); 697 + ret = PTR_ERR_OR_ZERO(host->chan); 698 + if (ret) { 699 + dev_err(&pdev->dev, "Cannot get DMA channel.\n"); 700 + return ret; 701 + } 702 + 703 + return 0; 704 + } 705 + 706 + static struct loongson2_mmc_pdata ls2k0500_mmc_pdata = { 707 + .regmap_config = &ls2k0500_mmc_regmap_config, 708 + .reorder_cmd_data = ls2k0500_mmc_reorder_cmd_data, 709 + .setting_dma = ls2k0500_mmc_set_external_dma, 710 + .prepare_dma = loongson2_mmc_prepare_external_dma, 711 + .release_dma = loongson2_mmc_release_external_dma, 712 + }; 713 + 714 + static int ls2k1000_mmc_set_external_dma(struct loongson2_mmc_host *host, 715 + struct platform_device *pdev) 716 + { 717 + int ret, val; 718 + void __iomem *regs; 719 + 720 + regs = devm_platform_ioremap_resource(pdev, 1); 721 + if (IS_ERR(regs)) 722 + return PTR_ERR(regs); 723 + 724 + val = readl(regs); 725 + val |= FIELD_PREP(LS2K1000_SDIO_DMA_MASK, LS2K1000_DMA1_CONF); 726 + writel(val, regs); 727 + 728 + host->chan = dma_request_chan(&pdev->dev, "rx-tx"); 729 + ret = PTR_ERR_OR_ZERO(host->chan); 730 + if (ret) { 731 + dev_err(&pdev->dev, "Cannot get DMA channel.\n"); 732 + return ret; 733 + } 734 + 735 + return 0; 736 + } 737 + 738 + static struct loongson2_mmc_pdata ls2k1000_mmc_pdata = { 739 + .regmap_config = &ls2k0500_mmc_regmap_config, 740 + .reorder_cmd_data = ls2k0500_mmc_reorder_cmd_data, 741 + .setting_dma = ls2k1000_mmc_set_external_dma, 742 + .prepare_dma = loongson2_mmc_prepare_external_dma, 743 + .release_dma = loongson2_mmc_release_external_dma, 744 + }; 745 + 746 + static const struct regmap_config ls2k2000_mmc_regmap_config = { 747 + .reg_bits = 32, 748 + .val_bits = 32, 749 + .reg_stride = 4, 750 + .max_register = LOONGSON2_MMC_REG_RDMA_HI, 751 + }; 752 + 753 + static void ls2k2000_mmc_reorder_cmd_data(struct loongson2_mmc_host *host, 754 + struct mmc_command *cmd) 755 + { 756 + struct scatterlist *sg; 757 + u32 *data; 758 + int i, j; 759 + 760 + if (cmd->opcode != SD_SWITCH || mmc_cmd_type(cmd) != MMC_CMD_ADTC) 761 + return; 762 + 763 + for_each_sg(cmd->data->sg, sg, cmd->data->sg_len, i) { 764 + data = sg_virt(&sg[i]); 765 + for (j = 0; j < (sg_dma_len(&sg[i]) / 4); j++) 766 + data[j] = bitrev8x4(data[j]); 767 + } 768 + } 769 + 770 + /* 771 + * This is a controller hardware defect. Single/multiple block write commands 772 + * must be sent after the TX FULL flag is set, otherwise a data timeout interrupt 773 + * will occur. 774 + */ 775 + static void ls2k2000_mmc_fix_data_timeout(struct loongson2_mmc_host *host, 776 + struct mmc_command *cmd) 777 + { 778 + int val; 779 + 780 + if (cmd->opcode != MMC_WRITE_BLOCK && cmd->opcode != MMC_WRITE_MULTIPLE_BLOCK) 781 + return; 782 + 783 + regmap_read_poll_timeout(host->regmap, LOONGSON2_MMC_REG_FSTS, val, 784 + (val & LOONGSON2_MMC_FSTS_TXFULL), 0, 785 + LOONGSON2_MMC_TXFULL_TIMEOUT_US); 786 + } 787 + 788 + static int loongson2_mmc_prepare_internal_dma(struct loongson2_mmc_host *host, 789 + struct mmc_data *data) 790 + { 791 + struct loongson2_dma_desc *pdes = (struct loongson2_dma_desc *)host->sg_cpu; 792 + struct mmc_host *mmc = mmc_from_priv(host); 793 + dma_addr_t next_desc = host->sg_dma; 794 + struct scatterlist *sg; 795 + int reg_lo, reg_hi; 796 + u64 dma_order; 797 + int i, ret; 798 + 799 + ret = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, 800 + mmc_get_dma_dir(data)); 801 + if (!ret) 802 + return -ENOMEM; 803 + 804 + for_each_sg(data->sg, sg, data->sg_len, i) { 805 + pdes[i].len = sg_dma_len(&sg[i]) / 4; 806 + pdes[i].step_len = 0; 807 + pdes[i].step_times = 1; 808 + pdes[i].mem_addr = lower_32_bits(sg_dma_address(&sg[i])); 809 + pdes[i].high_mem_addr = upper_32_bits(sg_dma_address(&sg[i])); 810 + pdes[i].apb_addr = host->res->start + LOONGSON2_MMC_REG_DATA; 811 + pdes[i].cmd = LOONGSON2_MMC_DMA_INT; 812 + 813 + if (data->flags & MMC_DATA_READ) { 814 + reg_lo = LOONGSON2_MMC_REG_RDMA_LO; 815 + reg_hi = LOONGSON2_MMC_REG_RDMA_HI; 816 + } else { 817 + pdes[i].cmd |= LOONGSON2_MMC_DMA_DATA_DIR; 818 + reg_lo = LOONGSON2_MMC_REG_WDMA_LO; 819 + reg_hi = LOONGSON2_MMC_REG_WDMA_HI; 820 + } 821 + 822 + next_desc += sizeof(struct loongson2_dma_desc); 823 + pdes[i].ndesc_addr = lower_32_bits(next_desc) | 824 + LOONGSON2_MMC_DMA_DESC_EN; 825 + pdes[i].high_ndesc_addr = upper_32_bits(next_desc); 826 + } 827 + 828 + /* Setting the last descriptor enable bit */ 829 + pdes[i - 1].ndesc_addr &= ~LOONGSON2_MMC_DMA_DESC_EN; 830 + 831 + dma_order = (host->sg_dma & ~LOONGSON2_MMC_DMA_CONFIG_MASK) | 832 + LOONGSON2_MMC_DMA_64BIT_EN | 833 + LOONGSON2_MMC_DMA_START; 834 + 835 + regmap_write(host->regmap, reg_hi, upper_32_bits(dma_order)); 836 + regmap_write(host->regmap, reg_lo, lower_32_bits(dma_order)); 837 + 838 + return 0; 839 + } 840 + 841 + static int ls2k2000_mmc_set_internal_dma(struct loongson2_mmc_host *host, 842 + struct platform_device *pdev) 843 + { 844 + host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 845 + &host->sg_dma, GFP_KERNEL); 846 + if (!host->sg_cpu) 847 + return -ENOMEM; 848 + 849 + memset(host->sg_cpu, 0, PAGE_SIZE); 850 + return 0; 851 + } 852 + 853 + static void loongson2_mmc_release_internal_dma(struct loongson2_mmc_host *host, 854 + struct device *dev) 855 + { 856 + dma_free_coherent(dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 857 + } 858 + 859 + static struct loongson2_mmc_pdata ls2k2000_mmc_pdata = { 860 + .regmap_config = &ls2k2000_mmc_regmap_config, 861 + .reorder_cmd_data = ls2k2000_mmc_reorder_cmd_data, 862 + .fix_data_timeout = ls2k2000_mmc_fix_data_timeout, 863 + .setting_dma = ls2k2000_mmc_set_internal_dma, 864 + .prepare_dma = loongson2_mmc_prepare_internal_dma, 865 + .release_dma = loongson2_mmc_release_internal_dma, 866 + }; 867 + 868 + static int loongson2_mmc_resource_request(struct platform_device *pdev, 869 + struct loongson2_mmc_host *host) 870 + { 871 + struct device *dev = &pdev->dev; 872 + void __iomem *base; 873 + int ret, irq; 874 + 875 + base = devm_platform_get_and_ioremap_resource(pdev, 0, &host->res); 876 + if (IS_ERR(base)) 877 + return PTR_ERR(base); 878 + 879 + host->regmap = devm_regmap_init_mmio(dev, base, host->pdata->regmap_config); 880 + if (IS_ERR(host->regmap)) 881 + return PTR_ERR(host->regmap); 882 + 883 + host->clk = devm_clk_get_optional_enabled(dev, NULL); 884 + if (IS_ERR(host->clk)) 885 + return PTR_ERR(host->clk); 886 + 887 + if (host->clk) { 888 + ret = devm_clk_rate_exclusive_get(dev, host->clk); 889 + if (ret) 890 + return ret; 891 + 892 + host->current_clk = clk_get_rate(host->clk); 893 + } else { 894 + /* For ACPI, the clock is accessed via the clock-frequency attribute. */ 895 + device_property_read_u32(dev, "clock-frequency", &host->current_clk); 896 + } 897 + 898 + irq = platform_get_irq(pdev, 0); 899 + if (irq < 0) 900 + return irq; 901 + 902 + ret = devm_request_threaded_irq(dev, irq, loongson2_mmc_irq, 903 + loongson2_mmc_irq_worker, 904 + IRQF_ONESHOT, "loongson2-mmc", host); 905 + if (ret) 906 + return ret; 907 + 908 + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 909 + if (ret) 910 + return ret; 911 + 912 + return host->pdata->setting_dma(host, pdev); 913 + } 914 + 915 + static int loongson2_mmc_probe(struct platform_device *pdev) 916 + { 917 + struct device *dev = &pdev->dev; 918 + struct loongson2_mmc_host *host; 919 + struct mmc_host *mmc; 920 + int ret; 921 + 922 + mmc = devm_mmc_alloc_host(dev, sizeof(*host)); 923 + if (!mmc) 924 + return -ENOMEM; 925 + 926 + platform_set_drvdata(pdev, mmc); 927 + 928 + host = mmc_priv(mmc); 929 + host->state = STATE_NONE; 930 + spin_lock_init(&host->lock); 931 + 932 + host->pdata = device_get_match_data(dev); 933 + if (!host->pdata) 934 + return dev_err_probe(dev, -EINVAL, "Failed to get match data\n"); 935 + 936 + ret = loongson2_mmc_resource_request(pdev, host); 937 + if (ret) 938 + return dev_err_probe(dev, ret, "Failed to request resource\n"); 939 + 940 + mmc->ops = &loongson2_mmc_ops; 941 + mmc->f_min = DIV_ROUND_UP(host->current_clk, 256); 942 + mmc->f_max = host->current_clk; 943 + mmc->max_blk_count = 4095; 944 + mmc->max_blk_size = 4095; 945 + mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size; 946 + mmc->max_segs = 1; 947 + mmc->max_seg_size = mmc->max_req_size; 948 + 949 + /* Process SDIO IRQs through the sdio_irq_work. */ 950 + if (mmc->caps & MMC_CAP_SDIO_IRQ) 951 + mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 952 + 953 + ret = mmc_regulator_get_supply(mmc); 954 + if (ret || mmc->ocr_avail == 0) { 955 + dev_warn(dev, "Can't get voltage, defaulting to 3.3V\n"); 956 + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 957 + } 958 + 959 + ret = mmc_of_parse(mmc); 960 + if (ret) { 961 + dev_err(dev, "Failed to parse device node\n"); 962 + goto free_dma; 963 + } 964 + 965 + ret = mmc_add_host(mmc); 966 + if (ret) { 967 + dev_err(dev, "Failed to add mmc host\n"); 968 + goto free_dma; 969 + } 970 + 971 + return 0; 972 + 973 + free_dma: 974 + host->pdata->release_dma(host, dev); 975 + return ret; 976 + } 977 + 978 + static void loongson2_mmc_remove(struct platform_device *pdev) 979 + { 980 + struct mmc_host *mmc = platform_get_drvdata(pdev); 981 + struct loongson2_mmc_host *host = mmc_priv(mmc); 982 + 983 + mmc_remove_host(mmc); 984 + host->pdata->release_dma(host, &pdev->dev); 985 + } 986 + 987 + static const struct of_device_id loongson2_mmc_of_ids[] = { 988 + { .compatible = "loongson,ls2k0500-mmc", .data = &ls2k0500_mmc_pdata }, 989 + { .compatible = "loongson,ls2k1000-mmc", .data = &ls2k1000_mmc_pdata }, 990 + { .compatible = "loongson,ls2k2000-mmc", .data = &ls2k2000_mmc_pdata }, 991 + { }, 992 + }; 993 + MODULE_DEVICE_TABLE(of, loongson2_mmc_of_ids); 994 + 995 + static int loongson2_mmc_suspend(struct device *dev) 996 + { 997 + struct mmc_host *mmc = dev_get_drvdata(dev); 998 + struct loongson2_mmc_host *host = mmc_priv(mmc); 999 + 1000 + clk_disable_unprepare(host->clk); 1001 + 1002 + return 0; 1003 + } 1004 + 1005 + static int loongson2_mmc_resume(struct device *dev) 1006 + { 1007 + struct mmc_host *mmc = dev_get_drvdata(dev); 1008 + struct loongson2_mmc_host *host = mmc_priv(mmc); 1009 + 1010 + return clk_prepare_enable(host->clk); 1011 + } 1012 + 1013 + static DEFINE_SIMPLE_DEV_PM_OPS(loongson2_mmc_pm_ops, loongson2_mmc_suspend, loongson2_mmc_resume); 1014 + 1015 + static struct platform_driver loongson2_mmc_driver = { 1016 + .driver = { 1017 + .name = "loongson2-mmc", 1018 + .of_match_table = loongson2_mmc_of_ids, 1019 + .pm = pm_ptr(&loongson2_mmc_pm_ops), 1020 + .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1021 + }, 1022 + .probe = loongson2_mmc_probe, 1023 + .remove = loongson2_mmc_remove, 1024 + }; 1025 + 1026 + module_platform_driver(loongson2_mmc_driver); 1027 + 1028 + MODULE_DESCRIPTION("Loongson-2K SD/SDIO/eMMC Interface driver"); 1029 + MODULE_AUTHOR("Loongson Technology Corporation Limited"); 1030 + MODULE_LICENSE("GPL");

+1 -12

drivers/mmc/host/meson-mx-sdhc-mmc.c

··· 757 757 regmap_write(host->regmap, MESON_SDHC_ISTA, MESON_SDHC_ISTA_ALL_IRQS); 758 758 } 759 759 760 - static void meason_mx_mmc_free_host(void *data) 761 - { 762 - mmc_free_host(data); 763 - } 764 - 765 760 static int meson_mx_sdhc_probe(struct platform_device *pdev) 766 761 { 767 762 struct device *dev = &pdev->dev; ··· 765 770 void __iomem *base; 766 771 int ret, irq; 767 772 768 - mmc = mmc_alloc_host(sizeof(*host), dev); 773 + mmc = devm_mmc_alloc_host(dev, sizeof(*host)); 769 774 if (!mmc) 770 775 return -ENOMEM; 771 - 772 - ret = devm_add_action_or_reset(dev, meason_mx_mmc_free_host, mmc); 773 - if (ret) { 774 - dev_err(dev, "Failed to register mmc_free_host action\n"); 775 - return ret; 776 - } 777 776 778 777 host = mmc_priv(mmc); 779 778 host->mmc = mmc;

+1 -3

drivers/mmc/host/mmc_spi.c

··· 1185 1185 goto nomem; 1186 1186 memset(ones, 0xff, MMC_SPI_BLOCKSIZE); 1187 1187 1188 - mmc = mmc_alloc_host(sizeof(*host), &spi->dev); 1188 + mmc = devm_mmc_alloc_host(&spi->dev, sizeof(*host)); 1189 1189 if (!mmc) 1190 1190 goto nomem; 1191 1191 ··· 1305 1305 kfree(host->data); 1306 1306 fail_nobuf1: 1307 1307 mmc_spi_put_pdata(spi); 1308 - mmc_free_host(mmc); 1309 1308 nomem: 1310 1309 kfree(ones); 1311 1310 return status; ··· 1327 1328 1328 1329 spi->max_speed_hz = mmc->f_max; 1329 1330 mmc_spi_put_pdata(spi); 1330 - mmc_free_host(mmc); 1331 1331 } 1332 1332 1333 1333 static const struct spi_device_id mmc_spi_dev_ids[] = {

+11 -21

drivers/mmc/host/mmci.c

··· 2082 2082 spin_unlock_irqrestore(&host->lock, flags); 2083 2083 2084 2084 if (!enable) { 2085 - pm_runtime_mark_last_busy(mmc_dev(mmc)); 2086 2085 pm_runtime_put_autosuspend(mmc_dev(mmc)); 2087 2086 } 2088 2087 } ··· 2222 2223 return -ENOMEM; 2223 2224 } 2224 2225 2225 - mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 2226 + mmc = devm_mmc_alloc_host(&dev->dev, sizeof(*host)); 2226 2227 if (!mmc) 2227 2228 return -ENOMEM; 2228 2229 ··· 2233 2234 2234 2235 ret = mmci_of_parse(np, mmc); 2235 2236 if (ret) 2236 - goto host_free; 2237 + return ret; 2237 2238 2238 2239 /* 2239 2240 * Some variant (STM32) doesn't have opendrain bit, nevertheless ··· 2241 2242 */ 2242 2243 if (!variant->opendrain) { 2243 2244 host->pinctrl = devm_pinctrl_get(&dev->dev); 2244 - if (IS_ERR(host->pinctrl)) { 2245 - dev_err(&dev->dev, "failed to get pinctrl"); 2246 - ret = PTR_ERR(host->pinctrl); 2247 - goto host_free; 2248 - } 2245 + if (IS_ERR(host->pinctrl)) 2246 + return dev_err_probe(&dev->dev, PTR_ERR(host->pinctrl), 2247 + "failed to get pinctrl\n"); 2249 2248 2250 2249 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, 2251 2250 MMCI_PINCTRL_STATE_OPENDRAIN); 2252 - if (IS_ERR(host->pins_opendrain)) { 2253 - dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); 2254 - ret = PTR_ERR(host->pins_opendrain); 2255 - goto host_free; 2256 - } 2251 + if (IS_ERR(host->pins_opendrain)) 2252 + return dev_err_probe(&dev->dev, PTR_ERR(host->pins_opendrain), 2253 + "Can't select opendrain pins\n"); 2257 2254 } 2258 2255 2259 2256 host->hw_designer = amba_manf(dev); ··· 2258 2263 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 2259 2264 2260 2265 host->clk = devm_clk_get(&dev->dev, NULL); 2261 - if (IS_ERR(host->clk)) { 2262 - ret = PTR_ERR(host->clk); 2263 - goto host_free; 2264 - } 2266 + if (IS_ERR(host->clk)) 2267 + return PTR_ERR(host->clk); 2265 2268 2266 2269 ret = clk_prepare_enable(host->clk); 2267 2270 if (ret) 2268 - goto host_free; 2271 + return ret; 2269 2272 2270 2273 if (variant->qcom_fifo) 2271 2274 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; ··· 2484 2491 2485 2492 clk_disable: 2486 2493 clk_disable_unprepare(host->clk); 2487 - host_free: 2488 - mmc_free_host(mmc); 2489 2494 return ret; 2490 2495 } 2491 2496 ··· 2513 2522 2514 2523 mmci_dma_release(host); 2515 2524 clk_disable_unprepare(host->clk); 2516 - mmc_free_host(mmc); 2517 2525 } 2518 2526 } 2519 2527

+14 -26

drivers/mmc/host/moxart-mmc.c

··· 558 558 int irq, ret; 559 559 u32 i; 560 560 561 - mmc = mmc_alloc_host(sizeof(struct moxart_host), dev); 561 + mmc = devm_mmc_alloc_host(dev, sizeof(*host)); 562 562 if (!mmc) { 563 - dev_err(dev, "mmc_alloc_host failed\n"); 564 - ret = -ENOMEM; 565 - goto out_mmc; 563 + dev_err(dev, "devm_mmc_alloc_host failed\n"); 564 + return -ENOMEM; 566 565 } 567 566 568 567 ret = of_address_to_resource(node, 0, &res_mmc); 569 - if (ret) { 570 - dev_err(dev, "of_address_to_resource failed\n"); 571 - goto out_mmc; 572 - } 568 + if (ret) 569 + return dev_err_probe(dev, ret, 570 + "of_address_to_resource failed\n"); 573 571 574 572 irq = irq_of_parse_and_map(node, 0); 575 - if (irq <= 0) { 576 - dev_err(dev, "irq_of_parse_and_map failed\n"); 577 - ret = -EINVAL; 578 - goto out_mmc; 579 - } 573 + if (irq <= 0) 574 + return dev_err_probe(dev, -EINVAL, 575 + "irq_of_parse_and_map failed\n"); 580 576 581 577 clk = devm_clk_get(dev, NULL); 582 - if (IS_ERR(clk)) { 583 - ret = PTR_ERR(clk); 584 - goto out_mmc; 585 - } 578 + if (IS_ERR(clk)) 579 + return PTR_ERR(clk); 586 580 587 581 reg_mmc = devm_ioremap_resource(dev, &res_mmc); 588 - if (IS_ERR(reg_mmc)) { 589 - ret = PTR_ERR(reg_mmc); 590 - goto out_mmc; 591 - } 582 + if (IS_ERR(reg_mmc)) 583 + return PTR_ERR(reg_mmc); 592 584 593 585 ret = mmc_of_parse(mmc); 594 586 if (ret) 595 - goto out_mmc; 587 + return ret; 596 588 597 589 host = mmc_priv(mmc); 598 590 host->mmc = mmc; ··· 678 686 dma_release_channel(host->dma_chan_tx); 679 687 if (!IS_ERR_OR_NULL(host->dma_chan_rx)) 680 688 dma_release_channel(host->dma_chan_rx); 681 - out_mmc: 682 - if (mmc) 683 - mmc_free_host(mmc); 684 689 return ret; 685 690 } 686 691 ··· 696 707 writel(0, host->base + REG_POWER_CONTROL); 697 708 writel(readl(host->base + REG_CLOCK_CONTROL) | CLK_OFF, 698 709 host->base + REG_CLOCK_CONTROL); 699 - mmc_free_host(mmc); 700 710 } 701 711 702 712 static const struct of_device_id moxart_mmc_match[] = {

+7 -17

drivers/mmc/host/mvsdio.c

··· 706 706 if (irq < 0) 707 707 return irq; 708 708 709 - mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev); 710 - if (!mmc) { 711 - ret = -ENOMEM; 712 - goto out; 713 - } 709 + mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(*host)); 710 + if (!mmc) 711 + return -ENOMEM; 714 712 715 713 host = mmc_priv(mmc); 716 714 host->mmc = mmc; ··· 722 724 * fixed rate clock). 723 725 */ 724 726 host->clk = devm_clk_get(&pdev->dev, NULL); 725 - if (IS_ERR(host->clk)) { 726 - dev_err(&pdev->dev, "no clock associated\n"); 727 - ret = -EINVAL; 728 - goto out; 729 - } 727 + if (IS_ERR(host->clk)) 728 + return dev_err_probe(&pdev->dev, -EINVAL, "no clock associated\n"); 729 + 730 730 clk_prepare_enable(host->clk); 731 731 732 732 mmc->ops = &mvsd_ops; ··· 783 787 return 0; 784 788 785 789 out: 786 - if (mmc) { 787 - if (!IS_ERR(host->clk)) 788 - clk_disable_unprepare(host->clk); 789 - mmc_free_host(mmc); 790 - } 791 - 790 + clk_disable_unprepare(host->clk); 792 791 return ret; 793 792 } 794 793 ··· 799 808 800 809 if (!IS_ERR(host->clk)) 801 810 clk_disable_unprepare(host->clk); 802 - mmc_free_host(mmc); 803 811 } 804 812 805 813 static const struct of_device_id mvsdio_dt_ids[] = {

+10 -21

drivers/mmc/host/mxcmmc.c

··· 1005 1005 if (irq < 0) 1006 1006 return irq; 1007 1007 1008 - mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1008 + mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(*host)); 1009 1009 if (!mmc) 1010 1010 return -ENOMEM; 1011 1011 1012 1012 host = mmc_priv(mmc); 1013 1013 1014 1014 host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1015 - if (IS_ERR(host->base)) { 1016 - ret = PTR_ERR(host->base); 1017 - goto out_free; 1018 - } 1015 + if (IS_ERR(host->base)) 1016 + return PTR_ERR(host->base); 1019 1017 1020 1018 host->phys_base = res->start; 1021 1019 1022 1020 ret = mmc_of_parse(mmc); 1023 1021 if (ret) 1024 - goto out_free; 1022 + return ret; 1025 1023 mmc->ops = &mxcmci_ops; 1026 1024 1027 1025 /* For devicetree parsing, the bus width is read from devicetree */ ··· 1052 1054 1053 1055 ret = mmc_regulator_get_supply(mmc); 1054 1056 if (ret) 1055 - goto out_free; 1057 + return ret; 1056 1058 1057 1059 if (!mmc->ocr_avail) { 1058 1060 if (pdata && pdata->ocr_avail) ··· 1068 1070 host->default_irq_mask = 0; 1069 1071 1070 1072 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1071 - if (IS_ERR(host->clk_ipg)) { 1072 - ret = PTR_ERR(host->clk_ipg); 1073 - goto out_free; 1074 - } 1073 + if (IS_ERR(host->clk_ipg)) 1074 + return PTR_ERR(host->clk_ipg); 1075 1075 1076 1076 host->clk_per = devm_clk_get(&pdev->dev, "per"); 1077 - if (IS_ERR(host->clk_per)) { 1078 - ret = PTR_ERR(host->clk_per); 1079 - goto out_free; 1080 - } 1077 + if (IS_ERR(host->clk_per)) 1078 + return PTR_ERR(host->clk_per); 1081 1079 1082 1080 ret = clk_prepare_enable(host->clk_per); 1083 1081 if (ret) 1084 - goto out_free; 1082 + return ret; 1085 1083 1086 1084 ret = clk_prepare_enable(host->clk_ipg); 1087 1085 if (ret) ··· 1163 1169 out_clk_per_put: 1164 1170 clk_disable_unprepare(host->clk_per); 1165 1171 1166 - out_free: 1167 - mmc_free_host(mmc); 1168 - 1169 1172 return ret; 1170 1173 } 1171 1174 ··· 1181 1190 1182 1191 clk_disable_unprepare(host->clk_per); 1183 1192 clk_disable_unprepare(host->clk_ipg); 1184 - 1185 - mmc_free_host(mmc); 1186 1193 } 1187 1194 1188 1195 static int mxcmci_suspend(struct device *dev)

+11 -20

drivers/mmc/host/mxs-mmc.c

··· 569 569 if (irq_err < 0) 570 570 return irq_err; 571 571 572 - mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev); 572 + mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(*host)); 573 573 if (!mmc) 574 574 return -ENOMEM; 575 575 ··· 577 577 ssp = &host->ssp; 578 578 ssp->dev = &pdev->dev; 579 579 ssp->base = devm_platform_ioremap_resource(pdev, 0); 580 - if (IS_ERR(ssp->base)) { 581 - ret = PTR_ERR(ssp->base); 582 - goto out_mmc_free; 583 - } 580 + if (IS_ERR(ssp->base)) 581 + return PTR_ERR(ssp->base); 584 582 585 583 ssp->devid = (enum mxs_ssp_id)of_device_get_match_data(&pdev->dev); 586 584 ··· 588 590 reg_vmmc = devm_regulator_get(&pdev->dev, "vmmc"); 589 591 if (!IS_ERR(reg_vmmc)) { 590 592 ret = regulator_enable(reg_vmmc); 591 - if (ret) { 592 - dev_err(&pdev->dev, 593 - "Failed to enable vmmc regulator: %d\n", ret); 594 - goto out_mmc_free; 595 - } 593 + if (ret) 594 + return dev_err_probe(&pdev->dev, ret, 595 + "Failed to enable vmmc regulator\n"); 596 596 597 597 ret = devm_add_action_or_reset(&pdev->dev, mxs_mmc_regulator_disable, 598 598 reg_vmmc); 599 599 if (ret) 600 - goto out_mmc_free; 600 + return ret; 601 601 } 602 602 603 603 ssp->clk = devm_clk_get(&pdev->dev, NULL); 604 - if (IS_ERR(ssp->clk)) { 605 - ret = PTR_ERR(ssp->clk); 606 - goto out_mmc_free; 607 - } 604 + if (IS_ERR(ssp->clk)) 605 + return PTR_ERR(ssp->clk); 606 + 608 607 ret = clk_prepare_enable(ssp->clk); 609 608 if (ret) 610 - goto out_mmc_free; 609 + return ret; 611 610 612 611 ret = mxs_mmc_reset(host); 613 612 if (ret) { ··· 663 668 dma_release_channel(ssp->dmach); 664 669 out_clk_disable: 665 670 clk_disable_unprepare(ssp->clk); 666 - out_mmc_free: 667 - mmc_free_host(mmc); 668 671 return ret; 669 672 } 670 673 ··· 678 685 dma_release_channel(ssp->dmach); 679 686 680 687 clk_disable_unprepare(ssp->clk); 681 - 682 - mmc_free_host(mmc); 683 688 } 684 689 685 690 #ifdef CONFIG_PM_SLEEP

+9 -16

drivers/mmc/host/omap.c

··· 1259 1259 struct mmc_host *mmc; 1260 1260 int r; 1261 1261 1262 - mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev); 1262 + mmc = devm_mmc_alloc_host(host->dev, sizeof(*slot)); 1263 1263 if (mmc == NULL) 1264 1264 return -ENOMEM; 1265 1265 ··· 1273 1273 /* Check for some optional GPIO controls */ 1274 1274 slot->vsd = devm_gpiod_get_index_optional(host->dev, "vsd", 1275 1275 id, GPIOD_OUT_LOW); 1276 - if (IS_ERR(slot->vsd)) { 1277 - r = dev_err_probe(host->dev, PTR_ERR(slot->vsd), 1276 + if (IS_ERR(slot->vsd)) 1277 + return dev_err_probe(host->dev, PTR_ERR(slot->vsd), 1278 1278 "error looking up VSD GPIO\n"); 1279 - goto err_free_host; 1280 - } 1279 + 1281 1280 slot->vio = devm_gpiod_get_index_optional(host->dev, "vio", 1282 1281 id, GPIOD_OUT_LOW); 1283 - if (IS_ERR(slot->vio)) { 1284 - r = dev_err_probe(host->dev, PTR_ERR(slot->vio), 1282 + if (IS_ERR(slot->vio)) 1283 + return dev_err_probe(host->dev, PTR_ERR(slot->vio), 1285 1284 "error looking up VIO GPIO\n"); 1286 - goto err_free_host; 1287 - } 1285 + 1288 1286 slot->cover = devm_gpiod_get_index_optional(host->dev, "cover", 1289 1287 id, GPIOD_IN); 1290 - if (IS_ERR(slot->cover)) { 1291 - r = dev_err_probe(host->dev, PTR_ERR(slot->cover), 1288 + if (IS_ERR(slot->cover)) 1289 + return dev_err_probe(host->dev, PTR_ERR(slot->cover), 1292 1290 "error looking up cover switch GPIO\n"); 1293 - goto err_free_host; 1294 - } 1295 1291 1296 1292 host->slots[id] = slot; 1297 1293 ··· 1347 1351 device_remove_file(&mmc->class_dev, &dev_attr_slot_name); 1348 1352 err_remove_host: 1349 1353 mmc_remove_host(mmc); 1350 - err_free_host: 1351 - mmc_free_host(mmc); 1352 1354 return r; 1353 1355 } 1354 1356 ··· 1364 1370 flush_workqueue(slot->host->mmc_omap_wq); 1365 1371 1366 1372 mmc_remove_host(mmc); 1367 - mmc_free_host(mmc); 1368 1373 } 1369 1374 1370 1375 static int mmc_omap_probe(struct platform_device *pdev)

+5 -15

drivers/mmc/host/omap_hsmmc.c

··· 1663 1663 seq_printf(s, "CAPA:\t\t0x%08x\n", 1664 1664 OMAP_HSMMC_READ(host->base, CAPA)); 1665 1665 1666 - pm_runtime_mark_last_busy(host->dev); 1667 1666 pm_runtime_put_autosuspend(host->dev); 1668 1667 1669 1668 return 0; ··· 1797 1798 if (IS_ERR(base)) 1798 1799 return PTR_ERR(base); 1799 1800 1800 - mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1801 - if (!mmc) { 1802 - ret = -ENOMEM; 1803 - goto err; 1804 - } 1801 + mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(*host)); 1802 + if (!mmc) 1803 + return -ENOMEM; 1805 1804 1806 1805 ret = mmc_of_parse(mmc); 1807 1806 if (ret) 1808 - goto err1; 1807 + return ret; 1809 1808 1810 1809 host = mmc_priv(mmc); 1811 1810 host->mmc = mmc; ··· 1839 1842 if (IS_ERR(host->fclk)) { 1840 1843 ret = PTR_ERR(host->fclk); 1841 1844 host->fclk = NULL; 1842 - goto err1; 1845 + return ret; 1843 1846 } 1844 1847 1845 1848 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { ··· 1953 1956 } 1954 1957 1955 1958 omap_hsmmc_debugfs(mmc); 1956 - pm_runtime_mark_last_busy(host->dev); 1957 1959 pm_runtime_put_autosuspend(host->dev); 1958 1960 1959 1961 return 0; ··· 1969 1973 pm_runtime_put_sync(host->dev); 1970 1974 pm_runtime_disable(host->dev); 1971 1975 clk_disable_unprepare(host->dbclk); 1972 - err1: 1973 - mmc_free_host(mmc); 1974 - err: 1975 1976 return ret; 1976 1977 } 1977 1978 ··· 1988 1995 pm_runtime_disable(host->dev); 1989 1996 device_init_wakeup(&pdev->dev, false); 1990 1997 clk_disable_unprepare(host->dbclk); 1991 - 1992 - mmc_free_host(host->mmc); 1993 1998 } 1994 1999 1995 2000 #ifdef CONFIG_PM_SLEEP ··· 2029 2038 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 2030 2039 omap_hsmmc_conf_bus_power(host); 2031 2040 2032 - pm_runtime_mark_last_busy(host->dev); 2033 2041 pm_runtime_put_autosuspend(host->dev); 2034 2042 return 0; 2035 2043 }

+13 -24

drivers/mmc/host/owl-mmc.c

··· 567 567 struct resource *res; 568 568 int ret; 569 569 570 - mmc = mmc_alloc_host(sizeof(struct owl_mmc_host), &pdev->dev); 570 + mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(*owl_host)); 571 571 if (!mmc) { 572 572 dev_err(&pdev->dev, "mmc alloc host failed\n"); 573 573 return -ENOMEM; ··· 580 580 spin_lock_init(&owl_host->lock); 581 581 582 582 owl_host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 583 - if (IS_ERR(owl_host->base)) { 584 - ret = PTR_ERR(owl_host->base); 585 - goto err_free_host; 586 - } 583 + if (IS_ERR(owl_host->base)) 584 + return PTR_ERR(owl_host->base); 587 585 588 586 owl_host->clk = devm_clk_get(&pdev->dev, NULL); 589 - if (IS_ERR(owl_host->clk)) { 590 - dev_err(&pdev->dev, "No clock defined\n"); 591 - ret = PTR_ERR(owl_host->clk); 592 - goto err_free_host; 593 - } 587 + if (IS_ERR(owl_host->clk)) 588 + return dev_err_probe(&pdev->dev, PTR_ERR(owl_host->clk), 589 + "No clock defined\n"); 594 590 595 591 owl_host->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); 596 - if (IS_ERR(owl_host->reset)) { 597 - dev_err(&pdev->dev, "Could not get reset control\n"); 598 - ret = PTR_ERR(owl_host->reset); 599 - goto err_free_host; 600 - } 592 + if (IS_ERR(owl_host->reset)) 593 + return dev_err_probe(&pdev->dev, PTR_ERR(owl_host->reset), 594 + "Could not get reset control\n"); 601 595 602 596 mmc->ops = &owl_mmc_ops; 603 597 mmc->max_blk_count = 512; ··· 610 616 611 617 ret = mmc_of_parse(mmc); 612 618 if (ret) 613 - goto err_free_host; 619 + return ret; 614 620 615 621 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); 616 622 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; 617 623 owl_host->dma = dma_request_chan(&pdev->dev, "mmc"); 618 - if (IS_ERR(owl_host->dma)) { 619 - dev_err(owl_host->dev, "Failed to get external DMA channel.\n"); 620 - ret = PTR_ERR(owl_host->dma); 621 - goto err_free_host; 622 - } 624 + if (IS_ERR(owl_host->dma)) 625 + return dev_err_probe(&pdev->dev, PTR_ERR(owl_host->dma), 626 + "Failed to get external DMA channel.\n"); 623 627 624 628 dev_info(&pdev->dev, "Using %s for DMA transfers\n", 625 629 dma_chan_name(owl_host->dma)); ··· 654 662 655 663 err_release_channel: 656 664 dma_release_channel(owl_host->dma); 657 - err_free_host: 658 - mmc_free_host(mmc); 659 665 660 666 return ret; 661 667 } ··· 666 676 mmc_remove_host(mmc); 667 677 disable_irq(owl_host->irq); 668 678 dma_release_channel(owl_host->dma); 669 - mmc_free_host(mmc); 670 679 } 671 680 672 681 static const struct of_device_id owl_mmc_of_match[] = {

+15 -27

drivers/mmc/host/pxamci.c

··· 615 615 if (irq < 0) 616 616 return irq; 617 617 618 - mmc = mmc_alloc_host(sizeof(struct pxamci_host), dev); 619 - if (!mmc) { 620 - ret = -ENOMEM; 621 - goto out; 622 - } 618 + mmc = devm_mmc_alloc_host(dev, sizeof(*host)); 619 + if (!mmc) 620 + return -ENOMEM; 623 621 624 622 mmc->ops = &pxamci_ops; 625 623 ··· 644 646 645 647 ret = pxamci_of_init(pdev, mmc); 646 648 if (ret) 647 - goto out; 649 + return ret; 648 650 649 651 host = mmc_priv(mmc); 650 652 host->mmc = mmc; ··· 653 655 654 656 host->clk = devm_clk_get(dev, NULL); 655 657 if (IS_ERR(host->clk)) { 656 - ret = PTR_ERR(host->clk); 657 658 host->clk = NULL; 658 - goto out; 659 + return PTR_ERR(host->clk); 659 660 } 660 661 661 662 host->clkrate = clk_get_rate(host->clk); ··· 667 670 668 671 ret = pxamci_init_ocr(host); 669 672 if (ret < 0) 670 - goto out; 673 + return ret; 671 674 672 675 mmc->caps = 0; 673 676 host->cmdat = 0; ··· 683 686 host->imask = MMC_I_MASK_ALL; 684 687 685 688 host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r); 686 - if (IS_ERR(host->base)) { 687 - ret = PTR_ERR(host->base); 688 - goto out; 689 - } 689 + if (IS_ERR(host->base)) 690 + return PTR_ERR(host->base); 690 691 host->res = r; 691 692 692 693 /* ··· 699 704 ret = devm_request_irq(dev, irq, pxamci_irq, 0, 700 705 DRIVER_NAME, host); 701 706 if (ret) 702 - goto out; 707 + return ret; 703 708 704 709 platform_set_drvdata(pdev, mmc); 705 710 706 711 host->dma_chan_rx = dma_request_chan(dev, "rx"); 707 712 if (IS_ERR(host->dma_chan_rx)) { 708 - dev_err(dev, "unable to request rx dma channel\n"); 709 - ret = PTR_ERR(host->dma_chan_rx); 710 713 host->dma_chan_rx = NULL; 711 - goto out; 714 + return dev_err_probe(dev, PTR_ERR(host->dma_chan_rx), 715 + "unable to request rx dma channel\n"); 712 716 } 713 717 714 718 host->dma_chan_tx = dma_request_chan(dev, "tx"); ··· 765 771 return 0; 766 772 767 773 out: 768 - if (host) { 769 - if (host->dma_chan_rx) 770 - dma_release_channel(host->dma_chan_rx); 771 - if (host->dma_chan_tx) 772 - dma_release_channel(host->dma_chan_tx); 773 - } 774 - if (mmc) 775 - mmc_free_host(mmc); 774 + if (host->dma_chan_rx) 775 + dma_release_channel(host->dma_chan_rx); 776 + if (host->dma_chan_tx) 777 + dma_release_channel(host->dma_chan_tx); 776 778 return ret; 777 779 } 778 780 ··· 793 803 dmaengine_terminate_all(host->dma_chan_tx); 794 804 dma_release_channel(host->dma_chan_rx); 795 805 dma_release_channel(host->dma_chan_tx); 796 - 797 - mmc_free_host(mmc); 798 806 } 799 807 } 800 808

+1

drivers/mmc/host/renesas_sdhi.h

··· 85 85 u32 scc_tappos_hs400; 86 86 const u8 *adjust_hs400_calib_table; 87 87 bool needs_adjust_hs400; 88 + bool card_is_sdio; 88 89 89 90 /* Tuning values: 1 for success, 0 for failure */ 90 91 DECLARE_BITMAP(taps, BITS_PER_LONG);

+42 -12

drivers/mmc/host/renesas_sdhi_core.c

··· 686 686 /* Set SCC */ 687 687 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set); 688 688 689 - /* Enable auto re-tuning */ 690 689 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 691 - SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 690 + (priv->card_is_sdio ? 0 : SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) | 692 691 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 693 692 694 693 return 0; ··· 777 778 if (bad_taps & BIT(new_tap % priv->tap_num)) 778 779 return test_bit(error_tap % priv->tap_num, priv->smpcmp); 779 780 } else { 781 + if (!priv->card_is_sdio && 782 + !(val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)) { 783 + u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP); 784 + 785 + /* DAT1 is unmatched because of an SDIO irq */ 786 + if (smpcmp & (BIT(17) | BIT(1))) 787 + return false; 788 + } 780 789 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) 781 790 return true; /* need retune */ 782 791 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP) ··· 835 828 if (mmc_doing_tune(host->mmc)) 836 829 return false; 837 830 838 - if (((mrq->cmd->error == -ETIMEDOUT) || 839 - (mrq->data && mrq->data->error == -ETIMEDOUT)) && 840 - ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 841 - (host->ops.get_cd && host->ops.get_cd(host->mmc)))) 842 - ret |= true; 831 + /* mrq can be NULL to check SCC error on SDIO irq without any request */ 832 + if (mrq) { 833 + if (((mrq->cmd->error == -ETIMEDOUT) || 834 + (mrq->data && mrq->data->error == -ETIMEDOUT)) && 835 + ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 836 + (host->ops.get_cd && host->ops.get_cd(host->mmc)))) 837 + ret |= true; 838 + } 843 839 844 840 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 845 841 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) ··· 851 841 ret |= renesas_sdhi_manual_correction(host, use_4tap); 852 842 853 843 return ret; 844 + } 845 + 846 + static void renesas_sdhi_init_card(struct mmc_host *mmc, struct mmc_card *card) 847 + { 848 + struct tmio_mmc_host *host = mmc_priv(mmc); 849 + struct renesas_sdhi *priv = host_to_priv(host); 850 + 851 + /* 852 + * This controller cannot do auto-retune with SDIO irqs, so we 853 + * then need to enforce manual correction. However, when tuning, 854 + * mmc->card is not populated yet, so we don't know if the card 855 + * is SDIO. init_card provides this information earlier, so we 856 + * keep a copy of it. 857 + */ 858 + priv->card_is_sdio = mmc_card_sdio(card); 859 + } 860 + 861 + static void renesas_sdhi_sdio_irq(struct tmio_mmc_host *host) 862 + { 863 + /* This controller requires retune when an SDIO irq occurs */ 864 + if (renesas_sdhi_check_scc_error(host, NULL)) 865 + mmc_retune_needed(host->mmc); 854 866 } 855 867 856 868 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) ··· 1196 1164 1197 1165 ret = renesas_sdhi_clk_enable(host); 1198 1166 if (ret) 1199 - goto efree; 1167 + return ret; 1200 1168 1201 1169 rcfg.of_node = of_get_available_child_by_name(dev->of_node, "vqmmc-regulator"); 1202 1170 if (rcfg.of_node) { ··· 1259 1227 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); 1260 1228 1261 1229 host->check_retune = renesas_sdhi_check_scc_error; 1230 + host->sdio_irq = renesas_sdhi_sdio_irq; 1231 + host->ops.init_card = renesas_sdhi_init_card; 1262 1232 host->ops.execute_tuning = renesas_sdhi_execute_tuning; 1263 1233 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning; 1264 1234 host->ops.hs400_downgrade = renesas_sdhi_disable_scc; ··· 1300 1266 1301 1267 edisclk: 1302 1268 renesas_sdhi_clk_disable(host); 1303 - efree: 1304 - tmio_mmc_host_free(host); 1305 - 1306 1269 return ret; 1307 1270 } 1308 1271 EXPORT_SYMBOL_GPL(renesas_sdhi_probe); ··· 1310 1279 1311 1280 tmio_mmc_host_remove(host); 1312 1281 renesas_sdhi_clk_disable(host); 1313 - tmio_mmc_host_free(host); 1314 1282 } 1315 1283 EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 1316 1284

+1 -4

drivers/mmc/host/rtsx_pci_sdmmc.c

··· 1498 1498 1499 1499 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n"); 1500 1500 1501 - mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1501 + mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(*host)); 1502 1502 if (!mmc) 1503 1503 return -ENOMEM; 1504 1504 ··· 1529 1529 if (ret) { 1530 1530 pm_runtime_dont_use_autosuspend(&pdev->dev); 1531 1531 pm_runtime_disable(&pdev->dev); 1532 - mmc_free_host(mmc); 1533 1532 return ret; 1534 1533 } 1535 1534 ··· 1570 1571 1571 1572 pm_runtime_dont_use_autosuspend(&pdev->dev); 1572 1573 pm_runtime_disable(&pdev->dev); 1573 - 1574 - mmc_free_host(mmc); 1575 1574 1576 1575 dev_dbg(&(pdev->dev), 1577 1576 ": Realtek PCI-E SDMMC controller has been removed\n");

+28 -14

drivers/mmc/host/rtsx_usb_sdmmc.c

··· 1010 1010 return sd_pull_ctl_disable_qfn24(ucr); 1011 1011 } 1012 1012 1013 - static int sd_set_power_mode(struct rtsx_usb_sdmmc *host, 1013 + static void sd_set_power_mode(struct rtsx_usb_sdmmc *host, 1014 1014 unsigned char power_mode) 1015 1015 { 1016 1016 int err; 1017 - 1018 - if (power_mode != MMC_POWER_OFF) 1019 - power_mode = MMC_POWER_ON; 1017 + struct rtsx_ucr *ucr = host->ucr; 1020 1018 1021 1019 if (power_mode == host->power_mode) 1022 - return 0; 1020 + return; 1023 1021 1024 - if (power_mode == MMC_POWER_OFF) { 1022 + switch (power_mode) { 1023 + case MMC_POWER_OFF: 1025 1024 err = sd_power_off(host); 1025 + if (err) 1026 + dev_dbg(sdmmc_dev(host), "power-off (err = %d)\n", err); 1026 1027 pm_runtime_put_noidle(sdmmc_dev(host)); 1027 - } else { 1028 + break; 1029 + 1030 + case MMC_POWER_UP: 1028 1031 pm_runtime_get_noresume(sdmmc_dev(host)); 1029 1032 err = sd_power_on(host); 1033 + if (err) 1034 + dev_dbg(sdmmc_dev(host), "power-on (err = %d)\n", err); 1035 + /* issue the clock signals to card at least 74 clocks */ 1036 + rtsx_usb_write_register(ucr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN); 1037 + break; 1038 + 1039 + case MMC_POWER_ON: 1040 + /* stop to send the clock signals */ 1041 + rtsx_usb_write_register(ucr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0x00); 1042 + break; 1043 + 1044 + case MMC_POWER_UNDEFINED: 1045 + break; 1046 + 1047 + default: 1048 + break; 1030 1049 } 1031 1050 1032 - if (!err) 1033 - host->power_mode = power_mode; 1034 - 1035 - return err; 1051 + host->power_mode = power_mode; 1036 1052 } 1037 1053 1038 1054 static int sd_set_timing(struct rtsx_usb_sdmmc *host, ··· 1350 1334 1351 1335 dev_dbg(&(pdev->dev), ": Realtek USB SD/MMC controller found\n"); 1352 1336 1353 - mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1337 + mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(*host)); 1354 1338 if (!mmc) 1355 1339 return -ENOMEM; 1356 1340 ··· 1384 1368 #ifdef RTSX_USB_USE_LEDS_CLASS 1385 1369 led_classdev_unregister(&host->led); 1386 1370 #endif 1387 - mmc_free_host(mmc); 1388 1371 pm_runtime_disable(&pdev->dev); 1389 1372 return ret; 1390 1373 } ··· 1421 1406 led_classdev_unregister(&host->led); 1422 1407 #endif 1423 1408 1424 - mmc_free_host(mmc); 1425 1409 pm_runtime_disable(&pdev->dev); 1426 1410 platform_set_drvdata(pdev, NULL); 1427 1411

+3 -8

drivers/mmc/host/sdhci-acpi.c

··· 948 948 if (c->slot && c->slot->free_slot) 949 949 c->slot->free_slot(pdev); 950 950 951 - sdhci_free_host(c->host); 952 951 return err; 953 952 } 954 953 ··· 971 972 972 973 if (c->slot && c->slot->free_slot) 973 974 c->slot->free_slot(pdev); 974 - 975 - sdhci_free_host(c->host); 976 975 } 977 976 978 977 static void __maybe_unused sdhci_acpi_reset_signal_voltage_if_needed( ··· 1025 1028 { 1026 1029 struct sdhci_acpi_host *c = dev_get_drvdata(dev); 1027 1030 struct sdhci_host *host = c->host; 1028 - int ret; 1029 1031 1030 1032 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1031 1033 mmc_retune_needed(host->mmc); 1032 1034 1033 - ret = sdhci_runtime_suspend_host(host); 1034 - if (ret) 1035 - return ret; 1035 + sdhci_runtime_suspend_host(host); 1036 1036 1037 1037 sdhci_acpi_reset_signal_voltage_if_needed(dev); 1038 1038 return 0; ··· 1041 1047 1042 1048 sdhci_acpi_byt_setting(&c->pdev->dev); 1043 1049 1044 - return sdhci_runtime_resume_host(c->host, 0); 1050 + sdhci_runtime_resume_host(c->host, 0); 1051 + return 0; 1045 1052 } 1046 1053 1047 1054 #endif

-2

drivers/mmc/host/sdhci-bcm-kona.c

··· 304 304 clk_disable_unprepare(pltfm_priv->clk); 305 305 306 306 err_pltfm_free: 307 - sdhci_pltfm_free(pdev); 308 - 309 307 dev_err(dev, "Probing of sdhci-pltfm failed: %d\n", ret); 310 308 return ret; 311 309 }

-1

drivers/mmc/host/sdhci-brcmstb.c

··· 485 485 return res; 486 486 487 487 err: 488 - sdhci_pltfm_free(pdev); 489 488 clk_disable_unprepare(base_clk); 490 489 return res; 491 490 }

+18 -16

drivers/mmc/host/sdhci-cadence.c

··· 144 144 int i; 145 145 146 146 for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) 147 - if (of_property_read_bool(np, sdhci_cdns_phy_cfgs[i].property)) 147 + if (of_property_present(np, sdhci_cdns_phy_cfgs[i].property)) 148 148 count++; 149 149 150 150 return count; ··· 433 433 }, 434 434 }; 435 435 436 + static const struct sdhci_cdns_drv_data sdhci_eyeq_drv_data = { 437 + .pltfm_data = { 438 + .ops = &sdhci_cdns_ops, 439 + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 440 + }, 441 + }; 442 + 436 443 static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = { 437 444 .pltfm_data = { 438 445 .ops = &sdhci_cdns_ops, ··· 522 515 if (data->init) { 523 516 ret = data->init(pdev); 524 517 if (ret) 525 - goto free; 518 + return ret; 526 519 } 527 520 sdhci_enable_v4_mode(host); 528 521 __sdhci_read_caps(host, &version, NULL, NULL); ··· 531 524 532 525 ret = mmc_of_parse(host->mmc); 533 526 if (ret) 534 - goto free; 527 + return ret; 535 528 536 529 sdhci_cdns_phy_param_parse(dev->of_node, priv); 537 530 538 531 ret = sdhci_cdns_phy_init(priv); 539 532 if (ret) 540 - goto free; 533 + return ret; 541 534 542 535 if (host->mmc->caps & MMC_CAP_HW_RESET) { 543 536 priv->rst_hw = devm_reset_control_get_optional_exclusive(dev, NULL); 544 - if (IS_ERR(priv->rst_hw)) { 545 - ret = dev_err_probe(mmc_dev(host->mmc), PTR_ERR(priv->rst_hw), 537 + if (IS_ERR(priv->rst_hw)) 538 + return dev_err_probe(mmc_dev(host->mmc), PTR_ERR(priv->rst_hw), 546 539 "reset controller error\n"); 547 - goto free; 548 - } 549 540 if (priv->rst_hw) 550 541 host->mmc_host_ops.card_hw_reset = sdhci_cdns_mmc_hw_reset; 551 542 } 552 543 553 - ret = sdhci_add_host(host); 554 - if (ret) 555 - goto free; 556 - 557 - return 0; 558 - free: 559 - sdhci_pltfm_free(pdev); 560 - return ret; 544 + return sdhci_add_host(host); 561 545 } 562 546 563 547 #ifdef CONFIG_PM_SLEEP ··· 592 594 { 593 595 .compatible = "amd,pensando-elba-sd4hc", 594 596 .data = &sdhci_elba_drv_data, 597 + }, 598 + { 599 + .compatible = "mobileye,eyeq-sd4hc", 600 + .data = &sdhci_eyeq_drv_data, 595 601 }, 596 602 { .compatible = "cdns,sd4hc" }, 597 603 { /* sentinel */ }

+2 -10

drivers/mmc/host/sdhci-dove.c

··· 79 79 80 80 ret = mmc_of_parse(host->mmc); 81 81 if (ret) 82 - goto err_sdhci_add; 82 + return ret; 83 83 84 - ret = sdhci_add_host(host); 85 - if (ret) 86 - goto err_sdhci_add; 87 - 88 - return 0; 89 - 90 - err_sdhci_add: 91 - sdhci_pltfm_free(pdev); 92 - return ret; 84 + return sdhci_add_host(host); 93 85 } 94 86 95 87 static const struct of_device_id sdhci_dove_of_match_table[] = {

+47 -31

drivers/mmc/host/sdhci-esdhc-imx.c

··· 212 212 /* The IP does not have GPIO CD wake capabilities */ 213 213 #define ESDHC_FLAG_SKIP_CD_WAKE BIT(18) 214 214 215 + /* the controller has dummy pad for clock loopback */ 216 + #define ESDHC_FLAG_DUMMY_PAD BIT(19) 217 + 215 218 #define ESDHC_AUTO_TUNING_WINDOW 3 216 219 217 220 enum wp_types { ··· 351 348 .quirks = SDHCI_QUIRK_NO_LED, 352 349 }; 353 350 351 + static struct esdhc_soc_data usdhc_imx95_data = { 352 + .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 353 + | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 354 + | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 355 + | ESDHC_FLAG_STATE_LOST_IN_LPMODE 356 + | ESDHC_FLAG_DUMMY_PAD, 357 + .quirks = SDHCI_QUIRK_NO_LED, 358 + }; 359 + 354 360 struct pltfm_imx_data { 355 361 u32 scratchpad; 356 362 struct pinctrl *pinctrl; ··· 404 392 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, }, 405 393 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, }, 406 394 { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, }, 395 + { .compatible = "fsl,imx94-usdhc", .data = &usdhc_imx95_data, }, 396 + { .compatible = "fsl,imx95-usdhc", .data = &usdhc_imx95_data, }, 407 397 { .compatible = "fsl,imxrt1050-usdhc", .data = &usdhc_imxrt1050_data, }, 408 398 { .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, }, 409 399 { /* sentinel */ } ··· 742 728 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 743 729 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 744 730 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 745 - u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 746 - if (val & SDHCI_CTRL_TUNED_CLK) { 731 + if (val & SDHCI_CTRL_TUNED_CLK) 747 732 v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 748 - } else { 733 + else 749 734 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 750 - m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 751 - } 752 735 753 - if (val & SDHCI_CTRL_EXEC_TUNING) { 736 + if (val & SDHCI_CTRL_EXEC_TUNING) 754 737 v |= ESDHC_MIX_CTRL_EXE_TUNE; 755 - m |= ESDHC_MIX_CTRL_FBCLK_SEL; 756 - } else { 738 + else 757 739 v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 758 - } 759 740 760 741 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 761 - writel(m, host->ioaddr + ESDHC_MIX_CTRL); 762 742 } 763 743 return; 764 744 case SDHCI_TRANSFER_MODE: ··· 1090 1082 ctrl &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 1091 1083 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1092 1084 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1093 - ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 1094 1085 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 1095 1086 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1096 1087 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { ··· 1184 1177 "warning! RESET_ALL never complete before sending tuning command\n"); 1185 1178 1186 1179 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 1187 - reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 1188 - ESDHC_MIX_CTRL_FBCLK_SEL; 1180 + reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL; 1189 1181 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 1190 1182 writel(FIELD_PREP(ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK, val), 1191 1183 host->ioaddr + ESDHC_TUNE_CTRL_STATUS); ··· 1438 1432 break; 1439 1433 } 1440 1434 1435 + if (!(imx_data->socdata->flags & ESDHC_FLAG_DUMMY_PAD) && 1436 + (timing == MMC_TIMING_UHS_SDR104 || 1437 + timing == MMC_TIMING_MMC_HS200 || 1438 + timing == MMC_TIMING_MMC_HS400)) 1439 + m |= ESDHC_MIX_CTRL_FBCLK_SEL; 1440 + else 1441 + m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 1442 + 1443 + writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1444 + 1441 1445 esdhc_change_pinstate(host, timing); 1442 1446 } 1443 1447 ··· 1693 1677 writel(reg, host->ioaddr + ESDHC_TUNING_CTRL); 1694 1678 1695 1679 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 1696 - reg |= ESDHC_MIX_CTRL_SMPCLK_SEL | ESDHC_MIX_CTRL_FBCLK_SEL; 1680 + reg |= ESDHC_MIX_CTRL_SMPCLK_SEL; 1681 + if (!(imx_data->socdata->flags & ESDHC_FLAG_DUMMY_PAD)) 1682 + reg |= ESDHC_MIX_CTRL_FBCLK_SEL; 1697 1683 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 1698 1684 1699 1685 writel(FIELD_PREP(ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK, ··· 1991 1973 free_sdhci: 1992 1974 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1993 1975 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 1994 - sdhci_pltfm_free(pdev); 1995 1976 return err; 1996 1977 } 1997 1978 ··· 2014 1997 2015 1998 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 2016 1999 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 2017 - 2018 - sdhci_pltfm_free(pdev); 2019 2000 } 2020 2001 2021 2002 #ifdef CONFIG_PM_SLEEP ··· 2054 2039 ret = sdhci_enable_irq_wakeups(host); 2055 2040 if (!ret) 2056 2041 dev_warn(dev, "Failed to enable irq wakeup\n"); 2042 + } else { 2043 + /* 2044 + * For the device which works as wakeup source, no need 2045 + * to change the pinctrl to sleep state. 2046 + * e.g. For SDIO device, the interrupt share with data pin, 2047 + * but the pinctrl sleep state may config the data pin to 2048 + * other function like GPIO function to save power in PM, 2049 + * which finally block the SDIO wakeup function. 2050 + */ 2051 + ret = pinctrl_pm_select_sleep_state(dev); 2052 + if (ret) 2053 + return ret; 2057 2054 } 2058 - 2059 - ret = pinctrl_pm_select_sleep_state(dev); 2060 - if (ret) 2061 - return ret; 2062 2055 2063 2056 ret = mmc_gpio_set_cd_wake(host->mmc, true); 2064 2057 ··· 2108 2085 esdhc_is_usdhc(imx_data)) 2109 2086 sdhc_esdhc_tuning_restore(host); 2110 2087 2111 - pm_runtime_mark_last_busy(dev); 2112 2088 pm_runtime_put_autosuspend(dev); 2113 2089 2114 2090 return ret; ··· 2128 2106 return ret; 2129 2107 } 2130 2108 2131 - ret = sdhci_runtime_suspend_host(host); 2132 - if (ret) 2133 - return ret; 2109 + sdhci_runtime_suspend_host(host); 2134 2110 2135 2111 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 2136 2112 mmc_retune_needed(host->mmc); ··· 2142 2122 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 2143 2123 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 2144 2124 2145 - return ret; 2125 + return 0; 2146 2126 } 2147 2127 2148 2128 static int sdhci_esdhc_runtime_resume(struct device *dev) ··· 2172 2152 2173 2153 esdhc_pltfm_set_clock(host, imx_data->actual_clock); 2174 2154 2175 - err = sdhci_runtime_resume_host(host, 0); 2176 - if (err) 2177 - goto disable_ipg_clk; 2155 + sdhci_runtime_resume_host(host, 0); 2178 2156 2179 2157 if (host->mmc->caps2 & MMC_CAP2_CQE) 2180 2158 err = cqhci_resume(host->mmc); 2181 2159 2182 2160 return err; 2183 2161 2184 - disable_ipg_clk: 2185 - clk_disable_unprepare(imx_data->clk_ipg); 2186 2162 disable_per_clk: 2187 2163 clk_disable_unprepare(imx_data->clk_per); 2188 2164 disable_ahb_clk:

+7 -18

drivers/mmc/host/sdhci-esdhc-mcf.c

··· 426 426 host->flags |= SDHCI_AUTO_CMD12; 427 427 428 428 mcf_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 429 - if (IS_ERR(mcf_data->clk_ipg)) { 430 - err = PTR_ERR(mcf_data->clk_ipg); 431 - goto err_exit; 432 - } 429 + if (IS_ERR(mcf_data->clk_ipg)) 430 + return PTR_ERR(mcf_data->clk_ipg); 433 431 434 432 mcf_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 435 - if (IS_ERR(mcf_data->clk_ahb)) { 436 - err = PTR_ERR(mcf_data->clk_ahb); 437 - goto err_exit; 438 - } 433 + if (IS_ERR(mcf_data->clk_ahb)) 434 + return PTR_ERR(mcf_data->clk_ahb); 439 435 440 436 mcf_data->clk_per = devm_clk_get(&pdev->dev, "per"); 441 - if (IS_ERR(mcf_data->clk_per)) { 442 - err = PTR_ERR(mcf_data->clk_per); 443 - goto err_exit; 444 - } 437 + if (IS_ERR(mcf_data->clk_per)) 438 + return PTR_ERR(mcf_data->clk_per); 445 439 446 440 pltfm_host->clk = mcf_data->clk_per; 447 441 pltfm_host->clock = clk_get_rate(pltfm_host->clk); 448 442 err = clk_prepare_enable(mcf_data->clk_per); 449 443 if (err) 450 - goto err_exit; 444 + return err; 451 445 452 446 err = clk_prepare_enable(mcf_data->clk_ipg); 453 447 if (err) ··· 479 485 clk_disable_unprepare(mcf_data->clk_ipg); 480 486 unprep_per: 481 487 clk_disable_unprepare(mcf_data->clk_per); 482 - err_exit: 483 - sdhci_pltfm_free(pdev); 484 - 485 488 return err; 486 489 } 487 490 ··· 493 502 clk_disable_unprepare(mcf_data->clk_ipg); 494 503 clk_disable_unprepare(mcf_data->clk_ahb); 495 504 clk_disable_unprepare(mcf_data->clk_per); 496 - 497 - sdhci_pltfm_free(pdev); 498 505 } 499 506 500 507 static struct platform_driver sdhci_esdhc_mcf_driver = {

+4 -14

drivers/mmc/host/sdhci-iproc.c

··· 379 379 380 380 ret = mmc_of_parse(host->mmc); 381 381 if (ret) 382 - goto err; 382 + return ret; 383 383 384 384 sdhci_get_property(pdev); 385 385 ··· 387 387 388 388 if (dev->of_node) { 389 389 pltfm_host->clk = devm_clk_get_enabled(dev, NULL); 390 - if (IS_ERR(pltfm_host->clk)) { 391 - ret = PTR_ERR(pltfm_host->clk); 392 - goto err; 393 - } 390 + if (IS_ERR(pltfm_host->clk)) 391 + return PTR_ERR(pltfm_host->clk); 394 392 } 395 393 396 394 if (iproc_host->data->missing_caps) { ··· 397 399 &iproc_host->data->caps1); 398 400 } 399 401 400 - ret = sdhci_add_host(host); 401 - if (ret) 402 - goto err; 403 - 404 - return 0; 405 - 406 - err: 407 - sdhci_pltfm_free(pdev); 408 - return ret; 402 + return sdhci_add_host(host); 409 403 } 410 404 411 405 static void sdhci_iproc_shutdown(struct platform_device *pdev)

+6 -13

drivers/mmc/host/sdhci-milbeaut.c

··· 258 258 259 259 ret = mmc_of_parse(host->mmc); 260 260 if (ret) 261 - goto err; 261 + return ret; 262 262 263 263 platform_set_drvdata(pdev, host); 264 264 ··· 267 267 host->irq = irq; 268 268 269 269 host->ioaddr = devm_platform_ioremap_resource(pdev, 0); 270 - if (IS_ERR(host->ioaddr)) { 271 - ret = PTR_ERR(host->ioaddr); 272 - goto err; 273 - } 270 + if (IS_ERR(host->ioaddr)) 271 + return PTR_ERR(host->ioaddr); 274 272 275 273 if (dev_of_node(dev)) { 276 274 sdhci_get_of_property(pdev); 277 275 278 276 priv->clk_iface = devm_clk_get(&pdev->dev, "iface"); 279 - if (IS_ERR(priv->clk_iface)) { 280 - ret = PTR_ERR(priv->clk_iface); 281 - goto err; 282 - } 277 + if (IS_ERR(priv->clk_iface)) 278 + return PTR_ERR(priv->clk_iface); 283 279 284 280 ret = clk_prepare_enable(priv->clk_iface); 285 281 if (ret) 286 - goto err; 282 + return ret; 287 283 288 284 priv->clk = devm_clk_get(&pdev->dev, "core"); 289 285 if (IS_ERR(priv->clk)) { ··· 304 308 clk_disable_unprepare(priv->clk); 305 309 err_clk: 306 310 clk_disable_unprepare(priv->clk_iface); 307 - err: 308 - sdhci_free_host(host); 309 311 return ret; 310 312 } 311 313 ··· 318 324 clk_disable_unprepare(priv->clk_iface); 319 325 clk_disable_unprepare(priv->clk); 320 326 321 - sdhci_free_host(host); 322 327 platform_set_drvdata(pdev, NULL); 323 328 } 324 329

+18 -8

drivers/mmc/host/sdhci-msm.c

··· 1564 1564 { 1565 1565 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1566 1566 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); 1567 + struct mmc_host *mmc = host->mmc; 1567 1568 bool done = false; 1568 1569 u32 val = SWITCHABLE_SIGNALING_VOLTAGE; 1569 1570 const struct sdhci_msm_offset *msm_offset = ··· 1622 1621 "%s: pwr_irq for req: (%d) timed out\n", 1623 1622 mmc_hostname(host->mmc), req_type); 1624 1623 } 1624 + 1625 + if ((req_type & REQ_BUS_ON) && mmc->card && !mmc->ops->get_cd(mmc)) { 1626 + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1627 + host->pwr = 0; 1628 + } 1629 + 1625 1630 pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc), 1626 1631 __func__, req_type); 1627 1632 } ··· 1684 1677 msm_offset->core_pwrctl_clear); 1685 1678 retry--; 1686 1679 udelay(10); 1680 + } 1681 + 1682 + if ((irq_status & CORE_PWRCTL_BUS_ON) && mmc->card && 1683 + !mmc->ops->get_cd(mmc)) { 1684 + msm_host_writel(msm_host, CORE_PWRCTL_BUS_FAIL, host, 1685 + msm_offset->core_pwrctl_ctl); 1686 + return; 1687 1687 } 1688 1688 1689 1689 /* Handle BUS ON/OFF*/ ··· 2540 2526 2541 2527 ret = mmc_of_parse(host->mmc); 2542 2528 if (ret) 2543 - goto pltfm_free; 2529 + return ret; 2544 2530 2545 2531 /* 2546 2532 * Based on the compatible string, load the required msm host info from ··· 2562 2548 2563 2549 ret = sdhci_msm_gcc_reset(&pdev->dev, host); 2564 2550 if (ret) 2565 - goto pltfm_free; 2551 + return ret; 2566 2552 2567 2553 /* Setup SDCC bus voter clock. */ 2568 2554 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); ··· 2570 2556 /* Vote for max. clk rate for max. performance */ 2571 2557 ret = clk_set_rate(msm_host->bus_clk, INT_MAX); 2572 2558 if (ret) 2573 - goto pltfm_free; 2559 + return ret; 2574 2560 ret = clk_prepare_enable(msm_host->bus_clk); 2575 2561 if (ret) 2576 - goto pltfm_free; 2562 + return ret; 2577 2563 } 2578 2564 2579 2565 /* Setup main peripheral bus clock */ ··· 2764 2750 if (ret) 2765 2751 goto pm_runtime_disable; 2766 2752 2767 - pm_runtime_mark_last_busy(&pdev->dev); 2768 2753 pm_runtime_put_autosuspend(&pdev->dev); 2769 2754 2770 2755 return 0; ··· 2778 2765 bus_clk_disable: 2779 2766 if (!IS_ERR(msm_host->bus_clk)) 2780 2767 clk_disable_unprepare(msm_host->bus_clk); 2781 - pltfm_free: 2782 - sdhci_pltfm_free(pdev); 2783 2768 return ret; 2784 2769 } 2785 2770 ··· 2799 2788 msm_host->bulk_clks); 2800 2789 if (!IS_ERR(msm_host->bus_clk)) 2801 2790 clk_disable_unprepare(msm_host->bus_clk); 2802 - sdhci_pltfm_free(pdev); 2803 2791 } 2804 2792 2805 2793 static __maybe_unused int sdhci_msm_runtime_suspend(struct device *dev)

+3 -12

drivers/mmc/host/sdhci-npcm.c

··· 48 48 49 49 pltfm_host->clk = devm_clk_get_optional_enabled(dev, NULL); 50 50 if (IS_ERR(pltfm_host->clk)) { 51 - ret = PTR_ERR(pltfm_host->clk); 52 - goto err_sdhci; 51 + return PTR_ERR(pltfm_host->clk); 53 52 } 54 53 55 54 caps = sdhci_readl(host, SDHCI_CAPABILITIES); ··· 57 58 58 59 ret = mmc_of_parse(host->mmc); 59 60 if (ret) 60 - goto err_sdhci; 61 + return ret; 61 62 62 - ret = sdhci_add_host(host); 63 - if (ret) 64 - goto err_sdhci; 65 - 66 - return 0; 67 - 68 - err_sdhci: 69 - sdhci_pltfm_free(pdev); 70 - return ret; 63 + return sdhci_add_host(host); 71 64 } 72 65 73 66 static const struct of_device_id npcm_sdhci_of_match[] = {

+8 -18

drivers/mmc/host/sdhci-of-arasan.c

··· 1883 1883 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); 1884 1884 of_node_put(node); 1885 1885 1886 - if (IS_ERR(sdhci_arasan->soc_ctl_base)) { 1887 - ret = dev_err_probe(dev, 1886 + if (IS_ERR(sdhci_arasan->soc_ctl_base)) 1887 + return dev_err_probe(dev, 1888 1888 PTR_ERR(sdhci_arasan->soc_ctl_base), 1889 1889 "Can't get syscon\n"); 1890 - goto err_pltfm_free; 1891 - } 1892 1890 } 1893 1891 1894 1892 sdhci_get_of_property(pdev); 1895 1893 1896 1894 sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb"); 1897 - if (IS_ERR(sdhci_arasan->clk_ahb)) { 1898 - ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb), 1895 + if (IS_ERR(sdhci_arasan->clk_ahb)) 1896 + return dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb), 1899 1897 "clk_ahb clock not found.\n"); 1900 - goto err_pltfm_free; 1901 - } 1902 1898 1903 1899 clk_xin = devm_clk_get(dev, "clk_xin"); 1904 - if (IS_ERR(clk_xin)) { 1905 - ret = dev_err_probe(dev, PTR_ERR(clk_xin), "clk_xin clock not found.\n"); 1906 - goto err_pltfm_free; 1907 - } 1900 + if (IS_ERR(clk_xin)) 1901 + return dev_err_probe(dev, PTR_ERR(clk_xin), "clk_xin clock not found.\n"); 1908 1902 1909 1903 ret = clk_prepare_enable(sdhci_arasan->clk_ahb); 1910 - if (ret) { 1911 - dev_err(dev, "Unable to enable AHB clock.\n"); 1912 - goto err_pltfm_free; 1913 - } 1904 + if (ret) 1905 + return dev_err_probe(dev, ret, "Unable to enable AHB clock.\n"); 1914 1906 1915 1907 /* If clock-frequency property is set, use the provided value */ 1916 1908 if (pltfm_host->clock && ··· 2021 2029 clk_disable_unprepare(clk_xin); 2022 2030 clk_dis_ahb: 2023 2031 clk_disable_unprepare(sdhci_arasan->clk_ahb); 2024 - err_pltfm_free: 2025 - sdhci_pltfm_free(pdev); 2026 2032 return ret; 2027 2033 } 2028 2034

+2 -8

drivers/mmc/host/sdhci-of-aspeed.c

··· 425 425 return PTR_ERR(pltfm_host->clk); 426 426 427 427 ret = clk_prepare_enable(pltfm_host->clk); 428 - if (ret) { 429 - dev_err(&pdev->dev, "Unable to enable SDIO clock\n"); 430 - goto err_pltfm_free; 431 - } 428 + if (ret) 429 + return dev_err_probe(&pdev->dev, ret, "Unable to enable SDIO clock\n"); 432 430 433 431 ret = mmc_of_parse(host->mmc); 434 432 if (ret) ··· 443 445 444 446 err_sdhci_add: 445 447 clk_disable_unprepare(pltfm_host->clk); 446 - err_pltfm_free: 447 - sdhci_pltfm_free(pdev); 448 448 return ret; 449 449 } 450 450 ··· 457 461 sdhci_remove_host(host, 0); 458 462 459 463 clk_disable_unprepare(pltfm_host->clk); 460 - 461 - sdhci_pltfm_free(pdev); 462 464 } 463 465 464 466 static const struct aspeed_sdhci_pdata ast2400_sdhci_pdata = {

+15 -23

drivers/mmc/host/sdhci-of-at91.c

··· 251 251 struct sdhci_host *host = dev_get_drvdata(dev); 252 252 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 253 253 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 254 - int ret; 255 254 256 - ret = sdhci_runtime_suspend_host(host); 255 + sdhci_runtime_suspend_host(host); 257 256 258 257 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 259 258 mmc_retune_needed(host->mmc); ··· 261 262 clk_disable_unprepare(priv->hclock); 262 263 clk_disable_unprepare(priv->mainck); 263 264 264 - return ret; 265 + return 0; 265 266 } 266 267 267 268 static int sdhci_at91_runtime_resume(struct device *dev) ··· 299 300 } 300 301 301 302 out: 302 - return sdhci_runtime_resume_host(host, 0); 303 + sdhci_runtime_resume_host(host, 0); 304 + return 0; 303 305 } 304 306 #endif /* CONFIG_PM */ 305 307 ··· 333 333 334 334 priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); 335 335 if (IS_ERR(priv->mainck)) { 336 - if (soc_data->baseclk_is_generated_internally) { 336 + if (soc_data->baseclk_is_generated_internally) 337 337 priv->mainck = NULL; 338 - } else { 339 - dev_err(&pdev->dev, "failed to get baseclk\n"); 340 - ret = PTR_ERR(priv->mainck); 341 - goto sdhci_pltfm_free; 342 - } 338 + else 339 + return dev_err_probe(&pdev->dev, PTR_ERR(priv->mainck), 340 + "failed to get baseclk\n"); 343 341 } 344 342 345 343 priv->hclock = devm_clk_get(&pdev->dev, "hclock"); 346 - if (IS_ERR(priv->hclock)) { 347 - dev_err(&pdev->dev, "failed to get hclock\n"); 348 - ret = PTR_ERR(priv->hclock); 349 - goto sdhci_pltfm_free; 350 - } 344 + if (IS_ERR(priv->hclock)) 345 + return dev_err_probe(&pdev->dev, PTR_ERR(priv->hclock), 346 + "failed to get hclock\n"); 351 347 352 348 priv->gck = devm_clk_get(&pdev->dev, "multclk"); 353 - if (IS_ERR(priv->gck)) { 354 - dev_err(&pdev->dev, "failed to get multclk\n"); 355 - ret = PTR_ERR(priv->gck); 356 - goto sdhci_pltfm_free; 357 - } 349 + if (IS_ERR(priv->gck)) 350 + return dev_err_probe(&pdev->dev, PTR_ERR(priv->gck), 351 + "failed to get multclk\n"); 358 352 359 353 ret = sdhci_at91_set_clks_presets(&pdev->dev); 360 354 if (ret) 361 - goto sdhci_pltfm_free; 355 + return ret; 362 356 363 357 priv->restore_needed = false; 364 358 ··· 432 438 clk_disable_unprepare(priv->gck); 433 439 clk_disable_unprepare(priv->mainck); 434 440 clk_disable_unprepare(priv->hclock); 435 - sdhci_pltfm_free: 436 - sdhci_pltfm_free(pdev); 437 441 return ret; 438 442 } 439 443

+5 -9

drivers/mmc/host/sdhci-of-dwcmshc.c

··· 1387 1387 1388 1388 if (dev->of_node) { 1389 1389 pltfm_host->clk = devm_clk_get(dev, "core"); 1390 - if (IS_ERR(pltfm_host->clk)) { 1391 - err = PTR_ERR(pltfm_host->clk); 1392 - dev_err(dev, "failed to get core clk: %d\n", err); 1393 - goto free_pltfm; 1394 - } 1390 + if (IS_ERR(pltfm_host->clk)) 1391 + return dev_err_probe(dev, PTR_ERR(pltfm_host->clk), 1392 + "failed to get core clk\n"); 1393 + 1395 1394 err = clk_prepare_enable(pltfm_host->clk); 1396 1395 if (err) 1397 - goto free_pltfm; 1396 + return err; 1398 1397 1399 1398 priv->bus_clk = devm_clk_get(dev, "bus"); 1400 1399 if (!IS_ERR(priv->bus_clk)) ··· 1466 1467 clk_disable_unprepare(pltfm_host->clk); 1467 1468 clk_disable_unprepare(priv->bus_clk); 1468 1469 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); 1469 - free_pltfm: 1470 - sdhci_pltfm_free(pdev); 1471 1470 return err; 1472 1471 } 1473 1472 ··· 1497 1500 clk_disable_unprepare(pltfm_host->clk); 1498 1501 clk_disable_unprepare(priv->bus_clk); 1499 1502 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); 1500 - sdhci_pltfm_free(pdev); 1501 1503 } 1502 1504 1503 1505 #ifdef CONFIG_PM_SLEEP

+2 -9

drivers/mmc/host/sdhci-of-esdhc.c

··· 1499 1499 /* call to generic mmc_of_parse to support additional capabilities */ 1500 1500 ret = mmc_of_parse(host->mmc); 1501 1501 if (ret) 1502 - goto err; 1502 + return ret; 1503 1503 1504 1504 mmc_of_parse_voltage(host->mmc, &host->ocr_mask); 1505 1505 1506 - ret = sdhci_add_host(host); 1507 - if (ret) 1508 - goto err; 1509 - 1510 - return 0; 1511 - err: 1512 - sdhci_pltfm_free(pdev); 1513 - return ret; 1506 + return sdhci_add_host(host); 1514 1507 } 1515 1508 1516 1509 static struct platform_driver sdhci_esdhc_driver = {

+65 -62

drivers/mmc/host/sdhci-of-k1.c

··· 20 20 #include "sdhci.h" 21 21 #include "sdhci-pltfm.h" 22 22 23 - #define SDHC_MMC_CTRL_REG 0x114 24 - #define MISC_INT_EN BIT(1) 25 - #define MISC_INT BIT(2) 26 - #define ENHANCE_STROBE_EN BIT(8) 27 - #define MMC_HS400 BIT(9) 28 - #define MMC_HS200 BIT(10) 29 - #define MMC_CARD_MODE BIT(12) 23 + #define SPACEMIT_SDHC_MMC_CTRL_REG 0x114 24 + #define SDHC_MISC_INT_EN BIT(1) 25 + #define SDHC_MISC_INT BIT(2) 26 + #define SDHC_ENHANCE_STROBE_EN BIT(8) 27 + #define SDHC_MMC_HS400 BIT(9) 28 + #define SDHC_MMC_HS200 BIT(10) 29 + #define SDHC_MMC_CARD_MODE BIT(12) 30 30 31 - #define SDHC_TX_CFG_REG 0x11C 32 - #define TX_INT_CLK_SEL BIT(30) 33 - #define TX_MUX_SEL BIT(31) 31 + #define SPACEMIT_SDHC_TX_CFG_REG 0x11C 32 + #define SDHC_TX_INT_CLK_SEL BIT(30) 33 + #define SDHC_TX_MUX_SEL BIT(31) 34 34 35 - #define SDHC_PHY_CTRL_REG 0x160 36 - #define PHY_FUNC_EN BIT(0) 37 - #define PHY_PLL_LOCK BIT(1) 38 - #define HOST_LEGACY_MODE BIT(31) 35 + #define SPACEMIT_SDHC_PHY_CTRL_REG 0x160 36 + #define SDHC_PHY_FUNC_EN BIT(0) 37 + #define SDHC_PHY_PLL_LOCK BIT(1) 38 + #define SDHC_HOST_LEGACY_MODE BIT(31) 39 39 40 - #define SDHC_PHY_FUNC_REG 0x164 41 - #define PHY_TEST_EN BIT(7) 42 - #define HS200_USE_RFIFO BIT(15) 40 + #define SPACEMIT_SDHC_PHY_FUNC_REG 0x164 41 + #define SDHC_PHY_TEST_EN BIT(7) 42 + #define SDHC_HS200_USE_RFIFO BIT(15) 43 43 44 - #define SDHC_PHY_DLLCFG 0x168 45 - #define DLL_PREDLY_NUM GENMASK(3, 2) 46 - #define DLL_FULLDLY_RANGE GENMASK(5, 4) 47 - #define DLL_VREG_CTRL GENMASK(7, 6) 48 - #define DLL_ENABLE BIT(31) 44 + #define SPACEMIT_SDHC_PHY_DLLCFG 0x168 45 + #define SDHC_DLL_PREDLY_NUM GENMASK(3, 2) 46 + #define SDHC_DLL_FULLDLY_RANGE GENMASK(5, 4) 47 + #define SDHC_DLL_VREG_CTRL GENMASK(7, 6) 48 + #define SDHC_DLL_ENABLE BIT(31) 49 49 50 - #define SDHC_PHY_DLLCFG1 0x16C 51 - #define DLL_REG1_CTRL GENMASK(7, 0) 52 - #define DLL_REG2_CTRL GENMASK(15, 8) 53 - #define DLL_REG3_CTRL GENMASK(23, 16) 54 - #define DLL_REG4_CTRL GENMASK(31, 24) 50 + #define SPACEMIT_SDHC_PHY_DLLCFG1 0x16C 51 + #define SDHC_DLL_REG1_CTRL GENMASK(7, 0) 52 + #define SDHC_DLL_REG2_CTRL GENMASK(15, 8) 53 + #define SDHC_DLL_REG3_CTRL GENMASK(23, 16) 54 + #define SDHC_DLL_REG4_CTRL GENMASK(31, 24) 55 55 56 - #define SDHC_PHY_DLLSTS 0x170 57 - #define DLL_LOCK_STATE BIT(0) 56 + #define SPACEMIT_SDHC_PHY_DLLSTS 0x170 57 + #define SDHC_DLL_LOCK_STATE BIT(0) 58 58 59 - #define SDHC_PHY_PADCFG_REG 0x178 60 - #define PHY_DRIVE_SEL GENMASK(2, 0) 61 - #define RX_BIAS_CTRL BIT(5) 59 + #define SPACEMIT_SDHC_PHY_PADCFG_REG 0x178 60 + #define SDHC_PHY_DRIVE_SEL GENMASK(2, 0) 61 + #define SDHC_RX_BIAS_CTRL BIT(5) 62 62 63 63 struct spacemit_sdhci_host { 64 64 struct clk *clk_core; ··· 91 91 if (mask != SDHCI_RESET_ALL) 92 92 return; 93 93 94 - spacemit_sdhci_setbits(host, PHY_FUNC_EN | PHY_PLL_LOCK, SDHC_PHY_CTRL_REG); 94 + spacemit_sdhci_setbits(host, SDHC_PHY_FUNC_EN | SDHC_PHY_PLL_LOCK, 95 + SPACEMIT_SDHC_PHY_CTRL_REG); 95 96 96 - spacemit_sdhci_clrsetbits(host, PHY_DRIVE_SEL, 97 - RX_BIAS_CTRL | FIELD_PREP(PHY_DRIVE_SEL, 4), 98 - SDHC_PHY_PADCFG_REG); 97 + spacemit_sdhci_clrsetbits(host, SDHC_PHY_DRIVE_SEL, 98 + SDHC_RX_BIAS_CTRL | FIELD_PREP(SDHC_PHY_DRIVE_SEL, 4), 99 + SPACEMIT_SDHC_PHY_PADCFG_REG); 99 100 100 101 if (!(host->mmc->caps2 & MMC_CAP2_NO_MMC)) 101 - spacemit_sdhci_setbits(host, MMC_CARD_MODE, SDHC_MMC_CTRL_REG); 102 + spacemit_sdhci_setbits(host, SDHC_MMC_CARD_MODE, SPACEMIT_SDHC_MMC_CTRL_REG); 102 103 } 103 104 104 105 static void spacemit_sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) 105 106 { 106 107 if (timing == MMC_TIMING_MMC_HS200) 107 - spacemit_sdhci_setbits(host, MMC_HS200, SDHC_MMC_CTRL_REG); 108 + spacemit_sdhci_setbits(host, SDHC_MMC_HS200, SPACEMIT_SDHC_MMC_CTRL_REG); 108 109 109 110 if (timing == MMC_TIMING_MMC_HS400) 110 - spacemit_sdhci_setbits(host, MMC_HS400, SDHC_MMC_CTRL_REG); 111 + spacemit_sdhci_setbits(host, SDHC_MMC_HS400, SPACEMIT_SDHC_MMC_CTRL_REG); 111 112 112 113 sdhci_set_uhs_signaling(host, timing); 113 114 ··· 121 120 struct mmc_host *mmc = host->mmc; 122 121 123 122 if (mmc->ios.timing <= MMC_TIMING_UHS_SDR50) 124 - spacemit_sdhci_setbits(host, TX_INT_CLK_SEL, SDHC_TX_CFG_REG); 123 + spacemit_sdhci_setbits(host, SDHC_TX_INT_CLK_SEL, SPACEMIT_SDHC_TX_CFG_REG); 125 124 else 126 - spacemit_sdhci_clrbits(host, TX_INT_CLK_SEL, SDHC_TX_CFG_REG); 125 + spacemit_sdhci_clrbits(host, SDHC_TX_INT_CLK_SEL, SPACEMIT_SDHC_TX_CFG_REG); 127 126 128 127 sdhci_set_clock(host, clock); 129 128 }; ··· 133 132 u32 state; 134 133 int ret; 135 134 136 - spacemit_sdhci_clrsetbits(host, DLL_PREDLY_NUM | DLL_FULLDLY_RANGE | DLL_VREG_CTRL, 137 - FIELD_PREP(DLL_PREDLY_NUM, 1) | 138 - FIELD_PREP(DLL_FULLDLY_RANGE, 1) | 139 - FIELD_PREP(DLL_VREG_CTRL, 1), 140 - SDHC_PHY_DLLCFG); 135 + spacemit_sdhci_clrsetbits(host, SDHC_DLL_PREDLY_NUM | 136 + SDHC_DLL_FULLDLY_RANGE | 137 + SDHC_DLL_VREG_CTRL, 138 + FIELD_PREP(SDHC_DLL_PREDLY_NUM, 1) | 139 + FIELD_PREP(SDHC_DLL_FULLDLY_RANGE, 1) | 140 + FIELD_PREP(SDHC_DLL_VREG_CTRL, 1), 141 + SPACEMIT_SDHC_PHY_DLLCFG); 141 142 142 - spacemit_sdhci_clrsetbits(host, DLL_REG1_CTRL, 143 - FIELD_PREP(DLL_REG1_CTRL, 0x92), 144 - SDHC_PHY_DLLCFG1); 143 + spacemit_sdhci_clrsetbits(host, SDHC_DLL_REG1_CTRL, 144 + FIELD_PREP(SDHC_DLL_REG1_CTRL, 0x92), 145 + SPACEMIT_SDHC_PHY_DLLCFG1); 145 146 146 - spacemit_sdhci_setbits(host, DLL_ENABLE, SDHC_PHY_DLLCFG); 147 + spacemit_sdhci_setbits(host, SDHC_DLL_ENABLE, SPACEMIT_SDHC_PHY_DLLCFG); 147 148 148 - ret = readl_poll_timeout(host->ioaddr + SDHC_PHY_DLLSTS, state, 149 - state & DLL_LOCK_STATE, 2, 100); 149 + ret = readl_poll_timeout(host->ioaddr + SPACEMIT_SDHC_PHY_DLLSTS, state, 150 + state & SDHC_DLL_LOCK_STATE, 2, 100); 150 151 if (ret == -ETIMEDOUT) 151 152 dev_warn(mmc_dev(host->mmc), "fail to lock phy dll in 100us!\n"); 152 153 } ··· 158 155 struct sdhci_host *host = mmc_priv(mmc); 159 156 160 157 if (!ios->enhanced_strobe) { 161 - spacemit_sdhci_clrbits(host, ENHANCE_STROBE_EN, SDHC_MMC_CTRL_REG); 158 + spacemit_sdhci_clrbits(host, SDHC_ENHANCE_STROBE_EN, SPACEMIT_SDHC_MMC_CTRL_REG); 162 159 return; 163 160 } 164 161 165 - spacemit_sdhci_setbits(host, ENHANCE_STROBE_EN, SDHC_MMC_CTRL_REG); 162 + spacemit_sdhci_setbits(host, SDHC_ENHANCE_STROBE_EN, SPACEMIT_SDHC_MMC_CTRL_REG); 166 163 spacemit_sdhci_phy_dll_init(host); 167 164 } 168 165 ··· 177 174 { 178 175 struct sdhci_host *host = mmc_priv(mmc); 179 176 180 - spacemit_sdhci_setbits(host, MMC_HS400, SDHC_MMC_CTRL_REG); 181 - host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 177 + spacemit_sdhci_setbits(host, SDHC_MMC_HS400, SPACEMIT_SDHC_MMC_CTRL_REG); 182 178 183 179 return 0; 184 180 } ··· 187 185 struct sdhci_host *host = mmc_priv(mmc); 188 186 189 187 spacemit_sdhci_phy_dll_init(host); 190 - host->mmc->caps &= ~MMC_CAP_WAIT_WHILE_BUSY; 191 188 } 192 189 193 190 static void spacemit_sdhci_pre_hs400_to_hs200(struct mmc_host *mmc) 194 191 { 195 192 struct sdhci_host *host = mmc_priv(mmc); 196 193 197 - spacemit_sdhci_clrbits(host, PHY_FUNC_EN | PHY_PLL_LOCK, SDHC_PHY_CTRL_REG); 198 - spacemit_sdhci_clrbits(host, MMC_HS400 | MMC_HS200 | ENHANCE_STROBE_EN, SDHC_MMC_CTRL_REG); 199 - spacemit_sdhci_clrbits(host, HS200_USE_RFIFO, SDHC_PHY_FUNC_REG); 194 + spacemit_sdhci_clrbits(host, SDHC_PHY_FUNC_EN | SDHC_PHY_PLL_LOCK, 195 + SPACEMIT_SDHC_PHY_CTRL_REG); 196 + spacemit_sdhci_clrbits(host, SDHC_MMC_HS400 | SDHC_MMC_HS200 | SDHC_ENHANCE_STROBE_EN, 197 + SPACEMIT_SDHC_MMC_CTRL_REG); 198 + spacemit_sdhci_clrbits(host, SDHC_HS200_USE_RFIFO, SPACEMIT_SDHC_PHY_FUNC_REG); 200 199 201 200 udelay(5); 202 201 203 - spacemit_sdhci_setbits(host, PHY_FUNC_EN | PHY_PLL_LOCK, SDHC_PHY_CTRL_REG); 202 + spacemit_sdhci_setbits(host, SDHC_PHY_FUNC_EN | SDHC_PHY_PLL_LOCK, 203 + SPACEMIT_SDHC_PHY_CTRL_REG); 204 204 } 205 205 206 206 static inline int spacemit_sdhci_get_clocks(struct device *dev, ··· 291 287 return 0; 292 288 293 289 err_pltfm: 294 - sdhci_pltfm_free(pdev); 295 290 return ret; 296 291 } 297 292

+8 -15

drivers/mmc/host/sdhci-of-ma35d1.c

··· 211 211 priv = sdhci_pltfm_priv(pltfm_host); 212 212 213 213 pltfm_host->clk = devm_clk_get_optional_enabled(dev, NULL); 214 - if (IS_ERR(pltfm_host->clk)) { 215 - err = dev_err_probe(dev, PTR_ERR(pltfm_host->clk), "failed to get clk\n"); 216 - goto err_sdhci; 217 - } 214 + if (IS_ERR(pltfm_host->clk)) 215 + return dev_err_probe(dev, PTR_ERR(pltfm_host->clk), 216 + "failed to get clk\n"); 218 217 219 218 err = mmc_of_parse(host->mmc); 220 219 if (err) 221 - goto err_sdhci; 220 + return err; 222 221 223 222 priv->rst = devm_reset_control_get_exclusive(dev, NULL); 224 - if (IS_ERR(priv->rst)) { 225 - err = dev_err_probe(dev, PTR_ERR(priv->rst), "failed to get reset control\n"); 226 - goto err_sdhci; 227 - } 223 + if (IS_ERR(priv->rst)) 224 + return dev_err_probe(dev, PTR_ERR(priv->rst), 225 + "failed to get reset control\n"); 228 226 229 227 sdhci_get_of_property(pdev); 230 228 ··· 253 255 254 256 err = sdhci_add_host(host); 255 257 if (err) 256 - goto err_sdhci; 258 + return err; 257 259 258 260 /* 259 261 * Split data into chunks of 16 or 8 bytes for transmission. ··· 266 268 sdhci_writew(host, ctl, MA35_SDHCI_MBIUCTL); 267 269 268 270 return 0; 269 - 270 - err_sdhci: 271 - sdhci_pltfm_free(pdev); 272 - return err; 273 271 } 274 272 275 273 static void ma35_disable_card_clk(struct sdhci_host *host) ··· 285 291 286 292 sdhci_remove_host(host, 0); 287 293 ma35_disable_card_clk(host); 288 - sdhci_pltfm_free(pdev); 289 294 } 290 295 291 296 static const struct of_device_id sdhci_ma35_dt_ids[] = {

+8 -16

drivers/mmc/host/sdhci-of-sparx5.c

··· 185 185 sdhci_sparx5->host = host; 186 186 187 187 pltfm_host->clk = devm_clk_get_enabled(&pdev->dev, "core"); 188 - if (IS_ERR(pltfm_host->clk)) { 189 - ret = PTR_ERR(pltfm_host->clk); 190 - dev_err(&pdev->dev, "failed to get and enable core clk: %d\n", ret); 191 - goto free_pltfm; 192 - } 188 + if (IS_ERR(pltfm_host->clk)) 189 + return dev_err_probe(&pdev->dev, PTR_ERR(pltfm_host->clk), 190 + "failed to get and enable core clk\n"); 193 191 194 192 if (!of_property_read_u32(np, "microchip,clock-delay", &value) && 195 193 (value > 0 && value <= MSHC_DLY_CC_MAX)) ··· 197 199 198 200 ret = mmc_of_parse(host->mmc); 199 201 if (ret) 200 - goto free_pltfm; 202 + return ret; 201 203 202 204 sdhci_sparx5->cpu_ctrl = syscon_regmap_lookup_by_compatible(syscon); 203 - if (IS_ERR(sdhci_sparx5->cpu_ctrl)) { 204 - dev_err(&pdev->dev, "No CPU syscon regmap !\n"); 205 - ret = PTR_ERR(sdhci_sparx5->cpu_ctrl); 206 - goto free_pltfm; 207 - } 205 + if (IS_ERR(sdhci_sparx5->cpu_ctrl)) 206 + return dev_err_probe(&pdev->dev, PTR_ERR(sdhci_sparx5->cpu_ctrl), 207 + "No CPU syscon regmap !\n"); 208 208 209 209 if (sdhci_sparx5->delay_clock >= 0) 210 210 sparx5_set_delay(host, sdhci_sparx5->delay_clock); ··· 218 222 219 223 ret = sdhci_add_host(host); 220 224 if (ret) 221 - goto free_pltfm; 225 + return ret; 222 226 223 227 /* Set AXI bus master to use un-cached access (for DMA) */ 224 228 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA) && ··· 230 234 pr_debug("%s: SDHC type: 0x%08x\n", 231 235 mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_TYPE)); 232 236 233 - return ret; 234 - 235 - free_pltfm: 236 - sdhci_pltfm_free(pdev); 237 237 return ret; 238 238 } 239 239

+7 -16

drivers/mmc/host/sdhci-omap.c

··· 1257 1257 sdhci_get_of_property(pdev); 1258 1258 ret = mmc_of_parse(mmc); 1259 1259 if (ret) 1260 - goto err_pltfm_free; 1260 + return ret; 1261 1261 1262 1262 soc = soc_device_match(sdhci_omap_soc_devices); 1263 1263 if (soc) { ··· 1274 1274 mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT; 1275 1275 1276 1276 pltfm_host->clk = devm_clk_get(dev, "fck"); 1277 - if (IS_ERR(pltfm_host->clk)) { 1278 - ret = PTR_ERR(pltfm_host->clk); 1279 - goto err_pltfm_free; 1280 - } 1277 + if (IS_ERR(pltfm_host->clk)) 1278 + return PTR_ERR(pltfm_host->clk); 1281 1279 1282 1280 ret = clk_set_rate(pltfm_host->clk, mmc->f_max); 1283 - if (ret) { 1284 - dev_err(dev, "failed to set clock to %d\n", mmc->f_max); 1285 - goto err_pltfm_free; 1286 - } 1281 + if (ret) 1282 + return dev_err_probe(dev, ret, 1283 + "failed to set clock to %d\n", mmc->f_max); 1287 1284 1288 1285 omap_host->pbias = devm_regulator_get_optional(dev, "pbias"); 1289 1286 if (IS_ERR(omap_host->pbias)) { 1290 1287 ret = PTR_ERR(omap_host->pbias); 1291 1288 if (ret != -ENODEV) 1292 - goto err_pltfm_free; 1289 + return ret; 1293 1290 dev_dbg(dev, "unable to get pbias regulator %d\n", ret); 1294 1291 } 1295 1292 omap_host->pbias_enabled = false; ··· 1370 1373 host->mmc->pm_caps |= MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; 1371 1374 } 1372 1375 1373 - pm_runtime_mark_last_busy(dev); 1374 1376 pm_runtime_put_autosuspend(dev); 1375 1377 1376 1378 return 0; ··· 1378 1382 sdhci_cleanup_host(host); 1379 1383 1380 1384 err_rpm_put: 1381 - pm_runtime_mark_last_busy(dev); 1382 1385 pm_runtime_put_autosuspend(dev); 1383 1386 err_rpm_disable: 1384 1387 pm_runtime_dont_use_autosuspend(dev); 1385 1388 pm_runtime_disable(dev); 1386 - 1387 - err_pltfm_free: 1388 - sdhci_pltfm_free(pdev); 1389 1389 return ret; 1390 1390 } 1391 1391 ··· 1398 1406 pm_runtime_put_sync(dev); 1399 1407 /* Ensure device gets disabled despite userspace sysfs config */ 1400 1408 pm_runtime_force_suspend(dev); 1401 - sdhci_pltfm_free(pdev); 1402 1409 } 1403 1410 1404 1411 #ifdef CONFIG_PM

+6 -22

drivers/mmc/host/sdhci-pci-core.c

··· 152 152 { 153 153 struct sdhci_pci_slot *slot; 154 154 struct sdhci_host *host; 155 - int i, ret; 156 155 157 - for (i = 0; i < chip->num_slots; i++) { 156 + for (int i = 0; i < chip->num_slots; i++) { 158 157 slot = chip->slots[i]; 159 158 if (!slot) 160 159 continue; 161 160 162 161 host = slot->host; 163 162 164 - ret = sdhci_runtime_suspend_host(host); 165 - if (ret) 166 - goto err_pci_runtime_suspend; 163 + sdhci_runtime_suspend_host(host); 167 164 168 165 if (chip->rpm_retune && 169 166 host->tuning_mode != SDHCI_TUNING_MODE_3) ··· 168 171 } 169 172 170 173 return 0; 171 - 172 - err_pci_runtime_suspend: 173 - while (--i >= 0) 174 - sdhci_runtime_resume_host(chip->slots[i]->host, 0); 175 - return ret; 176 174 } 177 175 178 176 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 179 177 { 180 178 struct sdhci_pci_slot *slot; 181 - int i, ret; 182 179 183 - for (i = 0; i < chip->num_slots; i++) { 180 + for (int i = 0; i < chip->num_slots; i++) { 184 181 slot = chip->slots[i]; 185 182 if (!slot) 186 183 continue; 187 184 188 - ret = sdhci_runtime_resume_host(slot->host, 0); 189 - if (ret) 190 - return ret; 185 + sdhci_runtime_resume_host(slot->host, 0); 191 186 } 192 187 193 188 return 0; ··· 2163 2174 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 2164 2175 if (ret) { 2165 2176 dev_err(&pdev->dev, "cannot request region\n"); 2166 - goto cleanup; 2177 + return ERR_PTR(ret); 2167 2178 } 2168 2179 2169 2180 host->ioaddr = pcim_iomap_table(pdev)[bar]; ··· 2171 2182 if (chip->fixes && chip->fixes->probe_slot) { 2172 2183 ret = chip->fixes->probe_slot(slot); 2173 2184 if (ret) 2174 - goto cleanup; 2185 + return ERR_PTR(ret); 2175 2186 } 2176 2187 2177 2188 host->mmc->pm_caps = MMC_PM_KEEP_POWER; ··· 2232 2243 if (chip->fixes && chip->fixes->remove_slot) 2233 2244 chip->fixes->remove_slot(slot, 0); 2234 2245 2235 - cleanup: 2236 - sdhci_free_host(host); 2237 - 2238 2246 return ERR_PTR(ret); 2239 2247 } 2240 2248 ··· 2252 2266 2253 2267 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2254 2268 slot->chip->fixes->remove_slot(slot, dead); 2255 - 2256 - sdhci_free_host(slot->host); 2257 2269 } 2258 2270 2259 2271 int sdhci_pci_uhs2_add_host(struct sdhci_pci_slot *slot)

+3 -6

drivers/mmc/host/sdhci-pic32.c

··· 157 157 ret = plat_data->setup_dma(ADMA_FIFO_RD_THSHLD, 158 158 ADMA_FIFO_WR_THSHLD); 159 159 if (ret) 160 - goto err_host; 160 + goto err; 161 161 } 162 162 163 163 sdhci_pdata->sys_clk = devm_clk_get(&pdev->dev, "sys_clk"); 164 164 if (IS_ERR(sdhci_pdata->sys_clk)) { 165 165 ret = PTR_ERR(sdhci_pdata->sys_clk); 166 166 dev_err(&pdev->dev, "Error getting clock\n"); 167 - goto err_host; 167 + goto err; 168 168 } 169 169 170 170 ret = clk_prepare_enable(sdhci_pdata->sys_clk); 171 171 if (ret) { 172 172 dev_err(&pdev->dev, "Error enabling clock\n"); 173 - goto err_host; 173 + goto err; 174 174 } 175 175 176 176 sdhci_pdata->base_clk = devm_clk_get(&pdev->dev, "base_clk"); ··· 203 203 clk_disable_unprepare(sdhci_pdata->base_clk); 204 204 err_sys_clk: 205 205 clk_disable_unprepare(sdhci_pdata->sys_clk); 206 - err_host: 207 - sdhci_pltfm_free(pdev); 208 206 err: 209 207 dev_err(&pdev->dev, "pic32-sdhci probe failed: %d\n", ret); 210 208 return ret; ··· 218 220 sdhci_remove_host(host, scratch == (u32)~0); 219 221 clk_disable_unprepare(sdhci_pdata->base_clk); 220 222 clk_disable_unprepare(sdhci_pdata->sys_clk); 221 - sdhci_pltfm_free(pdev); 222 223 } 223 224 224 225 static const struct of_device_id pic32_sdhci_id_table[] = {

+1 -15

drivers/mmc/host/sdhci-pltfm.c

··· 146 146 } 147 147 EXPORT_SYMBOL_GPL(sdhci_pltfm_init); 148 148 149 - void sdhci_pltfm_free(struct platform_device *pdev) 150 - { 151 - struct sdhci_host *host = platform_get_drvdata(pdev); 152 - 153 - sdhci_free_host(host); 154 - } 155 - EXPORT_SYMBOL_GPL(sdhci_pltfm_free); 156 - 157 149 int sdhci_pltfm_init_and_add_host(struct platform_device *pdev, 158 150 const struct sdhci_pltfm_data *pdata, 159 151 size_t priv_size) 160 152 { 161 153 struct sdhci_host *host; 162 - int ret = 0; 163 154 164 155 host = sdhci_pltfm_init(pdev, pdata, priv_size); 165 156 if (IS_ERR(host)) ··· 158 167 159 168 sdhci_get_property(pdev); 160 169 161 - ret = sdhci_add_host(host); 162 - if (ret) 163 - sdhci_pltfm_free(pdev); 164 - 165 - return ret; 170 + return sdhci_add_host(host); 166 171 } 167 172 EXPORT_SYMBOL_GPL(sdhci_pltfm_init_and_add_host); 168 173 ··· 168 181 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 169 182 170 183 sdhci_remove_host(host, dead); 171 - sdhci_pltfm_free(pdev); 172 184 } 173 185 EXPORT_SYMBOL_GPL(sdhci_pltfm_remove); 174 186

-1

drivers/mmc/host/sdhci-pltfm.h

··· 97 97 extern struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev, 98 98 const struct sdhci_pltfm_data *pdata, 99 99 size_t priv_size); 100 - extern void sdhci_pltfm_free(struct platform_device *pdev); 101 100 102 101 extern int sdhci_pltfm_init_and_add_host(struct platform_device *pdev, 103 102 const struct sdhci_pltfm_data *pdata,

+6 -20

drivers/mmc/host/sdhci-pxav2.c

··· 258 258 struct sdhci_host *host = NULL; 259 259 const struct sdhci_pxa_variant *variant; 260 260 261 - int ret; 262 261 struct clk *clk, *clk_core; 263 262 264 263 host = sdhci_pltfm_init(pdev, NULL, sizeof(*pxav2_host)); ··· 270 271 clk = devm_clk_get_optional_enabled(dev, "io"); 271 272 if (!clk) 272 273 clk = devm_clk_get_enabled(dev, NULL); 273 - if (IS_ERR(clk)) { 274 - ret = PTR_ERR(clk); 275 - dev_err_probe(dev, ret, "failed to get io clock\n"); 276 - goto free; 277 - } 274 + if (IS_ERR(clk)) 275 + return dev_err_probe(dev, PTR_ERR(clk), "failed to get io clock\n"); 278 276 pltfm_host->clk = clk; 279 277 280 278 clk_core = devm_clk_get_optional_enabled(dev, "core"); 281 - if (IS_ERR(clk_core)) { 282 - ret = PTR_ERR(clk_core); 283 - dev_err_probe(dev, ret, "failed to enable core clock\n"); 284 - goto free; 285 - } 279 + if (IS_ERR(clk_core)) 280 + return dev_err_probe(dev, PTR_ERR(clk_core), 281 + "failed to enable core clock\n"); 286 282 287 283 host->quirks = SDHCI_QUIRK_BROKEN_ADMA 288 284 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL ··· 326 332 pxav2_host->pinctrl = NULL; 327 333 } 328 334 329 - ret = sdhci_add_host(host); 330 - if (ret) 331 - goto free; 332 - 333 - return 0; 334 - 335 - free: 336 - sdhci_pltfm_free(pdev); 337 - return ret; 335 + return sdhci_add_host(host); 338 336 } 339 337 340 338 static struct platform_driver sdhci_pxav2_driver = {

+4 -13

drivers/mmc/host/sdhci-pxav3.c

··· 389 389 pxa->clk_io = devm_clk_get(dev, NULL); 390 390 if (IS_ERR(pxa->clk_io)) { 391 391 dev_err(dev, "failed to get io clock\n"); 392 - ret = PTR_ERR(pxa->clk_io); 393 - goto err_clk_get; 392 + return PTR_ERR(pxa->clk_io); 394 393 } 395 394 pltfm_host->clk = pxa->clk_io; 396 395 clk_prepare_enable(pxa->clk_io); ··· 465 466 err_mbus_win: 466 467 clk_disable_unprepare(pxa->clk_io); 467 468 clk_disable_unprepare(pxa->clk_core); 468 - err_clk_get: 469 - sdhci_pltfm_free(pdev); 470 469 return ret; 471 470 } 472 471 ··· 482 485 483 486 clk_disable_unprepare(pxa->clk_io); 484 487 clk_disable_unprepare(pxa->clk_core); 485 - 486 - sdhci_pltfm_free(pdev); 487 488 } 488 489 489 490 #ifdef CONFIG_PM_SLEEP ··· 494 499 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 495 500 mmc_retune_needed(host->mmc); 496 501 ret = sdhci_suspend_host(host); 497 - pm_runtime_mark_last_busy(dev); 498 502 pm_runtime_put_autosuspend(dev); 499 503 500 504 return ret; ··· 506 512 507 513 pm_runtime_get_sync(dev); 508 514 ret = sdhci_resume_host(host); 509 - pm_runtime_mark_last_busy(dev); 510 515 pm_runtime_put_autosuspend(dev); 511 516 512 517 return ret; ··· 518 525 struct sdhci_host *host = dev_get_drvdata(dev); 519 526 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 520 527 struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host); 521 - int ret; 522 528 523 - ret = sdhci_runtime_suspend_host(host); 524 - if (ret) 525 - return ret; 529 + sdhci_runtime_suspend_host(host); 526 530 527 531 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 528 532 mmc_retune_needed(host->mmc); ··· 541 551 if (!IS_ERR(pxa->clk_core)) 542 552 clk_prepare_enable(pxa->clk_core); 543 553 544 - return sdhci_runtime_resume_host(host, 0); 554 + sdhci_runtime_resume_host(host, 0); 555 + return 0; 545 556 } 546 557 #endif 547 558

+8 -18

drivers/mmc/host/sdhci-s3c.c

··· 507 507 sc = sdhci_priv(host); 508 508 509 509 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 510 - if (!pdata) { 511 - ret = -ENOMEM; 512 - goto err_pdata_io_clk; 513 - } 510 + if (!pdata) 511 + return -ENOMEM; 514 512 515 513 if (pdev->dev.of_node) { 516 514 ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata); 517 515 if (ret) 518 - goto err_pdata_io_clk; 516 + return ret; 519 517 } else { 520 518 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata)); 521 519 } ··· 530 532 sc->clk_io = devm_clk_get(dev, "hsmmc"); 531 533 if (IS_ERR(sc->clk_io)) { 532 534 dev_err(dev, "failed to get io clock\n"); 533 - ret = PTR_ERR(sc->clk_io); 534 - goto err_pdata_io_clk; 535 + return PTR_ERR(sc->clk_io); 535 536 } 536 537 537 538 /* enable the local io clock and keep it running for the moment. */ ··· 658 661 err_no_busclks: 659 662 clk_disable_unprepare(sc->clk_io); 660 663 661 - err_pdata_io_clk: 662 - sdhci_free_host(host); 663 - 664 664 return ret; 665 665 } 666 666 ··· 679 685 pm_runtime_disable(&pdev->dev); 680 686 681 687 clk_disable_unprepare(sc->clk_io); 682 - 683 - sdhci_free_host(host); 684 688 } 685 689 686 690 #ifdef CONFIG_PM_SLEEP ··· 706 714 struct sdhci_host *host = dev_get_drvdata(dev); 707 715 struct sdhci_s3c *ourhost = to_s3c(host); 708 716 struct clk *busclk = ourhost->clk_io; 709 - int ret; 710 717 711 - ret = sdhci_runtime_suspend_host(host); 718 + sdhci_runtime_suspend_host(host); 712 719 713 720 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 714 721 mmc_retune_needed(host->mmc); ··· 715 724 if (ourhost->cur_clk >= 0) 716 725 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]); 717 726 clk_disable_unprepare(busclk); 718 - return ret; 727 + return 0; 719 728 } 720 729 721 730 static int sdhci_s3c_runtime_resume(struct device *dev) ··· 723 732 struct sdhci_host *host = dev_get_drvdata(dev); 724 733 struct sdhci_s3c *ourhost = to_s3c(host); 725 734 struct clk *busclk = ourhost->clk_io; 726 - int ret; 727 735 728 736 clk_prepare_enable(busclk); 729 737 if (ourhost->cur_clk >= 0) 730 738 clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]); 731 - ret = sdhci_runtime_resume_host(host, 0); 732 - return ret; 739 + sdhci_runtime_resume_host(host, 0); 740 + return 0; 733 741 } 734 742 #endif 735 743

+4 -7

drivers/mmc/host/sdhci-spear.c

··· 59 59 if (IS_ERR(host->ioaddr)) { 60 60 ret = PTR_ERR(host->ioaddr); 61 61 dev_dbg(&pdev->dev, "unable to map iomem: %d\n", ret); 62 - goto err_host; 62 + goto err; 63 63 } 64 64 65 65 host->hw_name = "sdhci"; ··· 67 67 host->irq = platform_get_irq(pdev, 0); 68 68 if (host->irq < 0) { 69 69 ret = host->irq; 70 - goto err_host; 70 + goto err; 71 71 } 72 72 host->quirks = SDHCI_QUIRK_BROKEN_ADMA; 73 73 ··· 78 78 if (IS_ERR(sdhci->clk)) { 79 79 ret = PTR_ERR(sdhci->clk); 80 80 dev_dbg(&pdev->dev, "Error getting clock\n"); 81 - goto err_host; 81 + goto err; 82 82 } 83 83 84 84 ret = clk_prepare_enable(sdhci->clk); 85 85 if (ret) { 86 86 dev_dbg(&pdev->dev, "Error enabling clock\n"); 87 - goto err_host; 87 + goto err; 88 88 } 89 89 90 90 ret = clk_set_rate(sdhci->clk, 50000000); ··· 110 110 111 111 disable_clk: 112 112 clk_disable_unprepare(sdhci->clk); 113 - err_host: 114 - sdhci_free_host(host); 115 113 err: 116 114 dev_err(&pdev->dev, "spear-sdhci probe failed: %d\n", ret); 117 115 return ret; ··· 128 130 129 131 sdhci_remove_host(host, dead); 130 132 clk_disable_unprepare(sdhci->clk); 131 - sdhci_free_host(host); 132 133 } 133 134 134 135 #ifdef CONFIG_PM_SLEEP

+10 -24

drivers/mmc/host/sdhci-sprd.c

··· 764 764 765 765 ret = mmc_of_parse(host->mmc); 766 766 if (ret) 767 - goto pltfm_free; 767 + return ret; 768 768 769 769 if (!mmc_card_is_removable(host->mmc)) 770 770 host->mmc_host_ops.request_atomic = sdhci_sprd_request_atomic; ··· 778 778 if (!IS_ERR(sprd_host->pinctrl)) { 779 779 sprd_host->pins_uhs = 780 780 pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs"); 781 - if (IS_ERR(sprd_host->pins_uhs)) { 782 - ret = PTR_ERR(sprd_host->pins_uhs); 783 - goto pltfm_free; 784 - } 781 + if (IS_ERR(sprd_host->pins_uhs)) 782 + return PTR_ERR(sprd_host->pins_uhs); 785 783 786 784 sprd_host->pins_default = 787 785 pinctrl_lookup_state(sprd_host->pinctrl, "default"); 788 - if (IS_ERR(sprd_host->pins_default)) { 789 - ret = PTR_ERR(sprd_host->pins_default); 790 - goto pltfm_free; 791 - } 786 + if (IS_ERR(sprd_host->pins_default)) 787 + return PTR_ERR(sprd_host->pins_default); 792 788 } 793 789 794 790 clk = devm_clk_get(&pdev->dev, "sdio"); 795 - if (IS_ERR(clk)) { 796 - ret = PTR_ERR(clk); 797 - goto pltfm_free; 798 - } 791 + if (IS_ERR(clk)) 792 + return PTR_ERR(clk); 799 793 sprd_host->clk_sdio = clk; 800 794 sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); 801 795 if (!sprd_host->base_rate) 802 796 sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; 803 797 804 798 clk = devm_clk_get(&pdev->dev, "enable"); 805 - if (IS_ERR(clk)) { 806 - ret = PTR_ERR(clk); 807 - goto pltfm_free; 808 - } 799 + if (IS_ERR(clk)) 800 + return PTR_ERR(clk); 809 801 sprd_host->clk_enable = clk; 810 802 811 803 clk = devm_clk_get(&pdev->dev, "2x_enable"); ··· 806 814 807 815 ret = clk_prepare_enable(sprd_host->clk_sdio); 808 816 if (ret) 809 - goto pltfm_free; 817 + return ret; 810 818 811 819 ret = clk_prepare_enable(sprd_host->clk_enable); 812 820 if (ret) ··· 863 871 if (ret) 864 872 goto err_cleanup_host; 865 873 866 - pm_runtime_mark_last_busy(&pdev->dev); 867 874 pm_runtime_put_autosuspend(&pdev->dev); 868 875 869 876 return 0; ··· 882 891 883 892 clk_disable: 884 893 clk_disable_unprepare(sprd_host->clk_sdio); 885 - 886 - pltfm_free: 887 - sdhci_pltfm_free(pdev); 888 894 return ret; 889 895 } 890 896 ··· 895 907 clk_disable_unprepare(sprd_host->clk_sdio); 896 908 clk_disable_unprepare(sprd_host->clk_enable); 897 909 clk_disable_unprepare(sprd_host->clk_2x_enable); 898 - 899 - sdhci_pltfm_free(pdev); 900 910 } 901 911 902 912 static const struct of_device_id sdhci_sprd_of_match[] = {

+2 -4

drivers/mmc/host/sdhci-st.c

··· 380 380 ret = mmc_of_parse(host->mmc); 381 381 if (ret) { 382 382 dev_err(&pdev->dev, "Failed mmc_of_parse\n"); 383 - goto err_of; 383 + goto err_pltfm_init; 384 384 } 385 385 386 386 ret = clk_prepare_enable(clk); 387 387 if (ret) { 388 388 dev_err(&pdev->dev, "Failed to prepare clock\n"); 389 - goto err_of; 389 + goto err_pltfm_init; 390 390 } 391 391 392 392 ret = clk_prepare_enable(icnclk); ··· 423 423 clk_disable_unprepare(icnclk); 424 424 err_icnclk: 425 425 clk_disable_unprepare(clk); 426 - err_of: 427 - sdhci_pltfm_free(pdev); 428 426 err_pltfm_init: 429 427 reset_control_assert(rstc); 430 428

+3 -6

drivers/mmc/host/sdhci-tegra.c

··· 1693 1693 1694 1694 rc = mmc_of_parse(host->mmc); 1695 1695 if (rc) 1696 - goto err_parse_dt; 1696 + return rc; 1697 1697 1698 1698 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 1699 1699 host->mmc->caps |= MMC_CAP_1_8V_DDR; ··· 1739 1739 if (IS_ERR(clk)) { 1740 1740 rc = PTR_ERR(clk); 1741 1741 if (rc == -EPROBE_DEFER) 1742 - goto err_power_req; 1742 + return rc; 1743 1743 1744 1744 dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc); 1745 1745 clk = NULL; ··· 1750 1750 if (rc) { 1751 1751 dev_err(&pdev->dev, 1752 1752 "failed to enable tmclk: %d\n", rc); 1753 - goto err_power_req; 1753 + return rc; 1754 1754 } 1755 1755 1756 1756 tegra_host->tmclk = clk; ··· 1811 1811 err_clk_get: 1812 1812 clk_disable_unprepare(tegra_host->tmclk); 1813 1813 err_power_req: 1814 - err_parse_dt: 1815 - sdhci_pltfm_free(pdev); 1816 1814 return rc; 1817 1815 } 1818 1816 ··· 1829 1831 pm_runtime_force_suspend(&pdev->dev); 1830 1832 1831 1833 clk_disable_unprepare(tegra_host->tmclk); 1832 - sdhci_pltfm_free(pdev); 1833 1834 } 1834 1835 1835 1836 static int __maybe_unused sdhci_tegra_runtime_suspend(struct device *dev)

+7 -17

drivers/mmc/host/sdhci-xenon.c

··· 532 532 533 533 if (dev->of_node) { 534 534 pltfm_host->clk = devm_clk_get(&pdev->dev, "core"); 535 - if (IS_ERR(pltfm_host->clk)) { 536 - err = PTR_ERR(pltfm_host->clk); 537 - dev_err(&pdev->dev, "Failed to setup input clk: %d\n", err); 538 - goto free_pltfm; 539 - } 535 + if (IS_ERR(pltfm_host->clk)) 536 + return dev_err_probe(&pdev->dev, PTR_ERR(pltfm_host->clk), 537 + "Failed to setup input clk.\n"); 538 + 540 539 err = clk_prepare_enable(pltfm_host->clk); 541 540 if (err) 542 - goto free_pltfm; 541 + return err; 543 542 544 543 priv->axi_clk = devm_clk_get(&pdev->dev, "axi"); 545 544 if (IS_ERR(priv->axi_clk)) { ··· 602 603 clk_disable_unprepare(priv->axi_clk); 603 604 err_clk: 604 605 clk_disable_unprepare(pltfm_host->clk); 605 - free_pltfm: 606 - sdhci_pltfm_free(pdev); 607 606 return err; 608 607 } 609 608 ··· 620 623 xenon_sdhc_unprepare(host); 621 624 clk_disable_unprepare(priv->axi_clk); 622 625 clk_disable_unprepare(pltfm_host->clk); 623 - 624 - sdhci_pltfm_free(pdev); 625 626 } 626 627 627 628 #ifdef CONFIG_PM_SLEEP ··· 643 648 struct sdhci_host *host = dev_get_drvdata(dev); 644 649 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 645 650 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 646 - int ret; 647 651 648 - ret = sdhci_runtime_suspend_host(host); 649 - if (ret) 650 - return ret; 652 + sdhci_runtime_suspend_host(host); 651 653 652 654 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 653 655 mmc_retune_needed(host->mmc); ··· 679 687 priv->restore_needed = false; 680 688 } 681 689 682 - ret = sdhci_runtime_resume_host(host, 0); 683 - if (ret) 684 - goto out; 690 + sdhci_runtime_resume_host(host, 0); 685 691 return 0; 686 692 out: 687 693 clk_disable_unprepare(pltfm_host->clk);

+3 -14

drivers/mmc/host/sdhci.c

··· 3858 3858 3859 3859 EXPORT_SYMBOL_GPL(sdhci_resume_host); 3860 3860 3861 - int sdhci_runtime_suspend_host(struct sdhci_host *host) 3861 + void sdhci_runtime_suspend_host(struct sdhci_host *host) 3862 3862 { 3863 3863 unsigned long flags; 3864 3864 ··· 3875 3875 spin_lock_irqsave(&host->lock, flags); 3876 3876 host->runtime_suspended = true; 3877 3877 spin_unlock_irqrestore(&host->lock, flags); 3878 - 3879 - return 0; 3880 3878 } 3881 3879 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 3882 3880 3883 - int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset) 3881 + void sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset) 3884 3882 { 3885 3883 struct mmc_host *mmc = host->mmc; 3886 3884 unsigned long flags; ··· 3924 3926 sdhci_enable_card_detection(host); 3925 3927 3926 3928 spin_unlock_irqrestore(&host->lock, flags); 3927 - 3928 - return 0; 3929 3929 } 3930 3930 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 3931 3931 ··· 4067 4071 4068 4072 WARN_ON(dev == NULL); 4069 4073 4070 - mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 4074 + mmc = devm_mmc_alloc_host(dev, sizeof(struct sdhci_host) + priv_size); 4071 4075 if (!mmc) 4072 4076 return ERR_PTR(-ENOMEM); 4073 4077 ··· 4990 4994 } 4991 4995 4992 4996 EXPORT_SYMBOL_GPL(sdhci_remove_host); 4993 - 4994 - void sdhci_free_host(struct sdhci_host *host) 4995 - { 4996 - mmc_free_host(host->mmc); 4997 - } 4998 - 4999 - EXPORT_SYMBOL_GPL(sdhci_free_host); 5000 4997 5001 4998 /*****************************************************************************\ 5002 4999 * *

+2 -3

drivers/mmc/host/sdhci.h

··· 811 811 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 812 812 813 813 struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size); 814 - void sdhci_free_host(struct sdhci_host *host); 815 814 816 815 static inline void *sdhci_priv(struct sdhci_host *host) 817 816 { ··· 878 879 void sdhci_disable_irq_wakeups(struct sdhci_host *host); 879 880 int sdhci_suspend_host(struct sdhci_host *host); 880 881 int sdhci_resume_host(struct sdhci_host *host); 881 - int sdhci_runtime_suspend_host(struct sdhci_host *host); 882 - int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset); 882 + void sdhci_runtime_suspend_host(struct sdhci_host *host); 883 + void sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset); 883 884 #endif 884 885 885 886 void sdhci_cqe_enable(struct mmc_host *mmc);

+8 -21

drivers/mmc/host/sdhci_am654.c

··· 945 945 clk_xin = devm_clk_get(dev, "clk_xin"); 946 946 if (IS_ERR(clk_xin)) { 947 947 dev_err(dev, "clk_xin clock not found.\n"); 948 - ret = PTR_ERR(clk_xin); 949 - goto err_pltfm_free; 948 + return PTR_ERR(clk_xin); 950 949 } 951 950 952 951 pltfm_host->clk = clk_xin; 953 952 954 953 base = devm_platform_ioremap_resource(pdev, 1); 955 954 if (IS_ERR(base)) { 956 - ret = PTR_ERR(base); 957 - goto err_pltfm_free; 955 + return PTR_ERR(base); 958 956 } 959 957 960 958 sdhci_am654->base = devm_regmap_init_mmio(dev, base, 961 959 &sdhci_am654_regmap_config); 962 960 if (IS_ERR(sdhci_am654->base)) { 963 961 dev_err(dev, "Failed to initialize regmap\n"); 964 - ret = PTR_ERR(sdhci_am654->base); 965 - goto err_pltfm_free; 962 + return PTR_ERR(sdhci_am654->base); 966 963 } 967 964 968 965 ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 969 966 if (ret) 970 - goto err_pltfm_free; 967 + return ret; 971 968 972 969 ret = mmc_of_parse(host->mmc); 973 - if (ret) { 974 - dev_err_probe(dev, ret, "parsing dt failed\n"); 975 - goto err_pltfm_free; 976 - } 970 + if (ret) 971 + return dev_err_probe(dev, ret, "parsing dt failed\n"); 977 972 978 973 host->mmc_host_ops.start_signal_voltage_switch = sdhci_am654_start_signal_voltage_switch; 979 974 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; ··· 989 994 /* Setting up autosuspend */ 990 995 pm_runtime_set_autosuspend_delay(dev, SDHCI_AM654_AUTOSUSPEND_DELAY); 991 996 pm_runtime_use_autosuspend(dev); 992 - pm_runtime_mark_last_busy(dev); 993 997 pm_runtime_put_autosuspend(dev); 994 998 return 0; 995 999 ··· 998 1004 pm_runtime_disable(dev); 999 1005 pm_put: 1000 1006 pm_runtime_put_noidle(dev); 1001 - err_pltfm_free: 1002 - sdhci_pltfm_free(pdev); 1003 1007 return ret; 1004 1008 } 1005 1009 ··· 1016 1024 clk_disable_unprepare(pltfm_host->clk); 1017 1025 pm_runtime_disable(dev); 1018 1026 pm_runtime_put_noidle(dev); 1019 - sdhci_pltfm_free(pdev); 1020 1027 } 1021 1028 1022 1029 #ifdef CONFIG_PM ··· 1076 1085 if (ret) 1077 1086 return ret; 1078 1087 1079 - ret = sdhci_runtime_suspend_host(host); 1080 - if (ret) 1081 - return ret; 1088 + sdhci_runtime_suspend_host(host); 1082 1089 1083 1090 /* disable the clock */ 1084 1091 clk_disable_unprepare(pltfm_host->clk); ··· 1098 1109 if (ret) 1099 1110 return ret; 1100 1111 1101 - ret = sdhci_runtime_resume_host(host, 0); 1102 - if (ret) 1103 - return ret; 1112 + sdhci_runtime_resume_host(host, 0); 1104 1113 1105 1114 ret = cqhci_resume(host->mmc); 1106 1115 if (ret)

+4 -9

drivers/mmc/host/sdhci_f_sdh30.c

··· 133 133 134 134 ret = mmc_of_parse(host->mmc); 135 135 if (ret) 136 - goto err; 136 + return ret; 137 137 138 138 if (dev_of_node(dev)) { 139 139 sdhci_get_of_property(pdev); 140 140 141 141 priv->clk_iface = devm_clk_get(&pdev->dev, "iface"); 142 - if (IS_ERR(priv->clk_iface)) { 143 - ret = PTR_ERR(priv->clk_iface); 144 - goto err; 145 - } 142 + if (IS_ERR(priv->clk_iface)) 143 + return PTR_ERR(priv->clk_iface); 146 144 147 145 ret = clk_prepare_enable(priv->clk_iface); 148 146 if (ret) 149 - goto err; 147 + return ret; 150 148 151 149 priv->clk = devm_clk_get(&pdev->dev, "core"); 152 150 if (IS_ERR(priv->clk)) { ··· 198 200 clk_disable_unprepare(priv->clk); 199 201 err_clk: 200 202 clk_disable_unprepare(priv->clk_iface); 201 - err: 202 - sdhci_pltfm_free(pdev); 203 - 204 203 return ret; 205 204 } 206 205

+3 -7

drivers/mmc/host/sdricoh_cs.c

··· 403 403 } 404 404 /* allocate privdata */ 405 405 mmc = pcmcia_dev->priv = 406 - mmc_alloc_host(sizeof(struct sdricoh_host), &pcmcia_dev->dev); 406 + devm_mmc_alloc_host(&pcmcia_dev->dev, sizeof(*host)); 407 407 if (!mmc) { 408 - dev_err(dev, "mmc_alloc_host failed\n"); 408 + dev_err(dev, "devm_mmc_alloc_host failed\n"); 409 409 result = -ENOMEM; 410 410 goto unmap_io; 411 411 } ··· 431 431 if (sdricoh_reset(host)) { 432 432 dev_dbg(dev, "could not reset\n"); 433 433 result = -EIO; 434 - goto free_host; 434 + goto unmap_io; 435 435 } 436 436 437 437 result = mmc_add_host(mmc); ··· 440 440 dev_dbg(dev, "mmc host registered\n"); 441 441 return 0; 442 442 } 443 - free_host: 444 - mmc_free_host(mmc); 445 443 unmap_io: 446 444 pci_iounmap(pci_dev, iobase); 447 445 return result; ··· 481 483 mmc_remove_host(mmc); 482 484 pci_iounmap(host->pci_dev, host->iobase); 483 485 pci_dev_put(host->pci_dev); 484 - mmc_free_host(mmc); 485 486 } 486 487 pcmcia_disable_device(link); 487 - 488 488 } 489 489 490 490 #ifdef CONFIG_PM

+6 -11

drivers/mmc/host/sh_mmcif.c

··· 1444 1444 if (IS_ERR(reg)) 1445 1445 return PTR_ERR(reg); 1446 1446 1447 - mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), dev); 1447 + mmc = devm_mmc_alloc_host(dev, sizeof(*host)); 1448 1448 if (!mmc) 1449 1449 return -ENOMEM; 1450 1450 1451 1451 ret = mmc_of_parse(mmc); 1452 1452 if (ret < 0) 1453 - goto err_host; 1453 + return ret; 1454 1454 1455 1455 host = mmc_priv(mmc); 1456 1456 host->mmc = mmc; ··· 1481 1481 platform_set_drvdata(pdev, host); 1482 1482 1483 1483 host->clk = devm_clk_get(dev, NULL); 1484 - if (IS_ERR(host->clk)) { 1485 - ret = PTR_ERR(host->clk); 1486 - dev_err(dev, "cannot get clock: %d\n", ret); 1487 - goto err_host; 1488 - } 1484 + if (IS_ERR(host->clk)) 1485 + return dev_err_probe(dev, PTR_ERR(host->clk), 1486 + "cannot get clock\n"); 1489 1487 1490 1488 ret = clk_prepare_enable(host->clk); 1491 1489 if (ret < 0) 1492 - goto err_host; 1490 + return ret; 1493 1491 1494 1492 sh_mmcif_clk_setup(host); 1495 1493 ··· 1540 1542 clk_disable_unprepare(host->clk); 1541 1543 pm_runtime_put_sync(dev); 1542 1544 pm_runtime_disable(dev); 1543 - err_host: 1544 - mmc_free_host(mmc); 1545 1545 return ret; 1546 1546 } 1547 1547 ··· 1564 1568 cancel_delayed_work_sync(&host->timeout_work); 1565 1569 1566 1570 clk_disable_unprepare(host->clk); 1567 - mmc_free_host(host->mmc); 1568 1571 pm_runtime_put_sync(&pdev->dev); 1569 1572 pm_runtime_disable(&pdev->dev); 1570 1573 }

+8 -14

drivers/mmc/host/sunxi-mmc.c

··· 1369 1369 struct mmc_host *mmc; 1370 1370 int ret; 1371 1371 1372 - mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev); 1373 - if (!mmc) { 1374 - dev_err(&pdev->dev, "mmc alloc host failed\n"); 1375 - return -ENOMEM; 1376 - } 1372 + mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(*host)); 1373 + if (!mmc) 1374 + return dev_err_probe(&pdev->dev, -ENOMEM, 1375 + "mmc alloc host failed\n"); 1377 1376 platform_set_drvdata(pdev, mmc); 1378 1377 1379 1378 host = mmc_priv(mmc); ··· 1382 1383 1383 1384 ret = sunxi_mmc_resource_request(host, pdev); 1384 1385 if (ret) 1385 - goto error_free_host; 1386 + return ret; 1386 1387 1387 1388 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 1388 1389 &host->sg_dma, GFP_KERNEL); 1389 - if (!host->sg_cpu) { 1390 - dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n"); 1391 - ret = -ENOMEM; 1392 - goto error_free_host; 1393 - } 1390 + if (!host->sg_cpu) 1391 + return dev_err_probe(&pdev->dev, -ENOMEM, 1392 + "Failed to allocate DMA descriptor mem\n"); 1394 1393 1395 1394 if (host->cfg->ccu_has_timings_switch) { 1396 1395 /* ··· 1478 1481 1479 1482 error_free_dma: 1480 1483 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 1481 - error_free_host: 1482 - mmc_free_host(mmc); 1483 1484 return ret; 1484 1485 } 1485 1486 ··· 1493 1498 sunxi_mmc_disable(host); 1494 1499 } 1495 1500 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 1496 - mmc_free_host(mmc); 1497 1501 } 1498 1502 1499 1503 #ifdef CONFIG_PM

+1 -6

drivers/mmc/host/tifm_sd.c

··· 947 947 return rc; 948 948 } 949 949 950 - mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev); 950 + mmc = devm_mmc_alloc_host(&sock->dev, sizeof(*host)); 951 951 if (!mmc) 952 952 return -ENOMEM; 953 953 ··· 982 982 983 983 if (!rc) 984 984 rc = mmc_add_host(mmc); 985 - if (!rc) 986 - return 0; 987 985 988 - mmc_free_host(mmc); 989 986 return rc; 990 987 } 991 988 ··· 1012 1015 spin_unlock_irqrestore(&sock->lock, flags); 1013 1016 mmc_remove_host(mmc); 1014 1017 dev_dbg(&sock->dev, "after remove\n"); 1015 - 1016 - mmc_free_host(mmc); 1017 1018 } 1018 1019 1019 1020 #ifdef CONFIG_PM

+1 -1

drivers/mmc/host/tmio_mmc.h

··· 193 193 bool (*check_retune)(struct tmio_mmc_host *host, struct mmc_request *mrq); 194 194 void (*fixup_request)(struct tmio_mmc_host *host, struct mmc_request *mrq); 195 195 unsigned int (*get_timeout_cycles)(struct tmio_mmc_host *host); 196 + void (*sdio_irq)(struct tmio_mmc_host *host); 196 197 197 198 const struct tmio_mmc_dma_ops *dma_ops; 198 199 }; 199 200 200 201 struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev, 201 202 struct tmio_mmc_data *pdata); 202 - void tmio_mmc_host_free(struct tmio_mmc_host *host); 203 203 int tmio_mmc_host_probe(struct tmio_mmc_host *host); 204 204 void tmio_mmc_host_remove(struct tmio_mmc_host *host); 205 205 void tmio_mmc_do_data_irq(struct tmio_mmc_host *host);

+7 -17

drivers/mmc/host/tmio_mmc_core.c

··· 160 160 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask); 161 161 162 162 host->sdio_irq_enabled = false; 163 - pm_runtime_mark_last_busy(mmc_dev(mmc)); 164 163 pm_runtime_put_autosuspend(mmc_dev(mmc)); 165 164 } 166 165 } ··· 695 696 696 697 sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status); 697 698 698 - if (mmc->caps & MMC_CAP_SDIO_IRQ && ireg & TMIO_SDIO_STAT_IOIRQ) 699 + if (mmc->caps & MMC_CAP_SDIO_IRQ && ireg & TMIO_SDIO_STAT_IOIRQ) { 700 + if (host->sdio_irq) 701 + host->sdio_irq(host); 699 702 mmc_signal_sdio_irq(mmc); 703 + } 700 704 701 705 return ireg; 702 706 } ··· 1099 1097 if (IS_ERR(ctl)) 1100 1098 return ERR_CAST(ctl); 1101 1099 1102 - mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &pdev->dev); 1100 + mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(*host)); 1103 1101 if (!mmc) 1104 1102 return ERR_PTR(-ENOMEM); 1105 1103 ··· 1112 1110 mmc->ops = &host->ops; 1113 1111 1114 1112 ret = mmc_of_parse(host->mmc); 1115 - if (ret) { 1116 - host = ERR_PTR(ret); 1117 - goto free; 1118 - } 1113 + if (ret) 1114 + return ERR_PTR(ret); 1119 1115 1120 1116 tmio_mmc_of_parse(pdev, mmc); 1121 1117 1122 1118 platform_set_drvdata(pdev, host); 1123 1119 1124 1120 return host; 1125 - free: 1126 - mmc_free_host(mmc); 1127 - 1128 - return host; 1129 1121 } 1130 1122 EXPORT_SYMBOL_GPL(tmio_mmc_host_alloc); 1131 - 1132 - void tmio_mmc_host_free(struct tmio_mmc_host *host) 1133 - { 1134 - mmc_free_host(host->mmc); 1135 - } 1136 - EXPORT_SYMBOL_GPL(tmio_mmc_host_free); 1137 1123 1138 1124 int tmio_mmc_host_probe(struct tmio_mmc_host *_host) 1139 1125 {

+1 -3

drivers/mmc/host/toshsd.c

··· 612 612 if (ret) 613 613 return ret; 614 614 615 - mmc = mmc_alloc_host(sizeof(struct toshsd_host), &pdev->dev); 615 + mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(*host)); 616 616 if (!mmc) { 617 617 ret = -ENOMEM; 618 618 goto err; ··· 669 669 release: 670 670 pci_release_regions(pdev); 671 671 free: 672 - mmc_free_host(mmc); 673 672 pci_set_drvdata(pdev, NULL); 674 673 err: 675 674 pci_disable_device(pdev); ··· 684 685 free_irq(pdev->irq, host); 685 686 pci_iounmap(pdev, host->ioaddr); 686 687 pci_release_regions(pdev); 687 - mmc_free_host(host->mmc); 688 688 pci_set_drvdata(pdev, NULL); 689 689 pci_disable_device(pdev); 690 690 }

+2 -6

drivers/mmc/host/uniphier-sd.c

··· 663 663 priv->rst_hw = devm_reset_control_get_exclusive(dev, "hw"); 664 664 if (IS_ERR(priv->rst_hw)) { 665 665 dev_err(dev, "failed to get hw reset\n"); 666 - ret = PTR_ERR(priv->rst_hw); 667 - goto free_host; 666 + return PTR_ERR(priv->rst_hw); 668 667 } 669 668 host->ops.card_hw_reset = uniphier_sd_hw_reset; 670 669 } ··· 693 694 694 695 ret = uniphier_sd_clk_enable(host); 695 696 if (ret) 696 - goto free_host; 697 + return ret; 697 698 698 699 uniphier_sd_host_init(host); 699 700 ··· 719 720 720 721 disable_clk: 721 722 uniphier_sd_clk_disable(host); 722 - free_host: 723 - tmio_mmc_host_free(host); 724 723 725 724 return ret; 726 725 } ··· 729 732 730 733 tmio_mmc_host_remove(host); 731 734 uniphier_sd_clk_disable(host); 732 - tmio_mmc_host_free(host); 733 735 } 734 736 735 737 static const struct of_device_id uniphier_sd_match[] = {

+10 -20

drivers/mmc/host/usdhi6rol0.c

··· 1762 1762 if (irq_sdio < 0) 1763 1763 return irq_sdio; 1764 1764 1765 - mmc = mmc_alloc_host(sizeof(struct usdhi6_host), dev); 1765 + mmc = devm_mmc_alloc_host(dev, sizeof(*host)); 1766 1766 if (!mmc) 1767 1767 return -ENOMEM; 1768 1768 1769 1769 ret = mmc_regulator_get_supply(mmc); 1770 1770 if (ret) 1771 - goto e_free_mmc; 1771 + return ret; 1772 1772 1773 1773 ret = mmc_of_parse(mmc); 1774 1774 if (ret < 0) 1775 - goto e_free_mmc; 1775 + return ret; 1776 1776 1777 1777 host = mmc_priv(mmc); 1778 1778 host->mmc = mmc; ··· 1785 1785 mmc->max_busy_timeout = USDHI6_REQ_TIMEOUT_MS; 1786 1786 1787 1787 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1788 - if (IS_ERR(host->pinctrl)) { 1789 - ret = PTR_ERR(host->pinctrl); 1790 - goto e_free_mmc; 1791 - } 1788 + if (IS_ERR(host->pinctrl)) 1789 + return PTR_ERR(host->pinctrl); 1792 1790 1793 1791 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 1794 1792 1795 1793 host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1796 - if (IS_ERR(host->base)) { 1797 - ret = PTR_ERR(host->base); 1798 - goto e_free_mmc; 1799 - } 1794 + if (IS_ERR(host->base)) 1795 + return PTR_ERR(host->base); 1800 1796 1801 1797 host->clk = devm_clk_get(dev, NULL); 1802 - if (IS_ERR(host->clk)) { 1803 - ret = PTR_ERR(host->clk); 1804 - goto e_free_mmc; 1805 - } 1798 + if (IS_ERR(host->clk)) 1799 + return PTR_ERR(host->clk); 1806 1800 1807 1801 host->imclk = clk_get_rate(host->clk); 1808 1802 1809 1803 ret = clk_prepare_enable(host->clk); 1810 1804 if (ret < 0) 1811 - goto e_free_mmc; 1805 + return ret; 1812 1806 1813 1807 version = usdhi6_read(host, USDHI6_VERSION); 1814 1808 if ((version & 0xfff) != 0xa0d) { ··· 1872 1878 usdhi6_dma_release(host); 1873 1879 e_clk_off: 1874 1880 clk_disable_unprepare(host->clk); 1875 - e_free_mmc: 1876 - mmc_free_host(mmc); 1877 - 1878 1881 return ret; 1879 1882 } 1880 1883 ··· 1885 1894 cancel_delayed_work_sync(&host->timeout_work); 1886 1895 usdhi6_dma_release(host); 1887 1896 clk_disable_unprepare(host->clk); 1888 - mmc_free_host(host->mmc); 1889 1897 } 1890 1898 1891 1899 static struct platform_driver usdhi6_driver = {

+1 -3

drivers/mmc/host/ushc.c

··· 404 404 kfree(ushc->int_data); 405 405 kfree(ushc->cbw); 406 406 kfree(ushc->csw); 407 - 408 - mmc_free_host(ushc->mmc); 409 407 } 410 408 411 409 static const struct mmc_host_ops ushc_ops = { ··· 423 425 if (intf->cur_altsetting->desc.bNumEndpoints < 1) 424 426 return -ENODEV; 425 427 426 - mmc = mmc_alloc_host(sizeof(struct ushc_data), &intf->dev); 428 + mmc = devm_mmc_alloc_host(&intf->dev, sizeof(*ushc)); 427 429 if (mmc == NULL) 428 430 return -ENOMEM; 429 431 ushc = mmc_priv(mmc);

+2 -5

drivers/mmc/host/via-sdmmc.c

··· 1100 1100 pci_write_config_byte(pcidev, VIA_CRDR_PCI_WORK_MODE, 0); 1101 1101 pci_write_config_byte(pcidev, VIA_CRDR_PCI_DBG_MODE, 0); 1102 1102 1103 - mmc = mmc_alloc_host(sizeof(struct via_crdr_mmc_host), &pcidev->dev); 1103 + mmc = devm_mmc_alloc_host(&pcidev->dev, sizeof(*sdhost)); 1104 1104 if (!mmc) { 1105 1105 ret = -ENOMEM; 1106 1106 goto release; ··· 1115 1115 sdhost->mmiobase = ioremap(base, len); 1116 1116 if (!sdhost->mmiobase) { 1117 1117 ret = -ENOMEM; 1118 - goto free_mmc_host; 1118 + goto release; 1119 1119 } 1120 1120 1121 1121 sdhost->sdhc_mmiobase = ··· 1160 1160 1161 1161 unmap: 1162 1162 iounmap(sdhost->mmiobase); 1163 - free_mmc_host: 1164 - mmc_free_host(mmc); 1165 1163 release: 1166 1164 pci_release_regions(pcidev); 1167 1165 disable: ··· 1210 1212 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1211 1213 1212 1214 iounmap(sdhost->mmiobase); 1213 - mmc_free_host(sdhost->mmc); 1214 1215 pci_release_regions(pcidev); 1215 1216 pci_disable_device(pcidev); 1216 1217

+6 -10

drivers/mmc/host/vub300.c

··· 369 369 static void vub300_delete(struct kref *kref) 370 370 { /* kref callback - softirq */ 371 371 struct vub300_mmc_host *vub300 = kref_to_vub300_mmc_host(kref); 372 - struct mmc_host *mmc = vub300->mmc; 373 372 usb_free_urb(vub300->command_out_urb); 374 373 vub300->command_out_urb = NULL; 375 374 usb_free_urb(vub300->command_res_urb); 376 375 vub300->command_res_urb = NULL; 377 376 usb_put_dev(vub300->udev); 378 - mmc_free_host(mmc); 379 377 /* 380 378 * and hence also frees vub300 381 379 * which is contained at the end of struct mmc ··· 2112 2114 goto error1; 2113 2115 } 2114 2116 /* this also allocates memory for our VUB300 mmc host device */ 2115 - mmc = mmc_alloc_host(sizeof(struct vub300_mmc_host), &udev->dev); 2117 + mmc = devm_mmc_alloc_host(&udev->dev, sizeof(*vub300)); 2116 2118 if (!mmc) { 2117 2119 retval = -ENOMEM; 2118 2120 dev_err(&udev->dev, "not enough memory for the mmc_host\n"); ··· 2269 2271 dev_err(&vub300->udev->dev, 2270 2272 "Could not find two sets of bulk-in/out endpoint pairs\n"); 2271 2273 retval = -EINVAL; 2272 - goto error5; 2274 + goto error4; 2273 2275 } 2274 2276 retval = 2275 2277 usb_control_msg(vub300->udev, usb_rcvctrlpipe(vub300->udev, 0), ··· 2278 2280 0x0000, 0x0000, &vub300->hc_info, 2279 2281 sizeof(vub300->hc_info), 1000); 2280 2282 if (retval < 0) 2281 - goto error5; 2283 + goto error4; 2282 2284 retval = 2283 2285 usb_control_msg(vub300->udev, usb_sndctrlpipe(vub300->udev, 0), 2284 2286 SET_ROM_WAIT_STATES, 2285 2287 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 2286 2288 firmware_rom_wait_states, 0x0000, NULL, 0, 1000); 2287 2289 if (retval < 0) 2288 - goto error5; 2290 + goto error4; 2289 2291 dev_info(&vub300->udev->dev, 2290 2292 "operating_mode = %s %s %d MHz %s %d byte USB packets\n", 2291 2293 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "IRQs" : "POLL", ··· 2300 2302 0x0000, 0x0000, &vub300->system_port_status, 2301 2303 sizeof(vub300->system_port_status), 1000); 2302 2304 if (retval < 0) { 2303 - goto error5; 2305 + goto error4; 2304 2306 } else if (sizeof(vub300->system_port_status) == retval) { 2305 2307 vub300->card_present = 2306 2308 (0x0001 & vub300->system_port_status.port_flags) ? 1 : 0; ··· 2308 2310 (0x0010 & vub300->system_port_status.port_flags) ? 1 : 0; 2309 2311 } else { 2310 2312 retval = -EINVAL; 2311 - goto error5; 2313 + goto error4; 2312 2314 } 2313 2315 usb_set_intfdata(interface, vub300); 2314 2316 INIT_DELAYED_WORK(&vub300->pollwork, vub300_pollwork_thread); ··· 2338 2340 return 0; 2339 2341 error6: 2340 2342 timer_delete_sync(&vub300->inactivity_timer); 2341 - error5: 2342 - mmc_free_host(mmc); 2343 2343 /* 2344 2344 * and hence also frees vub300 2345 2345 * which is contained at the end of struct mmc

+1 -3

drivers/mmc/host/wbsd.c

··· 1190 1190 /* 1191 1191 * Allocate MMC structure. 1192 1192 */ 1193 - mmc = mmc_alloc_host(sizeof(struct wbsd_host), dev); 1193 + mmc = devm_mmc_alloc_host(dev, sizeof(*host)); 1194 1194 if (!mmc) 1195 1195 return -ENOMEM; 1196 1196 ··· 1262 1262 BUG_ON(host == NULL); 1263 1263 1264 1264 timer_delete_sync(&host->ignore_timer); 1265 - 1266 - mmc_free_host(mmc); 1267 1265 } 1268 1266 1269 1267 /*

+2 -6

drivers/mmc/host/wmt-sdmmc.c

··· 774 774 goto fail1; 775 775 } 776 776 777 - mmc = mmc_alloc_host(sizeof(struct wmt_mci_priv), &pdev->dev); 777 + mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(*priv)); 778 778 if (!mmc) { 779 779 dev_err(&pdev->dev, "Failed to allocate mmc_host\n"); 780 780 ret = -ENOMEM; ··· 808 808 if (!priv->sdmmc_base) { 809 809 dev_err(&pdev->dev, "Failed to map IO space\n"); 810 810 ret = -ENOMEM; 811 - goto fail2; 811 + goto fail1; 812 812 } 813 813 814 814 priv->irq_regular = regular_irq; ··· 873 873 free_irq(regular_irq, priv); 874 874 fail3: 875 875 iounmap(priv->sdmmc_base); 876 - fail2: 877 - mmc_free_host(mmc); 878 876 fail1: 879 877 return ret; 880 878 } ··· 907 909 908 910 clk_disable_unprepare(priv->clk_sdmmc); 909 911 clk_put(priv->clk_sdmmc); 910 - 911 - mmc_free_host(mmc); 912 912 913 913 dev_info(&pdev->dev, "WMT MCI device removed\n"); 914 914 }

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