+2

Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt

reviewed

··· 15 15 "mediatek,mt8173-i2c": for MediaTek MT8173 16 16 "mediatek,mt8183-i2c": for MediaTek MT8183 17 17 "mediatek,mt8192-i2c": for MediaTek MT8192 18 18 + "mediatek,mt8195-i2c", "mediatek,mt8192-i2c": for MediaTek MT8195 18 19 "mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516 19 20 - reg: physical base address of the controller and dma base, length of memory 20 21 mapped region. ··· 33 32 - mediatek,have-pmic: platform can control i2c form special pmic side. 34 33 Only mt6589 and mt8135 support this feature. 35 34 - mediatek,use-push-pull: IO config use push-pull mode. 35 35 + - vbus-supply: phandle to the regulator that provides power to SCL/SDA. 36 36 37 37 Example: 38 38

-1

Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt

reviewed

··· 62 62 reg = <0x3c>; 63 63 pwms = <&pwm 4 3000>; 64 64 reset-gpios = <&gpio2 7 1>; 65 65 - reset-active-low; 66 65 }; 67 66 }; 68 67

-37

Documentation/devicetree/bindings/i2c/i2c-omap.txt

reviewed

··· 1 1 - I2C for OMAP platforms 2 2 - 3 3 - Required properties : 4 4 - - compatible : Must be 5 5 - "ti,omap2420-i2c" for OMAP2420 SoCs 6 6 - "ti,omap2430-i2c" for OMAP2430 SoCs 7 7 - "ti,omap3-i2c" for OMAP3 SoCs 8 8 - "ti,omap4-i2c" for OMAP4+ SoCs 9 9 - "ti,am654-i2c", "ti,omap4-i2c" for AM654 SoCs 10 10 - "ti,j721e-i2c", "ti,omap4-i2c" for J721E SoCs 11 11 - "ti,am64-i2c", "ti,omap4-i2c" for AM64 SoCs 12 12 - - ti,hwmods : Must be "i2c<n>", n being the instance number (1-based) 13 13 - - #address-cells = <1>; 14 14 - - #size-cells = <0>; 15 15 - 16 16 - Recommended properties : 17 17 - - clock-frequency : Desired I2C bus clock frequency in Hz. Otherwise 18 18 - the default 100 kHz frequency will be used. 19 19 - 20 20 - Optional properties: 21 21 - - Child nodes conforming to i2c bus binding 22 22 - 23 23 - Note: Current implementation will fetch base address, irq and dma 24 24 - from omap hwmod data base during device registration. 25 25 - Future plan is to migrate hwmod data base contents into device tree 26 26 - blob so that, all the required data will be used from device tree dts 27 27 - file. 28 28 - 29 29 - Examples : 30 30 - 31 31 - i2c1: i2c@0 { 32 32 - compatible = "ti,omap3-i2c"; 33 33 - #address-cells = <1>; 34 34 - #size-cells = <0>; 35 35 - ti,hwmods = "i2c1"; 36 36 - clock-frequency = <400000>; 37 37 - };

+2 -2

Documentation/devicetree/bindings/i2c/i2c-pxa-pci-ce4100.txt

reviewed

··· 71 71 /* This I2C controller has one gpio controller */ 72 72 gpio@26 { 73 73 #gpio-cells = <2>; 74 74 - compatible = "ti,pcf8575"; 74 74 + compatible = "nxp,pcf8575"; 75 75 reg = <0x26>; 76 76 gpio-controller; 77 77 }; ··· 85 85 86 86 gpio@26 { 87 87 #gpio-cells = <2>; 88 88 - compatible = "ti,pcf8575"; 88 88 + compatible = "nxp,pcf8575"; 89 89 reg = <0x26>; 90 90 gpio-controller; 91 91 };

+3 -2

Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt

reviewed

··· 9 9 "qcom,msm8916-cci" 10 10 "qcom,msm8996-cci" 11 11 "qcom,sdm845-cci" 12 12 + "qcom,sm8250-cci" 12 13 13 14 - reg 14 15 Usage: required ··· 42 41 43 42 SUBNODES: 44 43 45 45 - The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996 and 46 46 - sdm845), described as subdevices named "i2c-bus@0" and "i2c-bus@1". 44 44 + The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996, 45 45 + sdm845 and sm8250), described as subdevices named "i2c-bus@0" and "i2c-bus@1". 47 46 48 47 PROPERTIES: 49 48

+1

Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml

reviewed

··· 36 36 - rockchip,px30-i2c 37 37 - rockchip,rk3308-i2c 38 38 - rockchip,rk3328-i2c 39 39 + - rockchip,rk3568-i2c 39 40 - const: rockchip,rk3399-i2c 40 41 41 42 reg:

+5 -2

Documentation/devicetree/bindings/i2c/i2c.txt

reviewed

··· 89 89 90 90 - smbus 91 91 states that additional SMBus restrictions and features apply to this bus. 92 92 - Examples of features are SMBusHostNotify and SMBusAlert. Examples of 93 93 - restrictions are more reserved addresses and timeout definitions. 92 92 + An example of feature is SMBusHostNotify. Examples of restrictions are 93 93 + more reserved addresses and timeout definitions. 94 94 + 95 95 + - smbus-alert 96 96 + states that the optional SMBus-Alert feature apply to this bus. 94 97 95 98 Required properties (per child device) 96 99 --------------------------------------

-67

Documentation/devicetree/bindings/i2c/renesas,i2c.txt

reviewed

··· 1 1 - I2C for R-Car platforms 2 2 - 3 3 - Required properties: 4 4 - - compatible: 5 5 - "renesas,i2c-r8a7742" if the device is a part of a R8A7742 SoC. 6 6 - "renesas,i2c-r8a7743" if the device is a part of a R8A7743 SoC. 7 7 - "renesas,i2c-r8a7744" if the device is a part of a R8A7744 SoC. 8 8 - "renesas,i2c-r8a7745" if the device is a part of a R8A7745 SoC. 9 9 - "renesas,i2c-r8a77470" if the device is a part of a R8A77470 SoC. 10 10 - "renesas,i2c-r8a774a1" if the device is a part of a R8A774A1 SoC. 11 11 - "renesas,i2c-r8a774b1" if the device is a part of a R8A774B1 SoC. 12 12 - "renesas,i2c-r8a774c0" if the device is a part of a R8A774C0 SoC. 13 13 - "renesas,i2c-r8a774e1" if the device is a part of a R8A774E1 SoC. 14 14 - "renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC. 15 15 - "renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC. 16 16 - "renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC. 17 17 - "renesas,i2c-r8a7791" if the device is a part of a R8A7791 SoC. 18 18 - "renesas,i2c-r8a7792" if the device is a part of a R8A7792 SoC. 19 19 - "renesas,i2c-r8a7793" if the device is a part of a R8A7793 SoC. 20 20 - "renesas,i2c-r8a7794" if the device is a part of a R8A7794 SoC. 21 21 - "renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC. 22 22 - "renesas,i2c-r8a7796" if the device is a part of a R8A77960 SoC. 23 23 - "renesas,i2c-r8a77961" if the device is a part of a R8A77961 SoC. 24 24 - "renesas,i2c-r8a77965" if the device is a part of a R8A77965 SoC. 25 25 - "renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC. 26 26 - "renesas,i2c-r8a77980" if the device is a part of a R8A77980 SoC. 27 27 - "renesas,i2c-r8a77990" if the device is a part of a R8A77990 SoC. 28 28 - "renesas,i2c-r8a77995" if the device is a part of a R8A77995 SoC. 29 29 - "renesas,i2c-r8a779a0" if the device is a part of a R8A779A0 SoC. 30 30 - "renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device. 31 31 - "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible 32 32 - device. 33 33 - "renesas,rcar-gen3-i2c" for a generic R-Car Gen3 or RZ/G2 compatible 34 34 - device. 35 35 - "renesas,i2c-rcar" (deprecated) 36 36 - 37 37 - When compatible with the generic version, nodes must list the 38 38 - SoC-specific version corresponding to the platform first followed 39 39 - by the generic version. 40 40 - 41 41 - - reg: physical base address of the controller and length of memory mapped 42 42 - region. 43 43 - - interrupts: interrupt specifier. 44 44 - 45 45 - Optional properties: 46 46 - - clock-frequency: desired I2C bus clock frequency in Hz. The absence of this 47 47 - property indicates the default frequency 100 kHz. 48 48 - - clocks: clock specifier. 49 49 - - dmas: Must contain a list of two references to DMA specifiers, one for 50 50 - transmission, and one for reception. 51 51 - - dma-names: Must contain a list of two DMA names, "tx" and "rx". 52 52 - 53 53 - - i2c-scl-falling-time-ns: see i2c.txt 54 54 - - i2c-scl-internal-delay-ns: see i2c.txt 55 55 - - i2c-scl-rising-time-ns: see i2c.txt 56 56 - 57 57 - Examples : 58 58 - 59 59 - i2c0: i2c@e6508000 { 60 60 - #address-cells = <1>; 61 61 - #size-cells = <0>; 62 62 - compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; 63 63 - reg = <0 0xe6508000 0 0x40>; 64 64 - interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; 65 65 - clocks = <&mstp9_clks R8A7791_CLK_I2C0>; 66 66 - clock-frequency = <400000>; 67 67 - };

-22

Documentation/devicetree/bindings/i2c/renesas,iic-emev2.txt

reviewed

··· 1 1 - Device tree configuration for Renesas EMEV2 IIC controller 2 2 - 3 3 - Required properties: 4 4 - - compatible : "renesas,iic-emev2" 5 5 - - reg : address start and address range size of device 6 6 - - interrupts : specifier for the IIC controller interrupt 7 7 - - clocks : phandle to the IP core SCLK 8 8 - - clock-names : must be "sclk" 9 9 - - #address-cells : should be <1> 10 10 - - #size-cells : should be <0> 11 11 - 12 12 - Example: 13 13 - 14 14 - iic0: i2c@e0070000 { 15 15 - #address-cells = <1>; 16 16 - #size-cells = <0>; 17 17 - compatible = "renesas,iic-emev2"; 18 18 - reg = <0xe0070000 0x28>; 19 19 - interrupts = <0 32 IRQ_TYPE_EDGE_RISING>; 20 20 - clocks = <&iic0_sclk>; 21 21 - clock-names = "sclk"; 22 22 - };

+54

Documentation/devicetree/bindings/i2c/renesas,iic-emev2.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/i2c/renesas,iic-emev2.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Renesas EMMA Mobile EV2 IIC Interface 8 8 + 9 9 + maintainers: 10 10 + - Wolfram Sang <wsa+renesas@sang-engineering.com> 11 11 + 12 12 + allOf: 13 13 + - $ref: /schemas/i2c/i2c-controller.yaml# 14 14 + 15 15 + properties: 16 16 + compatible: 17 17 + const: renesas,iic-emev2 18 18 + 19 19 + reg: 20 20 + maxItems: 1 21 21 + 22 22 + interrupts: 23 23 + maxItems: 1 24 24 + 25 25 + clocks: 26 26 + maxItems: 1 27 27 + 28 28 + clock-names: 29 29 + const: sclk 30 30 + 31 31 + required: 32 32 + - compatible 33 33 + - reg 34 34 + - interrupts 35 35 + - clocks 36 36 + - clock-names 37 37 + - '#address-cells' 38 38 + - '#size-cells' 39 39 + 40 40 + unevaluatedProperties: false 41 41 + 42 42 + examples: 43 43 + - | 44 44 + #include <dt-bindings/interrupt-controller/arm-gic.h> 45 45 + 46 46 + iic0: i2c@e0070000 { 47 47 + #address-cells = <1>; 48 48 + #size-cells = <0>; 49 49 + compatible = "renesas,iic-emev2"; 50 50 + reg = <0xe0070000 0x28>; 51 51 + interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; 52 52 + clocks = <&iic0_sclk>; 53 53 + clock-names = "sclk"; 54 54 + };

-72

Documentation/devicetree/bindings/i2c/renesas,iic.txt

reviewed

··· 1 1 - Device tree configuration for Renesas IIC (sh_mobile) driver 2 2 - 3 3 - Required properties: 4 4 - - compatible : 5 5 - - "renesas,iic-r8a73a4" (R-Mobile APE6) 6 6 - - "renesas,iic-r8a7740" (R-Mobile A1) 7 7 - - "renesas,iic-r8a7742" (RZ/G1H) 8 8 - - "renesas,iic-r8a7743" (RZ/G1M) 9 9 - - "renesas,iic-r8a7744" (RZ/G1N) 10 10 - - "renesas,iic-r8a7745" (RZ/G1E) 11 11 - - "renesas,iic-r8a774a1" (RZ/G2M) 12 12 - - "renesas,iic-r8a774b1" (RZ/G2N) 13 13 - - "renesas,iic-r8a774c0" (RZ/G2E) 14 14 - - "renesas,iic-r8a774e1" (RZ/G2H) 15 15 - - "renesas,iic-r8a7790" (R-Car H2) 16 16 - - "renesas,iic-r8a7791" (R-Car M2-W) 17 17 - - "renesas,iic-r8a7792" (R-Car V2H) 18 18 - - "renesas,iic-r8a7793" (R-Car M2-N) 19 19 - - "renesas,iic-r8a7794" (R-Car E2) 20 20 - - "renesas,iic-r8a7795" (R-Car H3) 21 21 - - "renesas,iic-r8a7796" (R-Car M3-W) 22 22 - - "renesas,iic-r8a77961" (R-Car M3-W+) 23 23 - - "renesas,iic-r8a77965" (R-Car M3-N) 24 24 - - "renesas,iic-r8a77990" (R-Car E3) 25 25 - - "renesas,iic-sh73a0" (SH-Mobile AG5) 26 26 - - "renesas,rcar-gen2-iic" (generic R-Car Gen2 or RZ/G1 27 27 - compatible device) 28 28 - - "renesas,rcar-gen3-iic" (generic R-Car Gen3 or RZ/G2 29 29 - compatible device) 30 30 - - "renesas,rmobile-iic" (generic device) 31 31 - 32 32 - When compatible with a generic R-Car version, nodes 33 33 - must list the SoC-specific version corresponding to 34 34 - the platform first followed by the generic R-Car 35 35 - version. 36 36 - 37 37 - When compatible with "renesas,rmobile-iic" it should 38 38 - be the last compatibility string listed. 39 39 - 40 40 - The r8a77990 (R-Car E3) and r8a774c0 (RZ/G2E) 41 41 - controllers are not considered compatible with 42 42 - "renesas,rcar-gen3-iic" or "renesas,rmobile-iic" 43 43 - due to the absence of automatic transmission registers. 44 44 - 45 45 - - reg : address start and address range size of device 46 46 - - interrupts : interrupt of device 47 47 - - clocks : clock for device 48 48 - - #address-cells : should be <1> 49 49 - - #size-cells : should be <0> 50 50 - 51 51 - Optional properties: 52 52 - - clock-frequency : frequency of bus clock in Hz. Default 100kHz if unset. 53 53 - - dmas : Must contain a list of two references to DMA 54 54 - specifiers, one for transmission, and one for 55 55 - reception. 56 56 - - dma-names : Must contain a list of two DMA names, "tx" and "rx". 57 57 - 58 58 - 59 59 - Pinctrl properties might be needed, too. See there. 60 60 - 61 61 - Example: 62 62 - 63 63 - iic0: i2c@e6500000 { 64 64 - compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic", 65 65 - "renesas,rmobile-iic"; 66 66 - reg = <0 0xe6500000 0 0x425>; 67 67 - interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; 68 68 - clocks = <&mstp3_clks R8A7790_CLK_IIC0>; 69 69 - clock-frequency = <400000>; 70 70 - #address-cells = <1>; 71 71 - #size-cells = <0>; 72 72 - };

+158

Documentation/devicetree/bindings/i2c/renesas,rcar-i2c.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/i2c/renesas,rcar-i2c.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Renesas R-Car I2C Controller 8 8 + 9 9 + maintainers: 10 10 + - Wolfram Sang <wsa+renesas@sang-engineering.com> 11 11 + 12 12 + properties: 13 13 + compatible: 14 14 + oneOf: 15 15 + - items: 16 16 + - enum: 17 17 + - renesas,i2c-r8a7778 # R-Car M1A 18 18 + - renesas,i2c-r8a7779 # R-Car H1 19 19 + - const: renesas,rcar-gen1-i2c # R-Car Gen1 20 20 + 21 21 + - items: 22 22 + - enum: 23 23 + - renesas,i2c-r8a7742 # RZ/G1H 24 24 + - renesas,i2c-r8a7743 # RZ/G1M 25 25 + - renesas,i2c-r8a7744 # RZ/G1N 26 26 + - renesas,i2c-r8a7745 # RZ/G1E 27 27 + - renesas,i2c-r8a77470 # RZ/G1C 28 28 + - renesas,i2c-r8a7790 # R-Car H2 29 29 + - renesas,i2c-r8a7791 # R-Car M2-W 30 30 + - renesas,i2c-r8a7792 # R-Car V2H 31 31 + - renesas,i2c-r8a7793 # R-Car M2-N 32 32 + - renesas,i2c-r8a7794 # R-Car E2 33 33 + - const: renesas,rcar-gen2-i2c # R-Car Gen2 and RZ/G1 34 34 + 35 35 + - items: 36 36 + - enum: 37 37 + - renesas,i2c-r8a774a1 # RZ/G2M 38 38 + - renesas,i2c-r8a774b1 # RZ/G2N 39 39 + - renesas,i2c-r8a774c0 # RZ/G2E 40 40 + - renesas,i2c-r8a774e1 # RZ/G2H 41 41 + - renesas,i2c-r8a7795 # R-Car H3 42 42 + - renesas,i2c-r8a7796 # R-Car M3-W 43 43 + - renesas,i2c-r8a77961 # R-Car M3-W+ 44 44 + - renesas,i2c-r8a77965 # R-Car M3-N 45 45 + - renesas,i2c-r8a77970 # R-Car V3M 46 46 + - renesas,i2c-r8a77980 # R-Car V3H 47 47 + - renesas,i2c-r8a77990 # R-Car E3 48 48 + - renesas,i2c-r8a77995 # R-Car D3 49 49 + - renesas,i2c-r8a779a0 # R-Car V3U 50 50 + - const: renesas,rcar-gen3-i2c # R-Car Gen3 and RZ/G2 51 51 + 52 52 + reg: 53 53 + maxItems: 1 54 54 + 55 55 + interrupts: 56 56 + maxItems: 1 57 57 + 58 58 + clock-frequency: 59 59 + description: 60 60 + Desired I2C bus clock frequency in Hz. The absence of this property 61 61 + indicates the default frequency 100 kHz. 62 62 + 63 63 + clocks: 64 64 + maxItems: 1 65 65 + 66 66 + power-domains: 67 67 + maxItems: 1 68 68 + 69 69 + resets: 70 70 + maxItems: 1 71 71 + 72 72 + dmas: 73 73 + minItems: 2 74 74 + maxItems: 4 75 75 + description: 76 76 + Must contain a list of pairs of references to DMA specifiers, one for 77 77 + transmission, and one for reception. 78 78 + 79 79 + dma-names: 80 80 + minItems: 2 81 81 + maxItems: 4 82 82 + items: 83 83 + enum: 84 84 + - tx 85 85 + - rx 86 86 + 87 87 + i2c-scl-falling-time-ns: 88 88 + default: 35 89 89 + description: 90 90 + Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C 91 91 + specification. 92 92 + 93 93 + i2c-scl-internal-delay-ns: 94 94 + default: 50 95 95 + description: 96 96 + Number of nanoseconds the IP core additionally needs to setup SCL. 97 97 + 98 98 + i2c-scl-rising-time-ns: 99 99 + default: 200 100 100 + description: 101 101 + Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C 102 102 + specification. 103 103 + 104 104 + required: 105 105 + - compatible 106 106 + - reg 107 107 + - interrupts 108 108 + - clocks 109 109 + - power-domains 110 110 + - '#address-cells' 111 111 + - '#size-cells' 112 112 + 113 113 + allOf: 114 114 + - $ref: /schemas/i2c/i2c-controller.yaml# 115 115 + 116 116 + - if: 117 117 + properties: 118 118 + compatible: 119 119 + contains: 120 120 + enum: 121 121 + - renesas,rcar-gen1-i2c 122 122 + - renesas,rcar-gen2-i2c 123 123 + then: 124 124 + properties: 125 125 + dmas: false 126 126 + dma-names: false 127 127 + 128 128 + - if: 129 129 + properties: 130 130 + compatible: 131 131 + contains: 132 132 + enum: 133 133 + - renesas,rcar-gen2-i2c 134 134 + - renesas,rcar-gen3-i2c 135 135 + then: 136 136 + required: 137 137 + - resets 138 138 + 139 139 + unevaluatedProperties: false 140 140 + 141 141 + examples: 142 142 + - | 143 143 + #include <dt-bindings/clock/r8a7791-cpg-mssr.h> 144 144 + #include <dt-bindings/interrupt-controller/arm-gic.h> 145 145 + #include <dt-bindings/power/r8a7791-sysc.h> 146 146 + 147 147 + i2c0: i2c@e6508000 { 148 148 + #address-cells = <1>; 149 149 + #size-cells = <0>; 150 150 + compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; 151 151 + reg = <0xe6508000 0x40>; 152 152 + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 153 153 + clock-frequency = <400000>; 154 154 + clocks = <&cpg CPG_MOD 931>; 155 155 + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 156 156 + resets = <&cpg 931>; 157 157 + i2c-scl-internal-delay-ns = <6>; 158 158 + };

-32

Documentation/devicetree/bindings/i2c/renesas,riic.txt

reviewed

··· 1 1 - Device tree configuration for Renesas RIIC driver 2 2 - 3 3 - Required properties: 4 4 - - compatible : 5 5 - "renesas,riic-r7s72100" if the device is a part of a R7S72100 SoC. 6 6 - "renesas,riic-r7s9210" if the device is a part of a R7S9210 SoC. 7 7 - "renesas,riic-rz" for a generic RZ/A compatible device. 8 8 - - reg : address start and address range size of device 9 9 - - interrupts : 8 interrupts (TEI, RI, TI, SPI, STI, NAKI, ALI, TMOI) 10 10 - - clock-frequency : frequency of bus clock in Hz 11 11 - - #address-cells : should be <1> 12 12 - - #size-cells : should be <0> 13 13 - 14 14 - Pinctrl properties might be needed, too. See there. 15 15 - 16 16 - Example: 17 17 - 18 18 - i2c0: i2c@fcfee000 { 19 19 - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 20 20 - reg = <0xfcfee000 0x44>; 21 21 - interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>, 22 22 - <0 158 IRQ_TYPE_EDGE_RISING>, 23 23 - <0 159 IRQ_TYPE_EDGE_RISING>, 24 24 - <0 160 IRQ_TYPE_LEVEL_HIGH>, 25 25 - <0 161 IRQ_TYPE_LEVEL_HIGH>, 26 26 - <0 162 IRQ_TYPE_LEVEL_HIGH>, 27 27 - <0 163 IRQ_TYPE_LEVEL_HIGH>, 28 28 - <0 164 IRQ_TYPE_LEVEL_HIGH>; 29 29 - clock-frequency = <100000>; 30 30 - #address-cells = <1>; 31 31 - #size-cells = <0>; 32 32 - };

+93

Documentation/devicetree/bindings/i2c/renesas,riic.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/i2c/renesas,riic.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Renesas RZ/A and RZ/G2L I2C Bus Interface (RIIC) 8 8 + 9 9 + maintainers: 10 10 + - Chris Brandt <chris.brandt@renesas.com> 11 11 + - Wolfram Sang <wsa+renesas@sang-engineering.com> 12 12 + 13 13 + allOf: 14 14 + - $ref: /schemas/i2c/i2c-controller.yaml# 15 15 + 16 16 + properties: 17 17 + compatible: 18 18 + items: 19 19 + - enum: 20 20 + - renesas,riic-r7s72100 # RZ/A1H 21 21 + - renesas,riic-r7s9210 # RZ/A2M 22 22 + - renesas,riic-r9a07g044 # RZ/G2{L,LC} 23 23 + - const: renesas,riic-rz # RZ/A or RZ/G2L 24 24 + 25 25 + reg: 26 26 + maxItems: 1 27 27 + 28 28 + interrupts: 29 29 + items: 30 30 + - description: Transmit End Interrupt (TEI) 31 31 + - description: Receive Data Full Interrupt (RI) 32 32 + - description: Transmit Data Empty Interrupt (TI) 33 33 + - description: Stop Condition Detection Interrupt (SPI) 34 34 + - description: Start Condition Detection Interrupt (STI) 35 35 + - description: NACK Reception Interrupt (NAKI) 36 36 + - description: Arbitration-Lost Interrupt (ALI) 37 37 + - description: Timeout Interrupt (TMOI) 38 38 + 39 39 + clock-frequency: 40 40 + description: 41 41 + Desired I2C bus clock frequency in Hz. The absence of this property 42 42 + indicates the default frequency 100 kHz. 43 43 + 44 44 + clocks: 45 45 + maxItems: 1 46 46 + 47 47 + power-domains: 48 48 + maxItems: 1 49 49 + 50 50 + required: 51 51 + - compatible 52 52 + - reg 53 53 + - interrupts 54 54 + - clocks 55 55 + - clock-frequency 56 56 + - power-domains 57 57 + - '#address-cells' 58 58 + - '#size-cells' 59 59 + 60 60 + if: 61 61 + properties: 62 62 + compatible: 63 63 + contains: 64 64 + enum: 65 65 + - renesas,riic-r9a07g044 66 66 + then: 67 67 + required: 68 68 + - resets 69 69 + 70 70 + unevaluatedProperties: false 71 71 + 72 72 + examples: 73 73 + - | 74 74 + #include <dt-bindings/clock/r7s72100-clock.h> 75 75 + #include <dt-bindings/interrupt-controller/arm-gic.h> 76 76 + 77 77 + i2c0: i2c@fcfee000 { 78 78 + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 79 79 + reg = <0xfcfee000 0x44>; 80 80 + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 81 81 + <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, 82 82 + <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>, 83 83 + <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 84 84 + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 85 85 + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 86 86 + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 87 87 + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 88 88 + clocks = <&mstp9_clks R7S72100_CLK_I2C0>; 89 89 + clock-frequency = <100000>; 90 90 + power-domains = <&cpg_clocks>; 91 91 + #address-cells = <1>; 92 92 + #size-cells = <0>; 93 93 + };

+149

Documentation/devicetree/bindings/i2c/renesas,rmobile-iic.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/i2c/renesas,rmobile-iic.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Renesas R-Mobile I2C Bus Interface (IIC) 8 8 + 9 9 + maintainers: 10 10 + - Wolfram Sang <wsa+renesas@sang-engineering.com> 11 11 + 12 12 + properties: 13 13 + compatible: 14 14 + oneOf: 15 15 + - items: 16 16 + - enum: 17 17 + - renesas,iic-r8a73a4 # R-Mobile APE6 18 18 + - renesas,iic-r8a7740 # R-Mobile A1 19 19 + - renesas,iic-sh73a0 # SH-Mobile AG5 20 20 + - const: renesas,rmobile-iic # Generic 21 21 + 22 22 + - items: 23 23 + - enum: 24 24 + - renesas,iic-r8a7742 # RZ/G1H 25 25 + - renesas,iic-r8a7743 # RZ/G1M 26 26 + - renesas,iic-r8a7744 # RZ/G1N 27 27 + - renesas,iic-r8a7745 # RZ/G1E 28 28 + - renesas,iic-r8a7790 # R-Car H2 29 29 + - renesas,iic-r8a7791 # R-Car M2-W 30 30 + - renesas,iic-r8a7792 # R-Car V2H 31 31 + - renesas,iic-r8a7793 # R-Car M2-N 32 32 + - renesas,iic-r8a7794 # R-Car E2 33 33 + - const: renesas,rcar-gen2-iic # R-Car Gen2 and RZ/G1 34 34 + - const: renesas,rmobile-iic # Generic 35 35 + 36 36 + - items: 37 37 + - enum: 38 38 + - renesas,iic-r8a774a1 # RZ/G2M 39 39 + - renesas,iic-r8a774b1 # RZ/G2N 40 40 + - renesas,iic-r8a774c0 # RZ/G2E 41 41 + - renesas,iic-r8a774e1 # RZ/G2H 42 42 + - renesas,iic-r8a7795 # R-Car H3 43 43 + - renesas,iic-r8a7796 # R-Car M3-W 44 44 + - renesas,iic-r8a77961 # R-Car M3-W+ 45 45 + - renesas,iic-r8a77965 # R-Car M3-N 46 46 + - renesas,iic-r8a77990 # R-Car E3 47 47 + - const: renesas,rcar-gen3-iic # R-Car Gen3 and RZ/G2 48 48 + - const: renesas,rmobile-iic # Generic 49 49 + 50 50 + reg: 51 51 + maxItems: 1 52 52 + 53 53 + interrupts: true 54 54 + 55 55 + clock-frequency: 56 56 + description: 57 57 + Desired I2C bus clock frequency in Hz. The absence of this property 58 58 + indicates the default frequency 100 kHz. 59 59 + 60 60 + clocks: 61 61 + maxItems: 1 62 62 + 63 63 + power-domains: 64 64 + maxItems: 1 65 65 + 66 66 + resets: 67 67 + maxItems: 1 68 68 + 69 69 + dmas: 70 70 + minItems: 2 71 71 + maxItems: 4 72 72 + description: 73 73 + Must contain a list of pairs of references to DMA specifiers, one for 74 74 + transmission, and one for reception. 75 75 + 76 76 + dma-names: 77 77 + minItems: 2 78 78 + maxItems: 4 79 79 + items: 80 80 + enum: 81 81 + - tx 82 82 + - rx 83 83 + 84 84 + required: 85 85 + - compatible 86 86 + - reg 87 87 + - interrupts 88 88 + - clocks 89 89 + - power-domains 90 90 + - '#address-cells' 91 91 + - '#size-cells' 92 92 + 93 93 + allOf: 94 94 + - $ref: /schemas/i2c/i2c-controller.yaml# 95 95 + 96 96 + - if: 97 97 + properties: 98 98 + compatible: 99 99 + contains: 100 100 + enum: 101 101 + - renesas,iic-r8a7740 102 102 + - renesas,iic-sh73a0 103 103 + then: 104 104 + properties: 105 105 + interrupts: 106 106 + items: 107 107 + - description: Arbitration Lost Interrupt (ALI) 108 108 + - description: Non-acknowledge Detection Interrupt (TACKI) 109 109 + - description: Wait Interrupt (WAITI) 110 110 + - description: Data Transmit Enable interrupt (DTEI) 111 111 + else: 112 112 + properties: 113 113 + interrupts: 114 114 + items: 115 115 + - description: Single combined interrupt 116 116 + 117 117 + - if: 118 118 + properties: 119 119 + compatible: 120 120 + contains: 121 121 + enum: 122 122 + - renesas,rcar-gen2-iic 123 123 + - renesas,rcar-gen3-iic 124 124 + then: 125 125 + required: 126 126 + - resets 127 127 + 128 128 + unevaluatedProperties: false 129 129 + 130 130 + examples: 131 131 + - | 132 132 + #include <dt-bindings/clock/r8a7790-cpg-mssr.h> 133 133 + #include <dt-bindings/interrupt-controller/arm-gic.h> 134 134 + #include <dt-bindings/power/r8a7790-sysc.h> 135 135 + 136 136 + iic0: i2c@e6500000 { 137 137 + compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic", 138 138 + "renesas,rmobile-iic"; 139 139 + reg = <0xe6500000 0x425>; 140 140 + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 141 141 + clocks = <&cpg CPG_MOD 318>; 142 142 + clock-frequency = <400000>; 143 143 + dmas = <&dmac0 0x61>, <&dmac0 0x62>, <&dmac1 0x61>, <&dmac1 0x62>; 144 144 + dma-names = "tx", "rx", "tx", "rx"; 145 145 + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 146 146 + resets = <&cpg 318>; 147 147 + #address-cells = <1>; 148 148 + #size-cells = <0>; 149 149 + };

+102

Documentation/devicetree/bindings/i2c/ti,omap4-i2c.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/i2c/ti,omap4-i2c.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Bindings for I2C controllers on TI's OMAP and K3 SoCs 8 8 + 9 9 + maintainers: 10 10 + - Vignesh Raghavendra <vigneshr@ti.com> 11 11 + 12 12 + properties: 13 13 + compatible: 14 14 + oneOf: 15 15 + - enum: 16 16 + - ti,omap2420-i2c 17 17 + - ti,omap2430-i2c 18 18 + - ti,omap3-i2c 19 19 + - ti,omap4-i2c 20 20 + - items: 21 21 + - enum: 22 22 + - ti,am4372-i2c 23 23 + - ti,am64-i2c 24 24 + - ti,am654-i2c 25 25 + - ti,j721e-i2c 26 26 + - const: ti,omap4-i2c 27 27 + 28 28 + reg: 29 29 + maxItems: 1 30 30 + 31 31 + interrupts: 32 32 + maxItems: 1 33 33 + 34 34 + clocks: 35 35 + maxItems: 1 36 36 + 37 37 + clock-names: 38 38 + const: fck 39 39 + 40 40 + clock-frequency: true 41 41 + 42 42 + power-domains: true 43 43 + 44 44 + "#address-cells": 45 45 + const: 1 46 46 + 47 47 + "#size-cells": 48 48 + const: 0 49 49 + 50 50 + ti,hwmods: 51 51 + description: 52 52 + Must be "i2c<n>", n being the instance number (1-based). 53 53 + This property is applicable only on legacy platforms mainly omap2/3 54 54 + and ti81xx and should not be used on other platforms. 55 55 + $ref: /schemas/types.yaml#/definitions/string 56 56 + deprecated: true 57 57 + 58 58 + # subnode's properties 59 59 + patternProperties: 60 60 + "@[0-9a-f]+$": 61 61 + type: object 62 62 + description: 63 63 + Flash device uses the below defined properties in the subnode. 64 64 + 65 65 + required: 66 66 + - compatible 67 67 + - reg 68 68 + - interrupts 69 69 + 70 70 + additionalProperties: false 71 71 + 72 72 + if: 73 73 + properties: 74 74 + compatible: 75 75 + oneOf: 76 76 + - const: ti,omap2420-i2c 77 77 + - const: ti,omap2430-i2c 78 78 + - const: ti,omap3-i2c 79 79 + - const: ti,omap4-i2c 80 80 + 81 81 + then: 82 82 + properties: 83 83 + ti,hwmods: 84 84 + items: 85 85 + - pattern: "^i2c([1-9])$" 86 86 + 87 87 + else: 88 88 + properties: 89 89 + ti,hwmods: false 90 90 + 91 91 + examples: 92 92 + - | 93 93 + #include <dt-bindings/interrupt-controller/irq.h> 94 94 + #include <dt-bindings/interrupt-controller/arm-gic.h> 95 95 + 96 96 + main_i2c0: i2c@2000000 { 97 97 + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 98 98 + reg = <0x2000000 0x100>; 99 99 + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 100 100 + #address-cells = <1>; 101 101 + #size-cells = <0>; 102 102 + };

+395

Documentation/i2c/i2c-sysfs.rst

reviewed

··· 1 1 + .. SPDX-License-Identifier: GPL-2.0 2 2 + 3 3 + =============== 4 4 + Linux I2C Sysfs 5 5 + =============== 6 6 + 7 7 + Overview 8 8 + ======== 9 9 + 10 10 + I2C topology can be complex because of the existence of I2C MUX 11 11 + (I2C Multiplexer). The Linux 12 12 + kernel abstracts the MUX channels into logical I2C bus numbers. However, there 13 13 + is a gap of knowledge to map from the I2C bus physical number and MUX topology 14 14 + to logical I2C bus number. This doc is aimed to fill in this gap, so the 15 15 + audience (hardware engineers and new software developers for example) can learn 16 16 + the concept of logical I2C buses in the kernel, by knowing the physical I2C 17 17 + topology and navigating through the I2C sysfs in Linux shell. This knowledge is 18 18 + useful and essential to use ``i2c-tools`` for the purpose of development and 19 19 + debugging. 20 20 + 21 21 + Target audience 22 22 + --------------- 23 23 + 24 24 + People who need to use Linux shell to interact with I2C subsystem on a system 25 25 + which the Linux is running on. 26 26 + 27 27 + Prerequisites 28 28 + ------------- 29 29 + 30 30 + 1. Knowledge of general Linux shell file system commands and operations. 31 31 + 32 32 + 2. General knowledge of I2C, I2C MUX and I2C topology. 33 33 + 34 34 + Location of I2C Sysfs 35 35 + ===================== 36 36 + 37 37 + Typically, the Linux Sysfs filesystem is mounted at the ``/sys`` directory, 38 38 + so you can find the I2C Sysfs under ``/sys/bus/i2c/devices`` 39 39 + where you can directly ``cd`` to it. 40 40 + There is a list of symbolic links under that directory. The links that 41 41 + start with ``i2c-`` are I2C buses, which may be either physical or logical. The 42 42 + other links that begin with numbers and end with numbers are I2C devices, where 43 43 + the first number is I2C bus number, and the second number is I2C address. 44 44 + 45 45 + Google Pixel 3 phone for example:: 46 46 + 47 47 + blueline:/sys/bus/i2c/devices $ ls 48 48 + 0-0008 0-0061 1-0028 3-0043 4-0036 4-0041 i2c-1 i2c-3 49 49 + 0-000c 0-0066 2-0049 4-000b 4-0040 i2c-0 i2c-2 i2c-4 50 50 + 51 51 + ``i2c-2`` is an I2C bus whose number is 2, and ``2-0049`` is an I2C device 52 52 + on bus 2 address 0x49 bound with a kernel driver. 53 53 + 54 54 + Terminologies 55 55 + ============= 56 56 + 57 57 + First, let us define a couple of terminologies to avoid confusions in the later 58 58 + sections. 59 59 + 60 60 + (Physical) I2C Bus Controller 61 61 + ----------------------------- 62 62 + 63 63 + The hardware system that the Linux kernel is running on may have multiple 64 64 + physical I2C bus controllers. The controllers are hardware and physical, and the 65 65 + system may define multiple registers in the memory space to manipulate the 66 66 + controllers. Linux kernel has I2C bus drivers under source directory 67 67 + ``drivers/i2c/busses`` to translate kernel I2C API into register 68 68 + operations for different systems. This terminology is not limited to Linux 69 69 + kernel only. 70 70 + 71 71 + I2C Bus Physical Number 72 72 + ----------------------- 73 73 + 74 74 + For each physical I2C bus controller, the system vendor may assign a physical 75 75 + number to each controller. For example, the first I2C bus controller which has 76 76 + the lowest register addresses may be called ``I2C-0``. 77 77 + 78 78 + Logical I2C Bus 79 79 + --------------- 80 80 + 81 81 + Every I2C bus number you see in Linux I2C Sysfs is a logical I2C bus with a 82 82 + number assigned. This is similar to the fact that software code is usually 83 83 + written upon virtual memory space, instead of physical memory space. 84 84 + 85 85 + Each logical I2C bus may be an abstraction of a physical I2C bus controller, or 86 86 + an abstraction of a channel behind an I2C MUX. In case it is an abstraction of a 87 87 + MUX channel, whenever we access an I2C device via a such logical bus, the kernel 88 88 + will switch the I2C MUX for you to the proper channel as part of the 89 89 + abstraction. 90 90 + 91 91 + Physical I2C Bus 92 92 + ---------------- 93 93 + 94 94 + If the logical I2C bus is a direct abstraction of a physical I2C bus controller, 95 95 + let us call it a physical I2C bus. 96 96 + 97 97 + Caveat 98 98 + ------ 99 99 + 100 100 + This may be a confusing part for people who only know about the physical I2C 101 101 + design of a board. It is actually possible to rename the I2C bus physical number 102 102 + to a different number in logical I2C bus level in Device Tree Source (DTS) under 103 103 + section ``aliases``. See 104 104 + `arch/arm/boot/dts/nuvoton-npcm730-gsj.dts 105 105 + <../../arch/arm/boot/dts/nuvoton-npcm730-gsj.dts>`_ 106 106 + for an example of DTS file. 107 107 + 108 108 + Best Practice: **(To kernel software developers)** It is better to keep the I2C 109 109 + bus physical number the same as their corresponding logical I2C bus number, 110 110 + instead of renaming or mapping them, so that it may be less confusing to other 111 111 + users. These physical I2C buses can be served as good starting points for I2C 112 112 + MUX fanouts. For the following examples, we will assume that the physical I2C 113 113 + bus has a number same as their I2C bus physical number. 114 114 + 115 115 + Walk through Logical I2C Bus 116 116 + ============================ 117 117 + 118 118 + For the following content, we will use a more complex I2C topology as an 119 119 + example. Here is a brief graph for the I2C topology. If you do not understand 120 120 + this graph at the first glance, do not be afraid to continue reading this doc 121 121 + and review it when you finish reading. 122 122 + 123 123 + :: 124 124 + 125 125 + i2c-7 (physical I2C bus controller 7) 126 126 + `-- 7-0071 (4-channel I2C MUX at 0x71) 127 127 + |-- i2c-60 (channel-0) 128 128 + |-- i2c-73 (channel-1) 129 129 + | |-- 73-0040 (I2C sensor device with hwmon directory) 130 130 + | |-- 73-0070 (I2C MUX at 0x70, exists in DTS, but failed to probe) 131 131 + | `-- 73-0072 (8-channel I2C MUX at 0x72) 132 132 + | |-- i2c-78 (channel-0) 133 133 + | |-- ... (channel-1...6, i2c-79...i2c-84) 134 134 + | `-- i2c-85 (channel-7) 135 135 + |-- i2c-86 (channel-2) 136 136 + `-- i2c-203 (channel-3) 137 137 + 138 138 + Distinguish Physical and Logical I2C Bus 139 139 + ---------------------------------------- 140 140 + 141 141 + One simple way to distinguish between a physical I2C bus and a logical I2C bus, 142 142 + is to read the symbolic link ``device`` under the I2C bus directory by using 143 143 + command ``ls -l`` or ``readlink``. 144 144 + 145 145 + An alternative symbolic link to check is ``mux_device``. This link only exists 146 146 + in logical I2C bus directory which is fanned out from another I2C bus. 147 147 + Reading this link will also tell you which I2C MUX device created 148 148 + this logical I2C bus. 149 149 + 150 150 + If the symbolic link points to a directory ending with ``.i2c``, it should be a 151 151 + physical I2C bus, directly abstracting a physical I2C bus controller. For 152 152 + example:: 153 153 + 154 154 + $ readlink /sys/bus/i2c/devices/i2c-7/device 155 155 + ../../f0087000.i2c 156 156 + $ ls /sys/bus/i2c/devices/i2c-7/mux_device 157 157 + ls: /sys/bus/i2c/devices/i2c-7/mux_device: No such file or directory 158 158 + 159 159 + In this case, ``i2c-7`` is a physical I2C bus, so it does not have the symbolic 160 160 + link ``mux_device`` under its directory. And if the kernel software developer 161 161 + follows the common practice by not renaming physical I2C buses, this should also 162 162 + mean the physical I2C bus controller 7 of the system. 163 163 + 164 164 + On the other hand, if the symbolic link points to another I2C bus, the I2C bus 165 165 + presented by the current directory has to be a logical bus. The I2C bus pointed 166 166 + by the link is the parent bus which may be either a physical I2C bus or a 167 167 + logical one. In this case, the I2C bus presented by the current directory 168 168 + abstracts an I2C MUX channel under the parent bus. 169 169 + 170 170 + For example:: 171 171 + 172 172 + $ readlink /sys/bus/i2c/devices/i2c-73/device 173 173 + ../../i2c-7 174 174 + $ readlink /sys/bus/i2c/devices/i2c-73/mux_device 175 175 + ../7-0071 176 176 + 177 177 + ``i2c-73`` is a logical bus fanout by an I2C MUX under ``i2c-7`` 178 178 + whose I2C address is 0x71. 179 179 + Whenever we access an I2C device with bus 73, the kernel will always 180 180 + switch the I2C MUX addressed 0x71 to the proper channel for you as part of the 181 181 + abstraction. 182 182 + 183 183 + Finding out Logical I2C Bus Number 184 184 + ---------------------------------- 185 185 + 186 186 + In this section, we will describe how to find out the logical I2C bus number 187 187 + representing certain I2C MUX channels based on the knowledge of physical 188 188 + hardware I2C topology. 189 189 + 190 190 + In this example, we have a system which has a physical I2C bus 7 and not renamed 191 191 + in DTS. There is a 4-channel MUX at address 0x71 on that bus. There is another 192 192 + 8-channel MUX at address 0x72 behind the channel 1 of the 0x71 MUX. Let us 193 193 + navigate through Sysfs and find out the logical I2C bus number of the channel 3 194 194 + of the 0x72 MUX. 195 195 + 196 196 + First of all, let us go to the directory of ``i2c-7``:: 197 197 + 198 198 + ~$ cd /sys/bus/i2c/devices/i2c-7 199 199 + /sys/bus/i2c/devices/i2c-7$ ls 200 200 + 7-0071 i2c-60 name subsystem 201 201 + delete_device i2c-73 new_device uevent 202 202 + device i2c-86 of_node 203 203 + i2c-203 i2c-dev power 204 204 + 205 205 + There, we see the 0x71 MUX as ``7-0071``. Go inside it:: 206 206 + 207 207 + /sys/bus/i2c/devices/i2c-7$ cd 7-0071/ 208 208 + /sys/bus/i2c/devices/i2c-7/7-0071$ ls -l 209 209 + channel-0 channel-3 modalias power 210 210 + channel-1 driver name subsystem 211 211 + channel-2 idle_state of_node uevent 212 212 + 213 213 + Read the link ``channel-1`` using ``readlink`` or ``ls -l``:: 214 214 + 215 215 + /sys/bus/i2c/devices/i2c-7/7-0071$ readlink channel-1 216 216 + ../i2c-73 217 217 + 218 218 + We find out that the channel 1 of 0x71 MUX on ``i2c-7`` is assigned 219 219 + with a logical I2C bus number of 73. 220 220 + Let us continue the journey to directory ``i2c-73`` in either ways:: 221 221 + 222 222 + # cd to i2c-73 under I2C Sysfs root 223 223 + /sys/bus/i2c/devices/i2c-7/7-0071$ cd /sys/bus/i2c/devices/i2c-73 224 224 + /sys/bus/i2c/devices/i2c-73$ 225 225 + 226 226 + # cd the channel symbolic link 227 227 + /sys/bus/i2c/devices/i2c-7/7-0071$ cd channel-1 228 228 + /sys/bus/i2c/devices/i2c-7/7-0071/channel-1$ 229 229 + 230 230 + # cd the link content 231 231 + /sys/bus/i2c/devices/i2c-7/7-0071$ cd ../i2c-73 232 232 + /sys/bus/i2c/devices/i2c-7/i2c-73$ 233 233 + 234 234 + Either ways, you will end up in the directory of ``i2c-73``. Similar to above, 235 235 + we can now find the 0x72 MUX and what logical I2C bus numbers 236 236 + that its channels are assigned:: 237 237 + 238 238 + /sys/bus/i2c/devices/i2c-73$ ls 239 239 + 73-0040 device i2c-83 new_device 240 240 + 73-004e i2c-78 i2c-84 of_node 241 241 + 73-0050 i2c-79 i2c-85 power 242 242 + 73-0070 i2c-80 i2c-dev subsystem 243 243 + 73-0072 i2c-81 mux_device uevent 244 244 + delete_device i2c-82 name 245 245 + /sys/bus/i2c/devices/i2c-73$ cd 73-0072 246 246 + /sys/bus/i2c/devices/i2c-73/73-0072$ ls 247 247 + channel-0 channel-4 driver of_node 248 248 + channel-1 channel-5 idle_state power 249 249 + channel-2 channel-6 modalias subsystem 250 250 + channel-3 channel-7 name uevent 251 251 + /sys/bus/i2c/devices/i2c-73/73-0072$ readlink channel-3 252 252 + ../i2c-81 253 253 + 254 254 + There, we find out the logical I2C bus number of the channel 3 of the 0x72 MUX 255 255 + is 81. We can later use this number to switch to its own I2C Sysfs directory or 256 256 + issue ``i2c-tools`` commands. 257 257 + 258 258 + Tip: Once you understand the I2C topology with MUX, command 259 259 + `i2cdetect -l 260 260 + <https://manpages.debian.org/unstable/i2c-tools/i2cdetect.8.en.html>`_ 261 261 + in 262 262 + `I2C Tools 263 263 + <https://i2c.wiki.kernel.org/index.php/I2C_Tools>`_ 264 264 + can give you 265 265 + an overview of the I2C topology easily, if it is available on your system. For 266 266 + example:: 267 267 + 268 268 + $ i2cdetect -l | grep -e '\-73' -e _7 | sort -V 269 269 + i2c-7 i2c npcm_i2c_7 I2C adapter 270 270 + i2c-73 i2c i2c-7-mux (chan_id 1) I2C adapter 271 271 + i2c-78 i2c i2c-73-mux (chan_id 0) I2C adapter 272 272 + i2c-79 i2c i2c-73-mux (chan_id 1) I2C adapter 273 273 + i2c-80 i2c i2c-73-mux (chan_id 2) I2C adapter 274 274 + i2c-81 i2c i2c-73-mux (chan_id 3) I2C adapter 275 275 + i2c-82 i2c i2c-73-mux (chan_id 4) I2C adapter 276 276 + i2c-83 i2c i2c-73-mux (chan_id 5) I2C adapter 277 277 + i2c-84 i2c i2c-73-mux (chan_id 6) I2C adapter 278 278 + i2c-85 i2c i2c-73-mux (chan_id 7) I2C adapter 279 279 + 280 280 + Pinned Logical I2C Bus Number 281 281 + ----------------------------- 282 282 + 283 283 + If not specified in DTS, when an I2C MUX driver is applied and the MUX device is 284 284 + successfully probed, the kernel will assign the MUX channels with a logical bus 285 285 + number based on the current biggest logical bus number incrementally. For 286 286 + example, if the system has ``i2c-15`` as the highest logical bus number, and a 287 287 + 4-channel MUX is applied successfully, we will have ``i2c-16`` for the 288 288 + MUX channel 0, and all the way to ``i2c-19`` for the MUX channel 3. 289 289 + 290 290 + The kernel software developer is able to pin the fanout MUX channels to a static 291 291 + logical I2C bus number in the DTS. This doc will not go through the details on 292 292 + how to implement this in DTS, but we can see an example in: 293 293 + `arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts 294 294 + <../../arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts>`_ 295 295 + 296 296 + In the above example, there is an 8-channel I2C MUX at address 0x70 on physical 297 297 + I2C bus 2. The channel 2 of the MUX is defined as ``imux18`` in DTS, 298 298 + and pinned to logical I2C bus number 18 with the line of ``i2c18 = &imux18;`` 299 299 + in section ``aliases``. 300 300 + 301 301 + Take it further, it is possible to design a logical I2C bus number schema that 302 302 + can be easily remembered by humans or calculated arithmetically. For example, we 303 303 + can pin the fanout channels of a MUX on bus 3 to start at 30. So 30 will be the 304 304 + logical bus number of the channel 0 of the MUX on bus 3, and 37 will be the 305 305 + logical bus number of the channel 7 of the MUX on bus 3. 306 306 + 307 307 + I2C Devices 308 308 + =========== 309 309 + 310 310 + In previous sections, we mostly covered the I2C bus. In this section, let us see 311 311 + what we can learn from the I2C device directory whose link name is in the format 312 312 + of ``${bus}-${addr}``. The ``${bus}`` part in the name is a logical I2C bus 313 313 + decimal number, while the ``${addr}`` part is a hex number of the I2C address 314 314 + of each device. 315 315 + 316 316 + I2C Device Directory Content 317 317 + ---------------------------- 318 318 + 319 319 + Inside each I2C device directory, there is a file named ``name``. 320 320 + This file tells what device name it was used for the kernel driver to 321 321 + probe this device. Use command ``cat`` to read its content. For example:: 322 322 + 323 323 + /sys/bus/i2c/devices/i2c-73$ cat 73-0040/name 324 324 + ina230 325 325 + /sys/bus/i2c/devices/i2c-73$ cat 73-0070/name 326 326 + pca9546 327 327 + /sys/bus/i2c/devices/i2c-73$ cat 73-0072/name 328 328 + pca9547 329 329 + 330 330 + There is a symbolic link named ``driver`` to tell what Linux kernel driver was 331 331 + used to probe this device:: 332 332 + 333 333 + /sys/bus/i2c/devices/i2c-73$ readlink -f 73-0040/driver 334 334 + /sys/bus/i2c/drivers/ina2xx 335 335 + /sys/bus/i2c/devices/i2c-73$ readlink -f 73-0072/driver 336 336 + /sys/bus/i2c/drivers/pca954x 337 337 + 338 338 + But if the link ``driver`` does not exist at the first place, 339 339 + it may mean that the kernel driver failed to probe this device due to 340 340 + some errors. The error may be found in ``dmesg``:: 341 341 + 342 342 + /sys/bus/i2c/devices/i2c-73$ ls 73-0070/driver 343 343 + ls: 73-0070/driver: No such file or directory 344 344 + /sys/bus/i2c/devices/i2c-73$ dmesg | grep 73-0070 345 345 + pca954x 73-0070: probe failed 346 346 + pca954x 73-0070: probe failed 347 347 + 348 348 + Depending on what the I2C device is and what kernel driver was used to probe the 349 349 + device, we may have different content in the device directory. 350 350 + 351 351 + I2C MUX Device 352 352 + -------------- 353 353 + 354 354 + While you may be already aware of this in previous sections, an I2C MUX device 355 355 + will have symbolic link ``channel-*`` inside its device directory. 356 356 + These symbolic links point to their logical I2C bus directories:: 357 357 + 358 358 + /sys/bus/i2c/devices/i2c-73$ ls -l 73-0072/channel-* 359 359 + lrwxrwxrwx ... 73-0072/channel-0 -> ../i2c-78 360 360 + lrwxrwxrwx ... 73-0072/channel-1 -> ../i2c-79 361 361 + lrwxrwxrwx ... 73-0072/channel-2 -> ../i2c-80 362 362 + lrwxrwxrwx ... 73-0072/channel-3 -> ../i2c-81 363 363 + lrwxrwxrwx ... 73-0072/channel-4 -> ../i2c-82 364 364 + lrwxrwxrwx ... 73-0072/channel-5 -> ../i2c-83 365 365 + lrwxrwxrwx ... 73-0072/channel-6 -> ../i2c-84 366 366 + lrwxrwxrwx ... 73-0072/channel-7 -> ../i2c-85 367 367 + 368 368 + I2C Sensor Device / Hwmon 369 369 + ------------------------- 370 370 + 371 371 + I2C sensor device is also common to see. If they are bound by a kernel hwmon 372 372 + (Hardware Monitoring) driver successfully, you will see a ``hwmon`` directory 373 373 + inside the I2C device directory. Keep digging into it, you will find the Hwmon 374 374 + Sysfs for the I2C sensor device:: 375 375 + 376 376 + /sys/bus/i2c/devices/i2c-73/73-0040/hwmon/hwmon17$ ls 377 377 + curr1_input in0_lcrit_alarm name subsystem 378 378 + device in1_crit power uevent 379 379 + in0_crit in1_crit_alarm power1_crit update_interval 380 380 + in0_crit_alarm in1_input power1_crit_alarm 381 381 + in0_input in1_lcrit power1_input 382 382 + in0_lcrit in1_lcrit_alarm shunt_resistor 383 383 + 384 384 + For more info on the Hwmon Sysfs, refer to the doc: 385 385 + 386 386 + `Naming and data format standards for sysfs files 387 387 + <../hwmon/sysfs-interface.rst>`_ 388 388 + 389 389 + Instantiate I2C Devices in I2C Sysfs 390 390 + ------------------------------------ 391 391 + 392 392 + Refer to the doc: 393 393 + 394 394 + `How to instantiate I2C devices, Method 4: Instantiate from user-space 395 395 + <instantiating-devices.rst#method-4-instantiate-from-user-space>`_

+8 -5

MAINTAINERS

reviewed

··· 13494 13494 L: linux-omap@vger.kernel.org 13495 13495 L: linux-i2c@vger.kernel.org 13496 13496 S: Maintained 13497 13497 - F: Documentation/devicetree/bindings/i2c/i2c-omap.txt 13497 13497 + F: Documentation/devicetree/bindings/i2c/ti,omap4-i2c.yaml 13498 13498 F: drivers/i2c/busses/i2c-omap.c 13499 13499 13500 13500 OMAP IMAGING SUBSYSTEM (OMAP3 ISP and OMAP4 ISS) ··· 15722 15722 15723 15723 RENESAS EMEV2 I2C DRIVER 15724 15724 M: Wolfram Sang <wsa+renesas@sang-engineering.com> 15725 15725 + L: linux-renesas-soc@vger.kernel.org 15725 15726 S: Supported 15726 15726 - F: Documentation/devicetree/bindings/i2c/renesas,iic-emev2.txt 15727 15727 + F: Documentation/devicetree/bindings/i2c/renesas,iic-emev2.yaml 15727 15728 F: drivers/i2c/busses/i2c-emev2.c 15728 15729 15729 15730 RENESAS ETHERNET DRIVERS ··· 15744 15743 15745 15744 RENESAS R-CAR I2C DRIVERS 15746 15745 M: Wolfram Sang <wsa+renesas@sang-engineering.com> 15746 15746 + L: linux-renesas-soc@vger.kernel.org 15747 15747 S: Supported 15748 15748 - F: Documentation/devicetree/bindings/i2c/renesas,i2c.txt 15749 15749 - F: Documentation/devicetree/bindings/i2c/renesas,iic.txt 15748 15748 + F: Documentation/devicetree/bindings/i2c/renesas,rcar-i2c.yaml 15749 15749 + F: Documentation/devicetree/bindings/i2c/renesas,rmobile-iic.yaml 15750 15750 F: drivers/i2c/busses/i2c-rcar.c 15751 15751 F: drivers/i2c/busses/i2c-sh_mobile.c 15752 15752 ··· 15762 15760 15763 15761 RENESAS RIIC DRIVER 15764 15762 M: Chris Brandt <chris.brandt@renesas.com> 15763 15763 + L: linux-renesas-soc@vger.kernel.org 15765 15764 S: Supported 15766 15766 - F: Documentation/devicetree/bindings/i2c/renesas,riic.txt 15765 15765 + F: Documentation/devicetree/bindings/i2c/renesas,riic.yaml 15767 15766 F: drivers/i2c/busses/i2c-riic.c 15768 15767 15769 15768 RENESAS USB PHY DRIVER

+5

drivers/i2c/busses/i2c-ali1535.c

reviewed

··· 508 508 { 509 509 i2c_del_adapter(&ali1535_adapter); 510 510 release_region(ali1535_smba, ALI1535_SMB_IOSIZE); 511 511 + 512 512 + /* 513 513 + * do not call pci_disable_device(dev) since it can cause hard hangs on 514 514 + * some systems during power-off 515 515 + */ 511 516 } 512 517 513 518 static struct pci_driver ali1535_driver = {

+8 -4

drivers/i2c/busses/i2c-aspeed.c

reviewed

··· 727 727 { 728 728 u32 addr_reg_val, func_ctrl_reg_val; 729 729 730 730 - /* Set slave addr. */ 731 731 - addr_reg_val = readl(bus->base + ASPEED_I2C_DEV_ADDR_REG); 732 732 - addr_reg_val &= ~ASPEED_I2CD_DEV_ADDR_MASK; 733 733 - addr_reg_val |= slave_addr & ASPEED_I2CD_DEV_ADDR_MASK; 730 730 + /* 731 731 + * Set slave addr. Reserved bits can all safely be written with zeros 732 732 + * on all of ast2[456]00, so zero everything else to ensure we only 733 733 + * enable a single slave address (ast2500 has two, ast2600 has three, 734 734 + * the enable bits for which are also in this register) so that we don't 735 735 + * end up with additional phantom devices responding on the bus. 736 736 + */ 737 737 + addr_reg_val = slave_addr & ASPEED_I2CD_DEV_ADDR_MASK; 734 738 writel(addr_reg_val, bus->base + ASPEED_I2C_DEV_ADDR_REG); 735 739 736 740 /* Turn on slave mode. */

+45 -12

drivers/i2c/busses/i2c-cadence.c

reviewed

··· 578 578 { 579 579 unsigned int ctrl_reg; 580 580 unsigned int isr_status; 581 581 + unsigned long flags; 582 582 + bool hold_clear = false; 583 583 + bool irq_save = false; 584 584 + 585 585 + u32 addr; 581 586 582 587 id->p_recv_buf = id->p_msg->buf; 583 588 id->recv_count = id->p_msg->len; ··· 623 618 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET); 624 619 } 625 620 626 626 - /* Set the slave address in address register - triggers operation */ 627 627 - cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, 628 628 - CDNS_I2C_ADDR_OFFSET); 629 629 - /* Clear the bus hold flag if bytes to receive is less than FIFO size */ 621 621 + /* Determine hold_clear based on number of bytes to receive and hold flag */ 630 622 if (!id->bus_hold_flag && 631 631 - ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) && 632 632 - (id->recv_count <= CDNS_I2C_FIFO_DEPTH)) 633 633 - cdns_i2c_clear_bus_hold(id); 623 623 + ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) && 624 624 + (id->recv_count <= CDNS_I2C_FIFO_DEPTH)) { 625 625 + if (cdns_i2c_readreg(CDNS_I2C_CR_OFFSET) & CDNS_I2C_CR_HOLD) { 626 626 + hold_clear = true; 627 627 + if (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) 628 628 + irq_save = true; 629 629 + } 630 630 + } 631 631 + 632 632 + addr = id->p_msg->addr; 633 633 + addr &= CDNS_I2C_ADDR_MASK; 634 634 + 635 635 + if (hold_clear) { 636 636 + ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET) & ~CDNS_I2C_CR_HOLD; 637 637 + /* 638 638 + * In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size 639 639 + * register reaches '0'. This is an IP bug which causes transfer size 640 640 + * register overflow to 0xFF. To satisfy this timing requirement, 641 641 + * disable the interrupts on current processor core between register 642 642 + * writes to slave address register and control register. 643 643 + */ 644 644 + if (irq_save) 645 645 + local_irq_save(flags); 646 646 + 647 647 + cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET); 648 648 + cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 649 649 + /* Read it back to avoid bufferring and make sure write happens */ 650 650 + cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 651 651 + 652 652 + if (irq_save) 653 653 + local_irq_restore(flags); 654 654 + } else { 655 655 + cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET); 656 656 + } 657 657 + 634 658 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); 635 659 } 636 660 ··· 1251 1217 "Cadence I2C at %08lx", (unsigned long)r_mem->start); 1252 1218 1253 1219 id->clk = devm_clk_get(&pdev->dev, NULL); 1254 1254 - if (IS_ERR(id->clk)) { 1255 1255 - if (PTR_ERR(id->clk) != -EPROBE_DEFER) 1256 1256 - dev_err(&pdev->dev, "input clock not found.\n"); 1257 1257 - return PTR_ERR(id->clk); 1258 1258 - } 1220 1220 + if (IS_ERR(id->clk)) 1221 1221 + return dev_err_probe(&pdev->dev, PTR_ERR(id->clk), 1222 1222 + "input clock not found.\n"); 1223 1223 + 1259 1224 ret = clk_prepare_enable(id->clk); 1260 1225 if (ret) 1261 1226 dev_err(&pdev->dev, "Unable to enable clock.\n");

+1 -2

drivers/i2c/busses/i2c-cht-wc.c

reviewed

··· 354 354 return ret; 355 355 356 356 /* Alloc and register client IRQ */ 357 357 - adap->irq_domain = irq_domain_add_linear(pdev->dev.of_node, 1, 358 358 - &irq_domain_simple_ops, NULL); 357 357 + adap->irq_domain = irq_domain_add_linear(NULL, 1, &irq_domain_simple_ops, NULL); 359 358 if (!adap->irq_domain) 360 359 return -ENOMEM; 361 360

+1 -4

drivers/i2c/busses/i2c-davinci.c

reviewed

··· 768 768 if (irq <= 0) { 769 769 if (!irq) 770 770 irq = -ENXIO; 771 771 - if (irq != -EPROBE_DEFER) 772 772 - dev_err(&pdev->dev, 773 773 - "can't get irq resource ret=%d\n", irq); 774 774 - return irq; 771 771 + return dev_err_probe(&pdev->dev, irq, "can't get irq resource\n"); 775 772 } 776 773 777 774 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev),

+51 -85

drivers/i2c/busses/i2c-i801.c

reviewed

··· 88 88 * See the file Documentation/i2c/busses/i2c-i801.rst for details. 89 89 */ 90 90 91 91 + #define DRV_NAME "i801_smbus" 92 92 + 91 93 #include <linux/interrupt.h> 92 94 #include <linux/module.h> 93 95 #include <linux/pci.h> ··· 105 103 #include <linux/dmi.h> 106 104 #include <linux/slab.h> 107 105 #include <linux/string.h> 108 108 - #include <linux/wait.h> 106 106 + #include <linux/completion.h> 109 107 #include <linux/err.h> 110 108 #include <linux/platform_device.h> 111 109 #include <linux/platform_data/itco_wdt.h> ··· 133 131 134 132 /* PCI Address Constants */ 135 133 #define SMBBAR 4 136 136 - #define SMBPCICTL 0x004 137 137 - #define SMBPCISTS 0x006 138 134 #define SMBHSTCFG 0x040 139 135 #define TCOBASE 0x050 140 136 #define TCOCTL 0x054 ··· 140 140 #define SBREG_BAR 0x10 141 141 #define SBREG_SMBCTRL 0xc6000c 142 142 #define SBREG_SMBCTRL_DNV 0xcf000c 143 143 - 144 144 - /* Host status bits for SMBPCISTS */ 145 145 - #define SMBPCISTS_INTS BIT(3) 146 146 - 147 147 - /* Control bits for SMBPCICTL */ 148 148 - #define SMBPCICTL_INTDIS BIT(10) 149 143 150 144 /* Host configuration bits for SMBHSTCFG */ 151 145 #define SMBHSTCFG_HST_EN BIT(0) ··· 157 163 /* Auxiliary control register bits, ICH4+ only */ 158 164 #define SMBAUXCTL_CRC BIT(0) 159 165 #define SMBAUXCTL_E32B BIT(1) 160 160 - 161 161 - /* Other settings */ 162 162 - #define MAX_RETRIES 400 163 166 164 167 /* I801 command constants */ 165 168 #define I801_QUICK 0x00 ··· 261 270 unsigned int features; 262 271 263 272 /* isr processing */ 264 264 - wait_queue_head_t waitq; 273 273 + struct completion done; 265 274 u8 status; 266 275 267 276 /* Command state used by isr for byte-by-byte block transactions */ ··· 444 453 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 445 454 static int i801_wait_intr(struct i801_priv *priv) 446 455 { 447 447 - int timeout = 0; 448 448 - int status; 456 456 + unsigned long timeout = jiffies + priv->adapter.timeout; 457 457 + int status, busy; 449 458 450 450 - /* We will always wait for a fraction of a second! */ 451 459 do { 452 460 usleep_range(250, 500); 453 461 status = inb_p(SMBHSTSTS(priv)); 454 454 - } while (((status & SMBHSTSTS_HOST_BUSY) || 455 455 - !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && 456 456 - (timeout++ < MAX_RETRIES)); 462 462 + busy = status & SMBHSTSTS_HOST_BUSY; 463 463 + status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR; 464 464 + if (!busy && status) 465 465 + return status; 466 466 + } while (time_is_after_eq_jiffies(timeout)); 457 467 458 458 - if (timeout > MAX_RETRIES) { 459 459 - dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); 460 460 - return -ETIMEDOUT; 461 461 - } 462 462 - return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); 468 468 + return -ETIMEDOUT; 463 469 } 464 470 465 471 /* Wait for either BYTE_DONE or an error flag being set */ 466 472 static int i801_wait_byte_done(struct i801_priv *priv) 467 473 { 468 468 - int timeout = 0; 474 474 + unsigned long timeout = jiffies + priv->adapter.timeout; 469 475 int status; 470 476 471 471 - /* We will always wait for a fraction of a second! */ 472 477 do { 473 478 usleep_range(250, 500); 474 479 status = inb_p(SMBHSTSTS(priv)); 475 475 - } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && 476 476 - (timeout++ < MAX_RETRIES)); 480 480 + if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) 481 481 + return status & STATUS_ERROR_FLAGS; 482 482 + } while (time_is_after_eq_jiffies(timeout)); 477 483 478 478 - if (timeout > MAX_RETRIES) { 479 479 - dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); 480 480 - return -ETIMEDOUT; 481 481 - } 482 482 - return status & STATUS_ERROR_FLAGS; 484 484 + return -ETIMEDOUT; 483 485 } 484 486 485 487 static int i801_transaction(struct i801_priv *priv, int xact) 486 488 { 487 489 int status; 488 488 - int result; 490 490 + unsigned long result; 489 491 const struct i2c_adapter *adap = &priv->adapter; 490 492 491 491 - result = i801_check_pre(priv); 492 492 - if (result < 0) 493 493 - return result; 493 493 + status = i801_check_pre(priv); 494 494 + if (status < 0) 495 495 + return status; 494 496 495 497 if (priv->features & FEATURE_IRQ) { 498 498 + reinit_completion(&priv->done); 496 499 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 497 500 SMBHSTCNT(priv)); 498 498 - result = wait_event_timeout(priv->waitq, 499 499 - (status = priv->status), 500 500 - adap->timeout); 501 501 - if (!result) { 502 502 - status = -ETIMEDOUT; 503 503 - dev_warn(&priv->pci_dev->dev, 504 504 - "Timeout waiting for interrupt!\n"); 505 505 - } 506 506 - priv->status = 0; 507 507 - return i801_check_post(priv, status); 501 501 + result = wait_for_completion_timeout(&priv->done, adap->timeout); 502 502 + return i801_check_post(priv, result ? priv->status : -ETIMEDOUT); 508 503 } 509 504 510 505 /* the current contents of SMBHSTCNT can be overwritten, since PEC, ··· 615 638 * DEV_ERR - Invalid command, NAK or communication timeout 616 639 * BUS_ERR - SMI# transaction collision 617 640 * FAILED - transaction was canceled due to a KILL request 618 618 - * When any of these occur, update ->status and wake up the waitq. 641 641 + * When any of these occur, update ->status and signal completion. 619 642 * ->status must be cleared before kicking off the next transaction. 620 643 * 621 644 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt ··· 630 653 u8 status; 631 654 632 655 /* Confirm this is our interrupt */ 633 633 - pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 634 634 - if (!(pcists & SMBPCISTS_INTS)) 656 656 + pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 657 657 + if (!(pcists & PCI_STATUS_INTERRUPT)) 635 658 return IRQ_NONE; 636 659 637 660 if (priv->features & FEATURE_HOST_NOTIFY) { ··· 652 675 if (status) { 653 676 outb_p(status, SMBHSTSTS(priv)); 654 677 priv->status = status; 655 655 - wake_up(&priv->waitq); 678 678 + complete(&priv->done); 656 679 } 657 680 658 681 return IRQ_HANDLED; ··· 671 694 int i, len; 672 695 int smbcmd; 673 696 int status; 674 674 - int result; 697 697 + unsigned long result; 675 698 const struct i2c_adapter *adap = &priv->adapter; 676 699 677 700 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 678 701 return -EOPNOTSUPP; 679 702 680 680 - result = i801_check_pre(priv); 681 681 - if (result < 0) 682 682 - return result; 703 703 + status = i801_check_pre(priv); 704 704 + if (status < 0) 705 705 + return status; 683 706 684 707 len = data->block[0]; 685 708 ··· 703 726 priv->count = 0; 704 727 priv->data = &data->block[1]; 705 728 729 729 + reinit_completion(&priv->done); 706 730 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 707 707 - result = wait_event_timeout(priv->waitq, 708 708 - (status = priv->status), 709 709 - adap->timeout); 710 710 - if (!result) { 711 711 - status = -ETIMEDOUT; 712 712 - dev_warn(&priv->pci_dev->dev, 713 713 - "Timeout waiting for interrupt!\n"); 714 714 - } 715 715 - priv->status = 0; 716 716 - return i801_check_post(priv, status); 731 731 + result = wait_for_completion_timeout(&priv->done, adap->timeout); 732 732 + return i801_check_post(priv, result ? priv->status : -ETIMEDOUT); 717 733 } 718 734 719 735 for (i = 1; i <= len; i++) { ··· 1292 1322 return; 1293 1323 1294 1324 if (apanel_addr) { 1295 1295 - struct i2c_board_info info; 1325 1325 + struct i2c_board_info info = { 1326 1326 + .addr = apanel_addr, 1327 1327 + .type = "fujitsu_apanel", 1328 1328 + }; 1296 1329 1297 1297 - memset(&info, 0, sizeof(struct i2c_board_info)); 1298 1298 - info.addr = apanel_addr; 1299 1299 - strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); 1300 1330 i2c_new_client_device(&priv->adapter, &info); 1301 1331 } 1302 1332 ··· 1685 1715 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1686 1716 #endif 1687 1717 1688 1688 - static unsigned char i801_setup_hstcfg(struct i801_priv *priv) 1718 1718 + static void i801_setup_hstcfg(struct i801_priv *priv) 1689 1719 { 1690 1720 unsigned char hstcfg = priv->original_hstcfg; 1691 1721 1692 1722 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1693 1723 hstcfg |= SMBHSTCFG_HST_EN; 1694 1724 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg); 1695 1695 - return hstcfg; 1696 1725 } 1697 1726 1698 1727 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1699 1728 { 1700 1700 - unsigned char temp; 1701 1729 int err, i; 1702 1730 struct i801_priv *priv; 1703 1731 ··· 1806 1838 if (i801_acpi_probe(priv)) 1807 1839 return -ENODEV; 1808 1840 1809 1809 - err = pcim_iomap_regions(dev, 1 << SMBBAR, 1810 1810 - dev_driver_string(&dev->dev)); 1841 1841 + err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME); 1811 1842 if (err) { 1812 1843 dev_err(&dev->dev, 1813 1844 "Failed to request SMBus region 0x%lx-0x%Lx\n", ··· 1817 1850 } 1818 1851 1819 1852 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg); 1820 1820 - temp = i801_setup_hstcfg(priv); 1853 1853 + i801_setup_hstcfg(priv); 1821 1854 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN)) 1822 1855 dev_info(&dev->dev, "Enabling SMBus device\n"); 1823 1856 1824 1824 - if (temp & SMBHSTCFG_SMB_SMI_EN) { 1857 1857 + if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) { 1825 1858 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1826 1859 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1827 1860 priv->features &= ~FEATURE_IRQ; 1828 1861 } 1829 1829 - if (temp & SMBHSTCFG_SPD_WD) 1862 1862 + if (priv->original_hstcfg & SMBHSTCFG_SPD_WD) 1830 1863 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1831 1864 1832 1865 /* Clear special mode bits */ ··· 1848 1881 u16 pcictl, pcists; 1849 1882 1850 1883 /* Complain if an interrupt is already pending */ 1851 1851 - pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 1852 1852 - if (pcists & SMBPCISTS_INTS) 1884 1884 + pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 1885 1885 + if (pcists & PCI_STATUS_INTERRUPT) 1853 1886 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1854 1887 1855 1888 /* Check if interrupts have been disabled */ 1856 1856 - pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl); 1857 1857 - if (pcictl & SMBPCICTL_INTDIS) { 1889 1889 + pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pcictl); 1890 1890 + if (pcictl & PCI_COMMAND_INTX_DISABLE) { 1858 1891 dev_info(&dev->dev, "Interrupts are disabled\n"); 1859 1892 priv->features &= ~FEATURE_IRQ; 1860 1893 } 1861 1894 } 1862 1895 1863 1896 if (priv->features & FEATURE_IRQ) { 1864 1864 - init_waitqueue_head(&priv->waitq); 1897 1897 + init_completion(&priv->done); 1865 1898 1866 1899 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1867 1867 - IRQF_SHARED, 1868 1868 - dev_driver_string(&dev->dev), priv); 1900 1900 + IRQF_SHARED, DRV_NAME, priv); 1869 1901 if (err) { 1870 1902 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1871 1903 dev->irq, err); ··· 1954 1988 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1955 1989 1956 1990 static struct pci_driver i801_driver = { 1957 1957 - .name = "i801_smbus", 1991 1991 + .name = DRV_NAME, 1958 1992 .id_table = i801_ids, 1959 1993 .probe = i801_probe, 1960 1994 .remove = i801_remove,

+5 -14

drivers/i2c/busses/i2c-imx.c

reviewed

··· 170 170 171 171 struct imx_i2c_hwdata { 172 172 enum imx_i2c_type devtype; 173 173 - unsigned regshift; 173 173 + unsigned int regshift; 174 174 struct imx_i2c_clk_pair *clk_div; 175 175 - unsigned ndivs; 176 176 - unsigned i2sr_clr_opcode; 177 177 - unsigned i2cr_ien_opcode; 175 175 + unsigned int ndivs; 176 176 + unsigned int i2sr_clr_opcode; 177 177 + unsigned int i2cr_ien_opcode; 178 178 }; 179 179 180 180 struct imx_i2c_dma { ··· 452 452 unsigned long orig_jiffies = jiffies; 453 453 unsigned int temp; 454 454 455 455 - dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 456 456 - 457 455 while (1) { 458 456 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 459 457 ··· 597 599 unsigned int temp = 0; 598 600 int result; 599 601 600 600 - dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 601 601 - 602 602 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); 603 603 /* Enable I2C controller */ 604 604 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); ··· 631 635 632 636 if (!i2c_imx->stopped) { 633 637 /* Stop I2C transaction */ 634 634 - dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 635 638 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 636 639 if (!(temp & I2CR_MSTA)) 637 640 i2c_imx->stopped = 1; ··· 1162 1167 bool is_lastmsg = false; 1163 1168 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1164 1169 1165 1165 - dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 1166 1166 - 1167 1170 /* Start I2C transfer */ 1168 1171 result = i2c_imx_start(i2c_imx, atomic); 1169 1172 if (result) { ··· 1364 1371 dma_addr_t phy_addr; 1365 1372 const struct imx_i2c_hwdata *match; 1366 1373 1367 1367 - dev_dbg(&pdev->dev, "<%s>\n", __func__); 1368 1368 - 1369 1374 irq = platform_get_irq(pdev, 0); 1370 1375 if (irq < 0) 1371 1376 return irq; ··· 1386 1395 platform_get_device_id(pdev)->driver_data; 1387 1396 1388 1397 /* Setup i2c_imx driver structure */ 1389 1389 - strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); 1398 1398 + strscpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); 1390 1399 i2c_imx->adapter.owner = THIS_MODULE; 1391 1400 i2c_imx->adapter.algo = &i2c_imx_algo; 1392 1401 i2c_imx->adapter.dev.parent = &pdev->dev;

+2

drivers/i2c/busses/i2c-mpc.c

reviewed

··· 635 635 636 636 status = readb(i2c->base + MPC_I2C_SR); 637 637 if (status & CSR_MIF) { 638 638 + /* Read again to allow register to stabilise */ 639 639 + status = readb(i2c->base + MPC_I2C_SR); 638 640 writeb(0, i2c->base + MPC_I2C_SR); 639 641 mpc_i2c_do_intr(i2c, status); 640 642 return IRQ_HANDLED;

+8 -1

drivers/i2c/busses/i2c-mt65xx.c

reviewed

··· 1225 1225 i2c->adap.quirks = i2c->dev_comp->quirks; 1226 1226 i2c->adap.timeout = 2 * HZ; 1227 1227 i2c->adap.retries = 1; 1228 1228 + i2c->adap.bus_regulator = devm_regulator_get_optional(&pdev->dev, "vbus"); 1229 1229 + if (IS_ERR(i2c->adap.bus_regulator)) { 1230 1230 + if (PTR_ERR(i2c->adap.bus_regulator) == -ENODEV) 1231 1231 + i2c->adap.bus_regulator = NULL; 1232 1232 + else 1233 1233 + return PTR_ERR(i2c->adap.bus_regulator); 1234 1234 + } 1228 1235 1229 1236 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c); 1230 1237 if (ret) ··· 1293 1286 1294 1287 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, 1295 1288 IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE, 1296 1296 - I2C_DRV_NAME, i2c); 1289 1289 + dev_name(&pdev->dev), i2c); 1297 1290 if (ret < 0) { 1298 1291 dev_err(&pdev->dev, 1299 1292 "Request I2C IRQ %d fail\n", irq);

+1

drivers/i2c/busses/i2c-qcom-cci.c

reviewed

··· 769 769 { .compatible = "qcom,msm8916-cci", .data = &cci_v1_data}, 770 770 { .compatible = "qcom,msm8996-cci", .data = &cci_v2_data}, 771 771 { .compatible = "qcom,sdm845-cci", .data = &cci_v2_data}, 772 772 + { .compatible = "qcom,sm8250-cci", .data = &cci_v2_data}, 772 773 {} 773 774 }; 774 775 MODULE_DEVICE_TABLE(of, cci_dt_match);

-1

drivers/i2c/busses/i2c-rcar.c

reviewed

··· 1013 1013 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, 1014 1014 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, 1015 1015 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 }, 1016 1016 - { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, /* Deprecated */ 1017 1016 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 }, 1018 1017 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 }, 1019 1018 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 },

+22 -1

drivers/i2c/busses/i2c-riic.c

reviewed

··· 42 42 #include <linux/io.h> 43 43 #include <linux/module.h> 44 44 #include <linux/of.h> 45 45 + #include <linux/of_device.h> 45 46 #include <linux/platform_device.h> 46 47 #include <linux/pm_runtime.h> 48 48 + #include <linux/reset.h> 47 49 48 50 #define RIIC_ICCR1 0x00 49 51 #define RIIC_ICCR2 0x04 ··· 87 85 #define ICBR_RESERVED 0xe0 /* Should be 1 on writes */ 88 86 89 87 #define RIIC_INIT_MSG -1 88 88 + 89 89 + enum riic_type { 90 90 + RIIC_RZ_A, 91 91 + RIIC_RZ_G2L, 92 92 + }; 90 93 91 94 struct riic_dev { 92 95 void __iomem *base; ··· 402 395 struct i2c_adapter *adap; 403 396 struct resource *res; 404 397 struct i2c_timings i2c_t; 398 398 + struct reset_control *rstc; 405 399 int i, ret; 400 400 + enum riic_type type; 406 401 407 402 riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL); 408 403 if (!riic) ··· 419 410 if (IS_ERR(riic->clk)) { 420 411 dev_err(&pdev->dev, "missing controller clock"); 421 412 return PTR_ERR(riic->clk); 413 413 + } 414 414 + 415 415 + type = (enum riic_type)of_device_get_match_data(&pdev->dev); 416 416 + if (type == RIIC_RZ_G2L) { 417 417 + rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 418 418 + if (IS_ERR(rstc)) { 419 419 + dev_err(&pdev->dev, "Error: missing reset ctrl\n"); 420 420 + return PTR_ERR(rstc); 421 421 + } 422 422 + 423 423 + reset_control_deassert(rstc); 422 424 } 423 425 424 426 for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) { ··· 492 472 } 493 473 494 474 static const struct of_device_id riic_i2c_dt_ids[] = { 495 495 - { .compatible = "renesas,riic-rz" }, 475 475 + { .compatible = "renesas,riic-r9a07g044", .data = (void *)RIIC_RZ_G2L }, 476 476 + { .compatible = "renesas,riic-rz", .data = (void *)RIIC_RZ_A }, 496 477 { /* Sentinel */ }, 497 478 }; 498 479

+73

drivers/i2c/busses/i2c-stm32f7.c

reviewed

··· 51 51 52 52 /* STM32F7 I2C control 1 */ 53 53 #define STM32F7_I2C_CR1_PECEN BIT(23) 54 54 + #define STM32F7_I2C_CR1_ALERTEN BIT(22) 54 55 #define STM32F7_I2C_CR1_SMBHEN BIT(20) 55 56 #define STM32F7_I2C_CR1_WUPEN BIT(18) 56 57 #define STM32F7_I2C_CR1_SBC BIT(16) ··· 126 125 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17) 127 126 #define STM32F7_I2C_ISR_DIR BIT(16) 128 127 #define STM32F7_I2C_ISR_BUSY BIT(15) 128 128 + #define STM32F7_I2C_ISR_ALERT BIT(13) 129 129 #define STM32F7_I2C_ISR_PECERR BIT(11) 130 130 #define STM32F7_I2C_ISR_ARLO BIT(9) 131 131 #define STM32F7_I2C_ISR_BERR BIT(8) ··· 140 138 #define STM32F7_I2C_ISR_TXE BIT(0) 141 139 142 140 /* STM32F7 I2C Interrupt Clear */ 141 141 + #define STM32F7_I2C_ICR_ALERTCF BIT(13) 143 142 #define STM32F7_I2C_ICR_PECCF BIT(11) 144 143 #define STM32F7_I2C_ICR_ARLOCF BIT(9) 145 144 #define STM32F7_I2C_ICR_BERRCF BIT(8) ··· 282 279 }; 283 280 284 281 /** 282 282 + * struct stm32f7_i2c_alert - SMBus alert specific data 283 283 + * @setup: platform data for the smbus_alert i2c client 284 284 + * @ara: I2C slave device used to respond to the SMBus Alert with Alert 285 285 + * Response Address 286 286 + */ 287 287 + struct stm32f7_i2c_alert { 288 288 + struct i2c_smbus_alert_setup setup; 289 289 + struct i2c_client *ara; 290 290 + }; 291 291 + 292 292 + /** 285 293 * struct stm32f7_i2c_dev - private data of the controller 286 294 * @adap: I2C adapter for this controller 287 295 * @dev: device for this controller ··· 324 310 * @analog_filter: boolean to indicate enabling of the analog filter 325 311 * @dnf_dt: value of digital filter requested via dt 326 312 * @dnf: value of digital filter to apply 313 313 + * @alert: SMBus alert specific data 327 314 */ 328 315 struct stm32f7_i2c_dev { 329 316 struct i2c_adapter adap; ··· 356 341 bool analog_filter; 357 342 u32 dnf_dt; 358 343 u32 dnf; 344 344 + struct stm32f7_i2c_alert *alert; 359 345 }; 360 346 361 347 /* ··· 1640 1624 f7_msg->result = -EINVAL; 1641 1625 } 1642 1626 1627 1627 + if (status & STM32F7_I2C_ISR_ALERT) { 1628 1628 + dev_dbg(dev, "<%s>: SMBus alert received\n", __func__); 1629 1629 + writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR); 1630 1630 + i2c_handle_smbus_alert(i2c_dev->alert->ara); 1631 1631 + return IRQ_HANDLED; 1632 1632 + } 1633 1633 + 1643 1634 if (!i2c_dev->slave_running) { 1644 1635 u32 mask; 1645 1636 /* Disable interrupts */ ··· 2013 1990 } 2014 1991 } 2015 1992 1993 1993 + static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev) 1994 1994 + { 1995 1995 + struct stm32f7_i2c_alert *alert; 1996 1996 + struct i2c_adapter *adap = &i2c_dev->adap; 1997 1997 + struct device *dev = i2c_dev->dev; 1998 1998 + void __iomem *base = i2c_dev->base; 1999 1999 + 2000 2000 + alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL); 2001 2001 + if (!alert) 2002 2002 + return -ENOMEM; 2003 2003 + 2004 2004 + alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup); 2005 2005 + if (IS_ERR(alert->ara)) 2006 2006 + return PTR_ERR(alert->ara); 2007 2007 + 2008 2008 + i2c_dev->alert = alert; 2009 2009 + 2010 2010 + /* Enable SMBus Alert */ 2011 2011 + stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN); 2012 2012 + 2013 2013 + return 0; 2014 2014 + } 2015 2015 + 2016 2016 + static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev) 2017 2017 + { 2018 2018 + struct stm32f7_i2c_alert *alert = i2c_dev->alert; 2019 2019 + void __iomem *base = i2c_dev->base; 2020 2020 + 2021 2021 + if (alert) { 2022 2022 + /* Disable SMBus Alert */ 2023 2023 + stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, 2024 2024 + STM32F7_I2C_CR1_ALERTEN); 2025 2025 + i2c_unregister_device(alert->ara); 2026 2026 + } 2027 2027 + } 2028 2028 + 2016 2029 static u32 stm32f7_i2c_func(struct i2c_adapter *adap) 2017 2030 { 2018 2031 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap); ··· 2232 2173 } 2233 2174 } 2234 2175 2176 2176 + if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) { 2177 2177 + ret = stm32f7_i2c_enable_smbus_alert(i2c_dev); 2178 2178 + if (ret) { 2179 2179 + dev_err(i2c_dev->dev, 2180 2180 + "failed to enable SMBus alert protocol (%d)\n", 2181 2181 + ret); 2182 2182 + goto i2c_disable_smbus_host; 2183 2183 + } 2184 2184 + } 2185 2185 + 2235 2186 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr); 2236 2187 2237 2188 pm_runtime_mark_last_busy(i2c_dev->dev); 2238 2189 pm_runtime_put_autosuspend(i2c_dev->dev); 2239 2190 2240 2191 return 0; 2192 2192 + 2193 2193 + i2c_disable_smbus_host: 2194 2194 + stm32f7_i2c_disable_smbus_host(i2c_dev); 2241 2195 2242 2196 i2c_adapter_remove: 2243 2197 i2c_del_adapter(adap); ··· 2286 2214 { 2287 2215 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 2288 2216 2217 2217 + stm32f7_i2c_disable_smbus_alert(i2c_dev); 2289 2218 stm32f7_i2c_disable_smbus_host(i2c_dev); 2290 2219 2291 2220 i2c_del_adapter(&i2c_dev->adap);

+4 -5

drivers/i2c/busses/i2c-xiic.c

reviewed

··· 798 798 init_waitqueue_head(&i2c->wait); 799 799 800 800 i2c->clk = devm_clk_get(&pdev->dev, NULL); 801 801 - if (IS_ERR(i2c->clk)) { 802 802 - if (PTR_ERR(i2c->clk) != -EPROBE_DEFER) 803 803 - dev_err(&pdev->dev, "input clock not found.\n"); 804 804 - return PTR_ERR(i2c->clk); 805 805 - } 801 801 + if (IS_ERR(i2c->clk)) 802 802 + return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), 803 803 + "input clock not found.\n"); 804 804 + 806 805 ret = clk_prepare_enable(i2c->clk); 807 806 if (ret) { 808 807 dev_err(&pdev->dev, "Unable to enable clock.\n");

+105 -3

drivers/i2c/i2c-core-base.c

reviewed

··· 24 24 #include <linux/i2c-smbus.h> 25 25 #include <linux/idr.h> 26 26 #include <linux/init.h> 27 27 + #include <linux/interrupt.h> 27 28 #include <linux/irqflags.h> 28 29 #include <linux/jump_label.h> 29 30 #include <linux/kernel.h> ··· 400 399 static int i2c_init_recovery(struct i2c_adapter *adap) 401 400 { 402 401 struct i2c_bus_recovery_info *bri = adap->bus_recovery_info; 403 403 - char *err_str, *err_level = KERN_ERR; 402 402 + bool is_error_level = true; 403 403 + char *err_str; 404 404 405 405 if (!bri) 406 406 return 0; ··· 411 409 412 410 if (!bri->recover_bus) { 413 411 err_str = "no suitable method provided"; 414 414 - err_level = KERN_DEBUG; 412 412 + is_error_level = false; 415 413 goto err; 416 414 } 417 415 ··· 438 436 439 437 return 0; 440 438 err: 441 441 - dev_printk(err_level, &adap->dev, "Not using recovery: %s\n", err_str); 439 439 + if (is_error_level) 440 440 + dev_err(&adap->dev, "Not using recovery: %s\n", err_str); 441 441 + else 442 442 + dev_dbg(&adap->dev, "Not using recovery: %s\n", err_str); 442 443 adap->bus_recovery_info = NULL; 443 444 444 445 return -EINVAL; ··· 466 461 static int i2c_device_probe(struct device *dev) 467 462 { 468 463 struct i2c_client *client = i2c_verify_client(dev); 464 464 + struct i2c_adapter *adap; 469 465 struct i2c_driver *driver; 470 466 int status; 471 467 472 468 if (!client) 473 469 return 0; 474 470 471 471 + adap = client->adapter; 475 472 client->irq = client->init_irq; 476 473 477 474 if (!client->irq) { ··· 539 532 540 533 dev_dbg(dev, "probe\n"); 541 534 535 535 + if (adap->bus_regulator) { 536 536 + status = regulator_enable(adap->bus_regulator); 537 537 + if (status < 0) { 538 538 + dev_err(&adap->dev, "Failed to enable bus regulator\n"); 539 539 + goto err_clear_wakeup_irq; 540 540 + } 541 541 + } 542 542 + 542 543 status = of_clk_set_defaults(dev->of_node, false); 543 544 if (status < 0) 544 545 goto err_clear_wakeup_irq; ··· 604 589 static int i2c_device_remove(struct device *dev) 605 590 { 606 591 struct i2c_client *client = to_i2c_client(dev); 592 592 + struct i2c_adapter *adap; 607 593 struct i2c_driver *driver; 608 594 595 595 + adap = client->adapter; 609 596 driver = to_i2c_driver(dev->driver); 610 597 if (driver->remove) { 611 598 int status; ··· 622 605 devres_release_group(&client->dev, client->devres_group_id); 623 606 624 607 dev_pm_domain_detach(&client->dev, true); 608 608 + if (!pm_runtime_status_suspended(&client->dev) && adap->bus_regulator) 609 609 + regulator_disable(adap->bus_regulator); 625 610 626 611 dev_pm_clear_wake_irq(&client->dev); 627 612 device_init_wakeup(&client->dev, false); ··· 636 617 return 0; 637 618 } 638 619 620 620 + #ifdef CONFIG_PM_SLEEP 621 621 + static int i2c_resume_early(struct device *dev) 622 622 + { 623 623 + struct i2c_client *client = i2c_verify_client(dev); 624 624 + int err; 625 625 + 626 626 + if (!client) 627 627 + return 0; 628 628 + 629 629 + if (pm_runtime_status_suspended(&client->dev) && 630 630 + client->adapter->bus_regulator) { 631 631 + err = regulator_enable(client->adapter->bus_regulator); 632 632 + if (err) 633 633 + return err; 634 634 + } 635 635 + 636 636 + return pm_generic_resume_early(&client->dev); 637 637 + } 638 638 + 639 639 + static int i2c_suspend_late(struct device *dev) 640 640 + { 641 641 + struct i2c_client *client = i2c_verify_client(dev); 642 642 + int err; 643 643 + 644 644 + if (!client) 645 645 + return 0; 646 646 + 647 647 + err = pm_generic_suspend_late(&client->dev); 648 648 + if (err) 649 649 + return err; 650 650 + 651 651 + if (!pm_runtime_status_suspended(&client->dev) && 652 652 + client->adapter->bus_regulator) 653 653 + return regulator_disable(client->adapter->bus_regulator); 654 654 + 655 655 + return 0; 656 656 + } 657 657 + #endif 658 658 + 659 659 + #ifdef CONFIG_PM 660 660 + static int i2c_runtime_resume(struct device *dev) 661 661 + { 662 662 + struct i2c_client *client = i2c_verify_client(dev); 663 663 + int err; 664 664 + 665 665 + if (!client) 666 666 + return 0; 667 667 + 668 668 + if (client->adapter->bus_regulator) { 669 669 + err = regulator_enable(client->adapter->bus_regulator); 670 670 + if (err) 671 671 + return err; 672 672 + } 673 673 + 674 674 + return pm_generic_runtime_resume(&client->dev); 675 675 + } 676 676 + 677 677 + static int i2c_runtime_suspend(struct device *dev) 678 678 + { 679 679 + struct i2c_client *client = i2c_verify_client(dev); 680 680 + int err; 681 681 + 682 682 + if (!client) 683 683 + return 0; 684 684 + 685 685 + err = pm_generic_runtime_suspend(&client->dev); 686 686 + if (err) 687 687 + return err; 688 688 + 689 689 + if (client->adapter->bus_regulator) 690 690 + return regulator_disable(client->adapter->bus_regulator); 691 691 + return 0; 692 692 + } 693 693 + #endif 694 694 + 695 695 + static const struct dev_pm_ops i2c_device_pm = { 696 696 + SET_LATE_SYSTEM_SLEEP_PM_OPS(i2c_suspend_late, i2c_resume_early) 697 697 + SET_RUNTIME_PM_OPS(i2c_runtime_suspend, i2c_runtime_resume, NULL) 698 698 + }; 699 699 + 639 700 static void i2c_device_shutdown(struct device *dev) 640 701 { 641 702 struct i2c_client *client = i2c_verify_client(dev); ··· 726 627 driver = to_i2c_driver(dev->driver); 727 628 if (driver->shutdown) 728 629 driver->shutdown(client); 630 630 + else if (client->irq > 0) 631 631 + disable_irq(client->irq); 729 632 } 730 633 731 634 static void i2c_client_dev_release(struct device *dev) ··· 775 674 .probe = i2c_device_probe, 776 675 .remove = i2c_device_remove, 777 676 .shutdown = i2c_device_shutdown, 677 677 + .pm = &i2c_device_pm, 778 678 }; 779 679 EXPORT_SYMBOL_GPL(i2c_bus_type); 780 680

+10 -2

drivers/i2c/i2c-core-smbus.c

reviewed

··· 37 37 return (u8)(data >> 8); 38 38 } 39 39 40 40 - /* Incremental CRC8 over count bytes in the array pointed to by p */ 41 41 - static u8 i2c_smbus_pec(u8 crc, u8 *p, size_t count) 40 40 + /** 41 41 + * i2c_smbus_pec - Incremental CRC8 over the given input data array 42 42 + * @crc: previous return crc8 value 43 43 + * @p: pointer to data buffer. 44 44 + * @count: number of bytes in data buffer. 45 45 + * 46 46 + * Incremental CRC8 over count bytes in the array pointed to by p 47 47 + */ 48 48 + u8 i2c_smbus_pec(u8 crc, u8 *p, size_t count) 42 49 { 43 50 int i; 44 51 ··· 53 46 crc = crc8((crc ^ p[i]) << 8); 54 47 return crc; 55 48 } 49 49 + EXPORT_SYMBOL(i2c_smbus_pec); 56 50 57 51 /* Assume a 7-bit address, which is reasonable for SMBus */ 58 52 static u8 i2c_smbus_msg_pec(u8 pec, struct i2c_msg *msg)

+3

include/linux/i2c.h

reviewed

··· 15 15 #include <linux/device.h> /* for struct device */ 16 16 #include <linux/sched.h> /* for completion */ 17 17 #include <linux/mutex.h> 18 18 + #include <linux/regulator/consumer.h> 18 19 #include <linux/rtmutex.h> 19 20 #include <linux/irqdomain.h> /* for Host Notify IRQ */ 20 21 #include <linux/of.h> /* for struct device_node */ ··· 148 147 /* Now follow the 'nice' access routines. These also document the calling 149 148 conventions of i2c_smbus_xfer. */ 150 149 150 150 + u8 i2c_smbus_pec(u8 crc, u8 *p, size_t count); 151 151 s32 i2c_smbus_read_byte(const struct i2c_client *client); 152 152 s32 i2c_smbus_write_byte(const struct i2c_client *client, u8 value); 153 153 s32 i2c_smbus_read_byte_data(const struct i2c_client *client, u8 command); ··· 731 729 const struct i2c_adapter_quirks *quirks; 732 730 733 731 struct irq_domain *host_notify_domain; 732 732 + struct regulator *bus_regulator; 734 733 }; 735 734 #define to_i2c_adapter(d) container_of(d, struct i2c_adapter, dev) 736 735