Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'phy-for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy updates from Vinod Koul:
"New Support:
- Qualcomm Milos Synopsys eUSB2 PHY, SM8750 QMP phy support, M31
eUSB2 PHY driver
- Samsung Exynos990 usbdrd phy, Exynos7870 MIPI phy support
- Renesas RZ/V2N usb2-phy support
Updates:
- Bulk Yaml binding conversion By Rob H (too many to be listed)
- cadence: Sierra PCIe, USB PHY multilink configuration support
- Qualcomm refactoring of UFS PHY reset and UFS driver support for
phy calibrate API"
* tag 'phy-for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (74 commits)
phy: qcom: phy-qcom-m31: Update IPQ5332 M31 USB phy initialization sequence
dt-bindings: phy: Convert brcm,sr-usb-combo-phy to DT schema
dt-bindings: phy: Convert ti,da830-usb-phy to DT schema
dt-bindings: phy: marvell,mmp2-usb-phy: Drop status from the example
dt-bindings: phy: mixel, mipi-dsi-phy: Allow assigned-clock* properties
phy: exynos-mipi-video: correct cam0 sysreg property name for exynos7870
phy: qcom: phy-qcom-snps-eusb2: Update init sequence per HPG 1.0.2
phy: qcom: phy-qcom-snps-eusb2: Add missing write from init sequence
dt-bindings: phy: qcom,snps-eusb2: document the Milos Synopsys eUSB2 PHY
dt-bindings: usb: qcom,snps-dwc3: Add Milos compatible
phy: rockchip-pcie: Properly disable TEST_WRITE strobe signal
phy: rockchip-pcie: Enable all four lanes if required
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for QCS615
phy: qcom: qmp-combo: Add missing PLL (VCO) configuration on SM8750
phy: qcom: m31-eusb2: drop registration printk
phy: qcom: m31-eusb2: fix match data santity check
phy: qcom: qmp-pcie: Update PHY settings for QCS8300 & SA8775P
phy: qualcomm: phy-qcom-eusb2-repeater: Don't zero-out registers
dt-bindings: phy: qcom,snps-eusb2-repeater: Remove default tuning values
phy: mediatek: tphy: Cleanup and document slew calibration
...
+3264
-1128
+1
-1
Documentation/devicetree/bindings/mfd/motorola-cpcap.txt
+1
-1
Documentation/devicetree/bindings/mfd/motorola-cpcap.txt
···
19
19
- Documentation/devicetree/bindings/power/supply/cpcap-battery.yaml
20
20
- Documentation/devicetree/bindings/power/supply/cpcap-charger.yaml
21
21
- Documentation/devicetree/bindings/regulator/cpcap-regulator.txt
22
-
- Documentation/devicetree/bindings/phy/phy-cpcap-usb.txt
22
+
- Documentation/devicetree/bindings/phy/motorola,cpcap-usb-phy.yaml
23
23
- Documentation/devicetree/bindings/input/cpcap-pwrbutton.txt
24
24
- Documentation/devicetree/bindings/rtc/cpcap-rtc.txt
25
25
- Documentation/devicetree/bindings/leds/leds-cpcap.txt
+169
Documentation/devicetree/bindings/phy/apm,xgene-phy.yaml
+169
Documentation/devicetree/bindings/phy/apm,xgene-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/apm,xgene-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: APM X-Gene 15Gbps Multi-purpose PHY
8
+
9
+
maintainers:
10
+
- Khuong Dinh <khuong@os.amperecomputing.com>
11
+
12
+
description:
13
+
PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
14
+
PHY (pair of lanes) has its own node.
15
+
16
+
properties:
17
+
compatible:
18
+
items:
19
+
- const: apm,xgene-phy
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
'#phy-cells':
25
+
description:
26
+
Possible values are 0 (SATA), 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
27
+
const: 1
28
+
29
+
clocks:
30
+
maxItems: 1
31
+
32
+
apm,tx-eye-tuning:
33
+
description:
34
+
Manual control to fine tune the capture of the serial bit lines from the
35
+
automatic calibrated position. Two set of 3-tuple setting for each
36
+
supported link speed on the host. Range from 0 to 127 in unit of one bit
37
+
period.
38
+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
39
+
minItems: 2
40
+
maxItems: 2
41
+
items:
42
+
minItems: 3
43
+
maxItems: 3
44
+
items:
45
+
minimum: 0
46
+
maximum: 127
47
+
default: 10
48
+
49
+
apm,tx-eye-direction:
50
+
description:
51
+
Eye tuning manual control direction. 0 means sample data earlier than the
52
+
nominal sampling point. 1 means sample data later than the nominal
53
+
sampling point. Two set of 3-tuple setting for each supported link speed
54
+
on the host.
55
+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
56
+
minItems: 2
57
+
maxItems: 2
58
+
items:
59
+
minItems: 3
60
+
maxItems: 3
61
+
items:
62
+
enum: [0, 1]
63
+
default: 0
64
+
65
+
apm,tx-boost-gain:
66
+
description:
67
+
Frequency boost AC (LSB 3-bit) and DC (2-bit) gain control. Two set of
68
+
3-tuple setting for each supported link speed on the host. Range is
69
+
between 0 to 31 in unit of dB. Default is 3.
70
+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
71
+
minItems: 2
72
+
maxItems: 2
73
+
items:
74
+
minItems: 3
75
+
maxItems: 3
76
+
items:
77
+
minimum: 0
78
+
maximum: 31
79
+
80
+
apm,tx-amplitude:
81
+
description:
82
+
Amplitude control. Two set of 3-tuple setting for each supported link
83
+
speed on the host. Range is between 0 to 199500 in unit of uV.
84
+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
85
+
minItems: 2
86
+
maxItems: 2
87
+
items:
88
+
minItems: 3
89
+
maxItems: 3
90
+
items:
91
+
minimum: 0
92
+
maximum: 199500
93
+
default: 199500
94
+
95
+
apm,tx-pre-cursor1:
96
+
description:
97
+
1st pre-cursor emphasis taps control. Two set of 3-tuple setting for
98
+
each supported link speed on the host. Range is 0 to 273000 in unit of
99
+
uV.
100
+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
101
+
minItems: 2
102
+
maxItems: 2
103
+
items:
104
+
minItems: 3
105
+
maxItems: 3
106
+
items:
107
+
minimum: 0
108
+
maximum: 273000
109
+
default: 0
110
+
111
+
apm,tx-pre-cursor2:
112
+
description:
113
+
2nd pre-cursor emphasis taps control. Two set of 3-tuple setting for
114
+
each supported link speed on the host. Range is 0 to 127400 in unit uV.
115
+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
116
+
minItems: 2
117
+
maxItems: 2
118
+
items:
119
+
minItems: 3
120
+
maxItems: 3
121
+
items:
122
+
minimum: 0
123
+
maximum: 127400
124
+
default: 0
125
+
126
+
apm,tx-post-cursor:
127
+
description: |
128
+
Post-cursor emphasis taps control. Two set of 3-tuple setting for Gen1,
129
+
Gen2, and Gen3 link speeds. Range is between 0 to 31 in unit of 18.2mV.
130
+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
131
+
minItems: 2
132
+
maxItems: 2
133
+
items:
134
+
minItems: 3
135
+
maxItems: 3
136
+
items:
137
+
minimum: 0
138
+
maximum: 31
139
+
default: 0xf
140
+
141
+
apm,tx-speed:
142
+
description: >
143
+
Tx operating speed. One set of 3-tuple for each supported link speed on
144
+
the host:
145
+
146
+
0 = 1-2Gbps
147
+
1 = 2-4Gbps (1st tuple default)
148
+
2 = 4-8Gbps
149
+
3 = 8-15Gbps (2nd tuple default)
150
+
4 = 2.5-4Gbps
151
+
5 = 4-5Gbps
152
+
6 = 5-6Gbps
153
+
7 = 6-16Gbps (3rd tuple default).
154
+
155
+
$ref: /schemas/types.yaml#/definitions/uint32-array
156
+
minItems: 3
157
+
maxItems: 3
158
+
items:
159
+
maximum: 7
160
+
161
+
additionalProperties: false
162
+
163
+
examples:
164
+
- |
165
+
phy@1f21a000 {
166
+
compatible = "apm,xgene-phy";
167
+
reg = <0x1f21a000 0x100>;
168
+
#phy-cells = <1>;
169
+
};
-76
Documentation/devicetree/bindings/phy/apm-xgene-phy.txt
-76
Documentation/devicetree/bindings/phy/apm-xgene-phy.txt
···
1
-
* APM X-Gene 15Gbps Multi-purpose PHY nodes
2
-
3
-
PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
4
-
PHY (pair of lanes) has its own node.
5
-
6
-
Required properties:
7
-
- compatible : Shall be "apm,xgene-phy".
8
-
- reg : PHY memory resource is the SDS PHY access resource.
9
-
- #phy-cells : Shall be 1 as it expects one argument for setting
10
-
the mode of the PHY. Possible values are 0 (SATA),
11
-
1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
12
-
13
-
Optional properties:
14
-
- status : Shall be "ok" if enabled or "disabled" if disabled.
15
-
Default is "ok".
16
-
- clocks : Reference to the clock entry.
17
-
- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial
18
-
bit lines from the automatic calibrated position.
19
-
Two set of 3-tuple setting for each (up to 3)
20
-
supported link speed on the host. Range from 0 to
21
-
127 in unit of one bit period. Default is 10.
22
-
- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
23
-
data earlier than the nominal sampling point. 1 means
24
-
sample data later than the nominal sampling point.
25
-
Two set of 3-tuple setting for each (up to 3)
26
-
supported link speed on the host. Default is 0.
27
-
- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit)
28
-
gain control. Two set of 3-tuple setting for each
29
-
(up to 3) supported link speed on the host. Range is
30
-
between 0 to 31 in unit of dB. Default is 3.
31
-
- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for
32
-
each (up to 3) supported link speed on the host.
33
-
Range is between 0 to 199500 in unit of uV.
34
-
Default is 199500 uV.
35
-
- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of
36
-
3-tuple setting for each (up to 3) supported link
37
-
speed on the host. Range is 0 to 273000 in unit of
38
-
uV. Default is 0.
39
-
- apm,tx-pre-cursor2 : 2nd pre-cursor emphasis taps control. Two set of
40
-
3-tuple setting for each (up to 3) supported link
41
-
speed on the host. Range is 0 to 127400 in unit uV.
42
-
Default is 0x0.
43
-
- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of
44
-
3-tuple setting for Gen1, Gen2, and Gen3. Range is
45
-
between 0 to 0x1f in unit of 18.2mV. Default is 0xf.
46
-
- apm,tx-speed : Tx operating speed. One set of 3-tuple for each
47
-
supported link speed on the host.
48
-
0 = 1-2Gbps
49
-
1 = 2-4Gbps (1st tuple default)
50
-
2 = 4-8Gbps
51
-
3 = 8-15Gbps (2nd tuple default)
52
-
4 = 2.5-4Gbps
53
-
5 = 4-5Gbps
54
-
6 = 5-6Gbps
55
-
7 = 6-16Gbps (3rd tuple default)
56
-
57
-
NOTE: PHY override parameters are board specific setting.
58
-
59
-
Example:
60
-
phy1: phy@1f21a000 {
61
-
compatible = "apm,xgene-phy";
62
-
reg = <0x0 0x1f21a000 0x0 0x100>;
63
-
#phy-cells = <1>;
64
-
};
65
-
66
-
phy2: phy@1f22a000 {
67
-
compatible = "apm,xgene-phy";
68
-
reg = <0x0 0x1f22a000 0x0 0x100>;
69
-
#phy-cells = <1>;
70
-
};
71
-
72
-
phy3: phy@1f23a000 {
73
-
compatible = "apm,xgene-phy";
74
-
reg = <0x0 0x1f23a000 0x0 0x100>;
75
-
#phy-cells = <1>;
76
-
};
-36
Documentation/devicetree/bindings/phy/berlin-sata-phy.txt
-36
Documentation/devicetree/bindings/phy/berlin-sata-phy.txt
···
1
-
Berlin SATA PHY
2
-
---------------
3
-
4
-
Required properties:
5
-
- compatible: should be one of
6
-
"marvell,berlin2-sata-phy"
7
-
"marvell,berlin2q-sata-phy"
8
-
- address-cells: should be 1
9
-
- size-cells: should be 0
10
-
- phy-cells: from the generic PHY bindings, must be 1
11
-
- reg: address and length of the register
12
-
- clocks: reference to the clock entry
13
-
14
-
Sub-nodes:
15
-
Each PHY should be represented as a sub-node.
16
-
17
-
Sub-nodes required properties:
18
-
- reg: the PHY number
19
-
20
-
Example:
21
-
sata_phy: phy@f7e900a0 {
22
-
compatible = "marvell,berlin2q-sata-phy";
23
-
reg = <0xf7e900a0 0x200>;
24
-
clocks = <&chip CLKID_SATA>;
25
-
#address-cells = <1>;
26
-
#size-cells = <0>;
27
-
#phy-cells = <1>;
28
-
29
-
sata-phy@0 {
30
-
reg = <0>;
31
-
};
32
-
33
-
sata-phy@1 {
34
-
reg = <1>;
35
-
};
36
-
};
-16
Documentation/devicetree/bindings/phy/berlin-usb-phy.txt
-16
Documentation/devicetree/bindings/phy/berlin-usb-phy.txt
···
1
-
* Marvell Berlin USB PHY
2
-
3
-
Required properties:
4
-
- compatible: "marvell,berlin2-usb-phy" or "marvell,berlin2cd-usb-phy"
5
-
- reg: base address and length of the registers
6
-
- #phys-cells: should be 0
7
-
- resets: reference to the reset controller
8
-
9
-
Example:
10
-
11
-
usb-phy@f774000 {
12
-
compatible = "marvell,berlin2-usb-phy";
13
-
reg = <0xf774000 0x128>;
14
-
#phy-cells = <0>;
15
-
resets = <&chip 0x104 14>;
16
-
};
-30
Documentation/devicetree/bindings/phy/brcm,ns2-drd-phy.txt
-30
Documentation/devicetree/bindings/phy/brcm,ns2-drd-phy.txt
···
1
-
BROADCOM NORTHSTAR2 USB2 (DUAL ROLE DEVICE) PHY
2
-
3
-
Required properties:
4
-
- compatible: brcm,ns2-drd-phy
5
-
- reg: offset and length of the NS2 PHY related registers.
6
-
- reg-names
7
-
The below registers must be provided.
8
-
icfg - for DRD ICFG configurations
9
-
rst-ctrl - for DRD IDM reset
10
-
crmu-ctrl - for CRMU core vdd, PHY and PHY PLL reset
11
-
usb2-strap - for port over current polarity reversal
12
-
- #phy-cells: Must be 0. No args required.
13
-
- vbus-gpios: vbus gpio binding
14
-
- id-gpios: id gpio binding
15
-
16
-
Refer to phy/phy-bindings.txt for the generic PHY binding properties
17
-
18
-
Example:
19
-
usbdrd_phy: phy@66000960 {
20
-
#phy-cells = <0>;
21
-
compatible = "brcm,ns2-drd-phy";
22
-
reg = <0x66000960 0x24>,
23
-
<0x67012800 0x4>,
24
-
<0x6501d148 0x4>,
25
-
<0x664d0700 0x4>;
26
-
reg-names = "icfg", "rst-ctrl",
27
-
"crmu-ctrl", "usb2-strap";
28
-
id-gpios = <&gpio_g 30 0>;
29
-
vbus-gpios = <&gpio_g 31 0>;
30
-
};
+62
Documentation/devicetree/bindings/phy/brcm,ns2-drd-phy.yaml
+62
Documentation/devicetree/bindings/phy/brcm,ns2-drd-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/brcm,ns2-drd-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Broadcom Northstar2 USB2 Dual Role Device PHY
8
+
9
+
maintainers:
10
+
- Florian Fainelli <florian.fainelli@broadcom.com>
11
+
- Hauke Mehrtens <hauke@hauke-m.de>
12
+
- Rafał Miłecki <zajec5@gmail.com>
13
+
14
+
properties:
15
+
compatible:
16
+
const: brcm,ns2-drd-phy
17
+
18
+
reg:
19
+
items:
20
+
- description: DRD ICFG configurations
21
+
- description: DRD IDM reset
22
+
- description: CRMU core vdd, PHY and PHY PLL reset
23
+
- description: Port over current polarity reversal
24
+
25
+
reg-names:
26
+
items:
27
+
- const: icfg
28
+
- const: rst-ctrl
29
+
- const: crmu-ctrl
30
+
- const: usb2-strap
31
+
32
+
'#phy-cells':
33
+
const: 0
34
+
35
+
id-gpios:
36
+
maxItems: 1
37
+
description: ID GPIO line
38
+
39
+
vbus-gpios:
40
+
maxItems: 1
41
+
description: VBUS GPIO line
42
+
43
+
required:
44
+
- '#phy-cells'
45
+
- compatible
46
+
- reg
47
+
- reg-names
48
+
- id-gpios
49
+
- vbus-gpios
50
+
51
+
additionalProperties: false
52
+
53
+
examples:
54
+
- |
55
+
phy@66000960 {
56
+
#phy-cells = <0>;
57
+
compatible = "brcm,ns2-drd-phy";
58
+
reg = <0x66000960 0x24>, <0x67012800 0x4>, <0x6501d148 0x4>, <0x664d0700 0x4>;
59
+
reg-names = "icfg", "rst-ctrl", "crmu-ctrl", "usb2-strap";
60
+
id-gpios = <&gpio_g 30 0>;
61
+
vbus-gpios = <&gpio_g 31 0>;
62
+
};
-41
Documentation/devicetree/bindings/phy/brcm,sr-pcie-phy.txt
-41
Documentation/devicetree/bindings/phy/brcm,sr-pcie-phy.txt
···
1
-
Broadcom Stingray PCIe PHY
2
-
3
-
Required properties:
4
-
- compatible: must be "brcm,sr-pcie-phy"
5
-
- reg: base address and length of the PCIe SS register space
6
-
- brcm,sr-cdru: phandle to the CDRU syscon node
7
-
- brcm,sr-mhb: phandle to the MHB syscon node
8
-
- #phy-cells: Must be 1, denotes the PHY index
9
-
10
-
For PAXB based root complex, one can have a configuration of up to 8 PHYs
11
-
PHY index goes from 0 to 7
12
-
13
-
For the internal PAXC based root complex, PHY index is always 8
14
-
15
-
Example:
16
-
mhb: syscon@60401000 {
17
-
compatible = "brcm,sr-mhb", "syscon";
18
-
reg = <0 0x60401000 0 0x38c>;
19
-
};
20
-
21
-
cdru: syscon@6641d000 {
22
-
compatible = "brcm,sr-cdru", "syscon";
23
-
reg = <0 0x6641d000 0 0x400>;
24
-
};
25
-
26
-
pcie_phy: phy@40000000 {
27
-
compatible = "brcm,sr-pcie-phy";
28
-
reg = <0 0x40000000 0 0x800>;
29
-
brcm,sr-cdru = <&cdru>;
30
-
brcm,sr-mhb = <&mhb>;
31
-
#phy-cells = <1>;
32
-
};
33
-
34
-
/* users of the PCIe PHY */
35
-
36
-
pcie0: pcie@48000000 {
37
-
...
38
-
...
39
-
phys = <&pcie_phy 0>;
40
-
phy-names = "pcie-phy";
41
-
};
+46
Documentation/devicetree/bindings/phy/brcm,sr-pcie-phy.yaml
+46
Documentation/devicetree/bindings/phy/brcm,sr-pcie-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/brcm,sr-pcie-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Broadcom Stingray PCIe PHY
8
+
9
+
maintainers:
10
+
- Ray Jui <ray.jui@broadcom.com>
11
+
12
+
description: >
13
+
For PAXB based root complex, one can have a configuration of up to 8 PHYs.
14
+
PHY index goes from 0 to 7.
15
+
16
+
For the internal PAXC based root complex, PHY index is always 8.
17
+
18
+
properties:
19
+
compatible:
20
+
const: brcm,sr-pcie-phy
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
'#phy-cells':
26
+
const: 1
27
+
28
+
brcm,sr-cdru:
29
+
description: phandle to the CDRU syscon node
30
+
$ref: /schemas/types.yaml#/definitions/phandle
31
+
32
+
brcm,sr-mhb:
33
+
description: phandle to the MHB syscon node
34
+
$ref: /schemas/types.yaml#/definitions/phandle
35
+
36
+
additionalProperties: false
37
+
38
+
examples:
39
+
- |
40
+
phy@40000000 {
41
+
compatible = "brcm,sr-pcie-phy";
42
+
reg = <0x40000000 0x800>;
43
+
brcm,sr-cdru = <&cdru>;
44
+
brcm,sr-mhb = <&mhb>;
45
+
#phy-cells = <1>;
46
+
};
+65
Documentation/devicetree/bindings/phy/brcm,sr-usb-combo-phy.yaml
+65
Documentation/devicetree/bindings/phy/brcm,sr-usb-combo-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/brcm,sr-usb-combo-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Broadcom Stingray USB PHY
8
+
9
+
maintainers:
10
+
- Ray Jui <rjui@broadcom.com>
11
+
- Scott Branden <sbranden@broadcom.com>
12
+
13
+
properties:
14
+
compatible:
15
+
enum:
16
+
- brcm,sr-usb-combo-phy
17
+
- brcm,sr-usb-hs-phy
18
+
19
+
reg:
20
+
maxItems: 1
21
+
22
+
'#phy-cells':
23
+
description: PHY cell count indicating PHY type
24
+
enum: [ 0, 1 ]
25
+
26
+
required:
27
+
- compatible
28
+
- reg
29
+
- '#phy-cells'
30
+
31
+
allOf:
32
+
- if:
33
+
properties:
34
+
compatible:
35
+
contains:
36
+
const: brcm,sr-usb-combo-phy
37
+
then:
38
+
properties:
39
+
'#phy-cells':
40
+
const: 1
41
+
- if:
42
+
properties:
43
+
compatible:
44
+
contains:
45
+
const: brcm,sr-usb-hs-phy
46
+
then:
47
+
properties:
48
+
'#phy-cells':
49
+
const: 0
50
+
51
+
additionalProperties: false
52
+
53
+
examples:
54
+
- |
55
+
usb-phy@0 {
56
+
compatible = "brcm,sr-usb-combo-phy";
57
+
reg = <0x00000000 0x100>;
58
+
#phy-cells = <1>;
59
+
};
60
+
- |
61
+
usb-phy@20000 {
62
+
compatible = "brcm,sr-usb-hs-phy";
63
+
reg = <0x00020000 0x100>;
64
+
#phy-cells = <0>;
65
+
};
-32
Documentation/devicetree/bindings/phy/brcm,stingray-usb-phy.txt
-32
Documentation/devicetree/bindings/phy/brcm,stingray-usb-phy.txt
···
1
-
Broadcom Stingray USB PHY
2
-
3
-
Required properties:
4
-
- compatible : should be one of the listed compatibles
5
-
- "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
6
-
- "brcm,sr-usb-hs-phy" is a single HS PHY.
7
-
- reg: offset and length of the PHY blocks registers
8
-
- #phy-cells:
9
-
- Must be 1 for brcm,sr-usb-combo-phy as it expects one argument to indicate
10
-
the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
11
-
- Must be 0 for brcm,sr-usb-hs-phy.
12
-
13
-
Refer to phy/phy-bindings.txt for the generic PHY binding properties
14
-
15
-
Example:
16
-
usbphy0: usb-phy@0 {
17
-
compatible = "brcm,sr-usb-combo-phy";
18
-
reg = <0x00000000 0x100>;
19
-
#phy-cells = <1>;
20
-
};
21
-
22
-
usbphy1: usb-phy@10000 {
23
-
compatible = "brcm,sr-usb-combo-phy";
24
-
reg = <0x00010000 0x100>,
25
-
#phy-cells = <1>;
26
-
};
27
-
28
-
usbphy2: usb-phy@20000 {
29
-
compatible = "brcm,sr-usb-hs-phy";
30
-
reg = <0x00020000 0x100>,
31
-
#phy-cells = <0>;
32
-
};
-24
Documentation/devicetree/bindings/phy/dm816x-phy.txt
-24
Documentation/devicetree/bindings/phy/dm816x-phy.txt
···
1
-
Device tree binding documentation for am816x USB PHY
2
-
=========================
3
-
4
-
Required properties:
5
-
- compatible : should be "ti,dm816x-usb-phy"
6
-
- reg : offset and length of the PHY register set.
7
-
- reg-names : name for the phy registers
8
-
- clocks : phandle to the clock
9
-
- clock-names : name of the clock
10
-
- syscon: phandle for the syscon node to access misc registers
11
-
- #phy-cells : from the generic PHY bindings, must be 1
12
-
- syscon: phandle for the syscon node to access misc registers
13
-
14
-
Example:
15
-
16
-
usb_phy0: usb-phy@20 {
17
-
compatible = "ti,dm8168-usb-phy";
18
-
reg = <0x20 0x8>;
19
-
reg-names = "phy";
20
-
clocks = <&main_fapll 6>;
21
-
clock-names = "refclk";
22
-
#phy-cells = <0>;
23
-
syscon = <&scm_conf>;
24
-
};
+35
Documentation/devicetree/bindings/phy/hisilicon,hi6220-usb-phy.yaml
+35
Documentation/devicetree/bindings/phy/hisilicon,hi6220-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/hisilicon,hi6220-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Hisilicon hi6220 USB PHY
8
+
9
+
maintainers:
10
+
- Zhangfei Gao <zhangfei.gao@linaro.org>
11
+
12
+
properties:
13
+
compatible:
14
+
const: hisilicon,hi6220-usb-phy
15
+
16
+
'#phy-cells':
17
+
const: 0
18
+
19
+
phy-supply:
20
+
description: PHY power supply.
21
+
22
+
hisilicon,peripheral-syscon:
23
+
description: Phandle to the system controller for PHY control.
24
+
$ref: /schemas/types.yaml#/definitions/phandle
25
+
26
+
additionalProperties: false
27
+
28
+
examples:
29
+
- |
30
+
usbphy {
31
+
compatible = "hisilicon,hi6220-usb-phy";
32
+
#phy-cells = <0>;
33
+
phy-supply = <&fixed_5v_hub>;
34
+
hisilicon,peripheral-syscon = <&sys_ctrl>;
35
+
};
+48
Documentation/devicetree/bindings/phy/hisilicon,hix5hd2-sata-phy.yaml
+48
Documentation/devicetree/bindings/phy/hisilicon,hix5hd2-sata-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/hisilicon,hix5hd2-sata-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: HiSilicon hix5hd2 SATA PHY
8
+
9
+
maintainers:
10
+
- Jiancheng Xue <xuejiancheng@huawei.com>
11
+
12
+
properties:
13
+
compatible:
14
+
const: hisilicon,hix5hd2-sata-phy
15
+
16
+
reg:
17
+
maxItems: 1
18
+
19
+
'#phy-cells':
20
+
const: 0
21
+
22
+
hisilicon,peripheral-syscon:
23
+
description: Phandle of syscon used to control peripheral
24
+
$ref: /schemas/types.yaml#/definitions/phandle
25
+
26
+
hisilicon,power-reg:
27
+
description: Offset and bit number within peripheral-syscon register controlling SATA power supply
28
+
$ref: /schemas/types.yaml#/definitions/uint32-array
29
+
items:
30
+
- description: Offset within peripheral-syscon register
31
+
- description: Bit number controlling SATA power supply
32
+
33
+
required:
34
+
- compatible
35
+
- reg
36
+
- '#phy-cells'
37
+
38
+
additionalProperties: false
39
+
40
+
examples:
41
+
- |
42
+
phy@f9900000 {
43
+
compatible = "hisilicon,hix5hd2-sata-phy";
44
+
reg = <0xf9900000 0x10000>;
45
+
#phy-cells = <0>;
46
+
hisilicon,peripheral-syscon = <&peripheral_ctrl>;
47
+
hisilicon,power-reg = <0x8 10>;
48
+
};
+93
Documentation/devicetree/bindings/phy/hisilicon,inno-usb2-phy.yaml
+93
Documentation/devicetree/bindings/phy/hisilicon,inno-usb2-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/hisilicon,inno-usb2-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: HiSilicon INNO USB2 PHY
8
+
9
+
maintainers:
10
+
- Pengcheng Li <lpc.li@hisilicon.com>
11
+
12
+
description:
13
+
The INNO USB2 PHY device should be a child node of peripheral controller that
14
+
contains the PHY configuration register, and each device supports up to 2 PHY
15
+
ports which are represented as child nodes of INNO USB2 PHY device.
16
+
17
+
properties:
18
+
compatible:
19
+
enum:
20
+
- hisilicon,hi3798cv200-usb2-phy
21
+
- hisilicon,hi3798mv100-usb2-phy
22
+
- hisilicon,inno-usb2-phy
23
+
24
+
reg:
25
+
maxItems: 1
26
+
27
+
clocks:
28
+
maxItems: 1
29
+
30
+
resets:
31
+
maxItems: 1
32
+
33
+
"#address-cells":
34
+
const: 1
35
+
36
+
"#size-cells":
37
+
const: 0
38
+
39
+
patternProperties:
40
+
"^phy@[0-1]$":
41
+
description: PHY port subnode
42
+
type: object
43
+
additionalProperties: false
44
+
45
+
properties:
46
+
reg:
47
+
maximum: 1
48
+
49
+
"#phy-cells":
50
+
const: 0
51
+
52
+
resets:
53
+
maxItems: 1
54
+
55
+
required:
56
+
- reg
57
+
- "#phy-cells"
58
+
- resets
59
+
60
+
required:
61
+
- compatible
62
+
- reg
63
+
- clocks
64
+
- resets
65
+
- "#address-cells"
66
+
- "#size-cells"
67
+
68
+
additionalProperties: false
69
+
70
+
examples:
71
+
- |
72
+
#include <dt-bindings/clock/histb-clock.h>
73
+
74
+
usb2-phy@120 {
75
+
compatible = "hisilicon,hi3798cv200-usb2-phy";
76
+
reg = <0x120 0x4>;
77
+
clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
78
+
resets = <&crg 0xbc 4>;
79
+
#address-cells = <1>;
80
+
#size-cells = <0>;
81
+
82
+
phy@0 {
83
+
reg = <0>;
84
+
#phy-cells = <0>;
85
+
resets = <&crg 0xbc 8>;
86
+
};
87
+
88
+
phy@1 {
89
+
reg = <1>;
90
+
#phy-cells = <0>;
91
+
resets = <&crg 0xbc 9>;
92
+
};
93
+
};
-22
Documentation/devicetree/bindings/phy/hix5hd2-phy.txt
-22
Documentation/devicetree/bindings/phy/hix5hd2-phy.txt
···
1
-
Hisilicon hix5hd2 SATA PHY
2
-
-----------------------
3
-
4
-
Required properties:
5
-
- compatible: should be "hisilicon,hix5hd2-sata-phy"
6
-
- reg: offset and length of the PHY registers
7
-
- #phy-cells: must be 0
8
-
Refer to phy/phy-bindings.txt for the generic PHY binding properties
9
-
10
-
Optional Properties:
11
-
- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
12
-
- hisilicon,power-reg: offset and bit number within peripheral-syscon,
13
-
register of controlling sata power supply.
14
-
15
-
Example:
16
-
sata_phy: phy@f9900000 {
17
-
compatible = "hisilicon,hix5hd2-sata-phy";
18
-
reg = <0xf9900000 0x10000>;
19
-
#phy-cells = <0>;
20
-
hisilicon,peripheral-syscon = <&peripheral_ctrl>;
21
-
hisilicon,power-reg = <0x8 10>;
22
-
};
+62
Documentation/devicetree/bindings/phy/img,pistachio-usb-phy.yaml
+62
Documentation/devicetree/bindings/phy/img,pistachio-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/img,pistachio-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Imagination Pistachio USB PHY
8
+
9
+
maintainers:
10
+
- Andrew Bresticker <abrestic@chromium.org>
11
+
12
+
properties:
13
+
compatible:
14
+
const: img,pistachio-usb-phy
15
+
16
+
clocks:
17
+
maxItems: 1
18
+
19
+
clock-names:
20
+
items:
21
+
- const: usb_phy
22
+
23
+
'#phy-cells':
24
+
const: 0
25
+
26
+
phy-supply:
27
+
description: USB VBUS supply. Must supply 5.0V.
28
+
29
+
img,refclk:
30
+
description:
31
+
Reference clock source for the USB PHY. See
32
+
<dt-bindings/phy/phy-pistachio-usb.h> for valid values.
33
+
$ref: /schemas/types.yaml#/definitions/uint32
34
+
35
+
img,cr-top:
36
+
description: CR_TOP syscon phandle.
37
+
$ref: /schemas/types.yaml#/definitions/phandle
38
+
39
+
required:
40
+
- compatible
41
+
- clocks
42
+
- clock-names
43
+
- '#phy-cells'
44
+
- img,refclk
45
+
- img,cr-top
46
+
47
+
additionalProperties: false
48
+
49
+
examples:
50
+
- |
51
+
#include <dt-bindings/phy/phy-pistachio-usb.h>
52
+
#include <dt-bindings/clock/pistachio-clk.h>
53
+
54
+
usb-phy {
55
+
compatible = "img,pistachio-usb-phy";
56
+
clocks = <&clk_core CLK_USB_PHY>;
57
+
clock-names = "usb_phy";
58
+
#phy-cells = <0>;
59
+
phy-supply = <&usb_vbus>;
60
+
img,refclk = <REFCLK_CLK_CORE>;
61
+
img,cr-top = <&cr_top>;
62
+
};
-19
Documentation/devicetree/bindings/phy/keystone-usb-phy.txt
-19
Documentation/devicetree/bindings/phy/keystone-usb-phy.txt
···
1
-
TI Keystone USB PHY
2
-
3
-
Required properties:
4
-
- compatible: should be "ti,keystone-usbphy".
5
-
- #address-cells, #size-cells : should be '1' if the device has sub-nodes
6
-
with 'reg' property.
7
-
- reg : Address and length of the usb phy control register set.
8
-
9
-
The main purpose of this PHY driver is to enable the USB PHY reference clock
10
-
gate on the Keystone SOC for both the USB2 and USB3 PHY. Otherwise it is just
11
-
an NOP PHY driver. Hence this node is referenced as both the usb2 and usb3
12
-
phy node in the USB Glue layer driver node.
13
-
14
-
usb_phy: usb_phy@2620738 {
15
-
compatible = "ti,keystone-usbphy";
16
-
#address-cells = <1>;
17
-
#size-cells = <1>;
18
-
reg = <0x2620738 32>;
19
-
};
+71
Documentation/devicetree/bindings/phy/lantiq,ase-usb2-phy.yaml
+71
Documentation/devicetree/bindings/phy/lantiq,ase-usb2-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/lantiq,ase-usb2-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Lantiq XWAY SoC RCU USB 1.1/2.0 PHY
8
+
9
+
maintainers:
10
+
- Hauke Mehrtens <hauke@hauke-m.de>
11
+
12
+
description:
13
+
This node has to be a sub node of the Lantiq RCU block.
14
+
15
+
properties:
16
+
compatible:
17
+
items:
18
+
- enum:
19
+
- lantiq,ase-usb2-phy
20
+
- lantiq,danube-usb2-phy
21
+
- lantiq,xrx100-usb2-phy
22
+
- lantiq,xrx200-usb2-phy
23
+
- lantiq,xrx300-usb2-phy
24
+
25
+
reg:
26
+
items:
27
+
- description: Offset of the USB PHY configuration register
28
+
- description: Offset of the USB Analog configuration register
29
+
30
+
clocks:
31
+
maxItems: 1
32
+
33
+
clock-names:
34
+
items:
35
+
- const: phy
36
+
37
+
resets:
38
+
minItems: 1
39
+
maxItems: 2
40
+
41
+
reset-names:
42
+
minItems: 1
43
+
items:
44
+
- enum: [ phy, ctrl ]
45
+
- const: ctrl
46
+
47
+
'#phy-cells':
48
+
const: 0
49
+
50
+
required:
51
+
- compatible
52
+
- reg
53
+
- clocks
54
+
- clock-names
55
+
- resets
56
+
- reset-names
57
+
- '#phy-cells'
58
+
59
+
additionalProperties: false
60
+
61
+
examples:
62
+
- |
63
+
usb2-phy@18 {
64
+
compatible = "lantiq,xrx200-usb2-phy";
65
+
reg = <0x18 4>, <0x38 4>;
66
+
clocks = <&pmu 1>;
67
+
clock-names = "phy";
68
+
resets = <&reset1 4 4>, <&reset0 4 4>;
69
+
reset-names = "phy", "ctrl";
70
+
#phy-cells = <0>;
71
+
};
+40
Documentation/devicetree/bindings/phy/marvell,armada-375-usb-cluster.yaml
+40
Documentation/devicetree/bindings/phy/marvell,armada-375-usb-cluster.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/marvell,armada-375-usb-cluster.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Armada 375 USB Cluster
8
+
9
+
maintainers:
10
+
- Andrew Lunn <andrew@lunn.ch>
11
+
- Gregory Clement <gregory.clement@bootlin.com>
12
+
13
+
description:
14
+
Control register for the Armada 375 USB cluster, managing USB2 and USB3 features.
15
+
16
+
properties:
17
+
compatible:
18
+
const: marvell,armada-375-usb-cluster
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
'#phy-cells':
24
+
description: Number of PHY cells in specifier. 1 for USB2, 2 for USB3.
25
+
const: 1
26
+
27
+
required:
28
+
- compatible
29
+
- reg
30
+
- '#phy-cells'
31
+
32
+
additionalProperties: false
33
+
34
+
examples:
35
+
- |
36
+
usbcluster: usb-cluster@18400 {
37
+
compatible = "marvell,armada-375-usb-cluster";
38
+
reg = <0x18400 0x4>;
39
+
#phy-cells = <1>;
40
+
};
+83
Documentation/devicetree/bindings/phy/marvell,armada-380-comphy.yaml
+83
Documentation/devicetree/bindings/phy/marvell,armada-380-comphy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/marvell,armada-380-comphy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Marvell Armada 38x COMPHY controller
8
+
9
+
maintainers:
10
+
- Andrew Lunn <andrew@lunn.ch>
11
+
- Gregory Clement <gregory.clement@bootlin.com>
12
+
13
+
description:
14
+
This comphy controller can be found on Marvell Armada 38x. It provides a
15
+
number of shared PHYs used by various interfaces (network, sata, usb,
16
+
PCIe...).
17
+
18
+
properties:
19
+
compatible:
20
+
items:
21
+
- const: marvell,armada-380-comphy
22
+
23
+
reg:
24
+
items:
25
+
- description: COMPHY register location and length
26
+
- description: Configuration register location and length
27
+
28
+
reg-names:
29
+
items:
30
+
- const: comphy
31
+
- const: conf
32
+
33
+
'#address-cells':
34
+
const: 1
35
+
36
+
'#size-cells':
37
+
const: 0
38
+
39
+
patternProperties:
40
+
'^phy@[0-5]$':
41
+
description: A COMPHY lane
42
+
type: object
43
+
additionalProperties: false
44
+
45
+
properties:
46
+
reg:
47
+
maximum: 1
48
+
49
+
'#phy-cells':
50
+
description: Input port index for the PHY lane
51
+
const: 1
52
+
53
+
required:
54
+
- reg
55
+
- '#phy-cells'
56
+
57
+
required:
58
+
- compatible
59
+
- reg
60
+
- '#address-cells'
61
+
- '#size-cells'
62
+
63
+
additionalProperties: false
64
+
65
+
examples:
66
+
- |
67
+
comphy: phy@18300 {
68
+
compatible = "marvell,armada-380-comphy";
69
+
reg = <0x18300 0x100>, <0x18460 4>;
70
+
reg-names = "comphy", "conf";
71
+
#address-cells = <1>;
72
+
#size-cells = <0>;
73
+
74
+
cpm_comphy0: phy@0 {
75
+
reg = <0>;
76
+
#phy-cells = <1>;
77
+
};
78
+
79
+
cpm_comphy1: phy@1 {
80
+
reg = <1>;
81
+
#phy-cells = <1>;
82
+
};
83
+
};
+76
Documentation/devicetree/bindings/phy/marvell,berlin2-sata-phy.yaml
+76
Documentation/devicetree/bindings/phy/marvell,berlin2-sata-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/marvell,berlin2-sata-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Marvell Berlin SATA PHY
8
+
9
+
maintainers:
10
+
- Antoine Tenart <atenart@kernel.org>
11
+
12
+
properties:
13
+
compatible:
14
+
enum:
15
+
- marvell,berlin2-sata-phy
16
+
- marvell,berlin2q-sata-phy
17
+
18
+
reg:
19
+
maxItems: 1
20
+
21
+
clocks:
22
+
maxItems: 1
23
+
24
+
'#address-cells':
25
+
const: 1
26
+
27
+
'#size-cells':
28
+
const: 0
29
+
30
+
'#phy-cells':
31
+
const: 1
32
+
33
+
patternProperties:
34
+
'^sata-phy@[0-1]$':
35
+
description: A SATA PHY sub-node.
36
+
type: object
37
+
additionalProperties: false
38
+
39
+
properties:
40
+
reg:
41
+
maximum: 1
42
+
description: PHY index number.
43
+
44
+
required:
45
+
- reg
46
+
47
+
required:
48
+
- compatible
49
+
- reg
50
+
- clocks
51
+
- '#address-cells'
52
+
- '#size-cells'
53
+
- '#phy-cells'
54
+
55
+
additionalProperties: false
56
+
57
+
examples:
58
+
- |
59
+
#include <dt-bindings/clock/berlin2q.h>
60
+
61
+
phy@f7e900a0 {
62
+
compatible = "marvell,berlin2q-sata-phy";
63
+
reg = <0xf7e900a0 0x200>;
64
+
clocks = <&chip CLKID_SATA>;
65
+
#address-cells = <1>;
66
+
#size-cells = <0>;
67
+
#phy-cells = <1>;
68
+
69
+
sata-phy@0 {
70
+
reg = <0>;
71
+
};
72
+
73
+
sata-phy@1 {
74
+
reg = <1>;
75
+
};
76
+
};
+42
Documentation/devicetree/bindings/phy/marvell,berlin2-usb-phy.yaml
+42
Documentation/devicetree/bindings/phy/marvell,berlin2-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/marvell,berlin2-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Marvell Berlin USB PHY
8
+
9
+
maintainers:
10
+
- Antoine Tenart <atenart@kernel.org>
11
+
12
+
properties:
13
+
compatible:
14
+
enum:
15
+
- marvell,berlin2-usb-phy
16
+
- marvell,berlin2cd-usb-phy
17
+
18
+
reg:
19
+
maxItems: 1
20
+
21
+
"#phy-cells":
22
+
const: 0
23
+
24
+
resets:
25
+
maxItems: 1
26
+
27
+
required:
28
+
- compatible
29
+
- reg
30
+
- "#phy-cells"
31
+
- resets
32
+
33
+
additionalProperties: false
34
+
35
+
examples:
36
+
- |
37
+
usb-phy@f774000 {
38
+
compatible = "marvell,berlin2-usb-phy";
39
+
reg = <0xf774000 0x128>;
40
+
#phy-cells = <0>;
41
+
resets = <&chip 0x104 14>;
42
+
};
+154
Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml
+154
Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/marvell,comphy-cp110.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Marvell MVEBU COMPHY Controller
8
+
9
+
maintainers:
10
+
- Miquel Raynal <miquel.raynal@bootlin.com>
11
+
12
+
description: >
13
+
COMPHY controllers can be found on the following Marvell MVEBU SoCs:
14
+
15
+
* Armada 7k/8k (on the CP110)
16
+
* Armada 3700
17
+
18
+
It provides a number of shared PHYs used by various interfaces (network, SATA,
19
+
USB, PCIe...).
20
+
21
+
properties:
22
+
compatible:
23
+
enum:
24
+
- marvell,comphy-cp110
25
+
- marvell,comphy-a3700
26
+
27
+
reg:
28
+
minItems: 1
29
+
items:
30
+
- description: Generic COMPHY registers
31
+
- description: Lane 1 (PCIe/GbE) registers (Armada 3700)
32
+
- description: Lane 0 (USB3/GbE) registers (Armada 3700)
33
+
- description: Lane 2 (SATA/USB3) registers (Armada 3700)
34
+
35
+
reg-names:
36
+
minItems: 1
37
+
items:
38
+
- const: comphy
39
+
- const: lane1_pcie_gbe
40
+
- const: lane0_usb3_gbe
41
+
- const: lane2_sata_usb3
42
+
43
+
'#address-cells':
44
+
const: 1
45
+
46
+
'#size-cells':
47
+
const: 0
48
+
49
+
clocks:
50
+
maxItems: 3
51
+
description: Reference clocks for CP110; MG clock, MG Core clock, AXI clock
52
+
53
+
clock-names:
54
+
items:
55
+
- const: mg_clk
56
+
- const: mg_core_clk
57
+
- const: axi_clk
58
+
59
+
marvell,system-controller:
60
+
description: Phandle to the Marvell system controller (CP110 only)
61
+
$ref: /schemas/types.yaml#/definitions/phandle
62
+
63
+
patternProperties:
64
+
'^phy@[0-2]$':
65
+
description: A COMPHY lane child node
66
+
type: object
67
+
additionalProperties: false
68
+
69
+
properties:
70
+
reg:
71
+
description: COMPHY lane number
72
+
73
+
'#phy-cells':
74
+
const: 1
75
+
76
+
required:
77
+
- reg
78
+
- '#phy-cells'
79
+
80
+
required:
81
+
- compatible
82
+
- reg
83
+
84
+
additionalProperties: false
85
+
86
+
allOf:
87
+
- if:
88
+
properties:
89
+
compatible:
90
+
const: marvell,comphy-a3700
91
+
92
+
then:
93
+
properties:
94
+
clocks: false
95
+
clock-names: false
96
+
97
+
required:
98
+
- reg-names
99
+
100
+
else:
101
+
required:
102
+
- marvell,system-controller
103
+
104
+
examples:
105
+
- |
106
+
phy@120000 {
107
+
compatible = "marvell,comphy-cp110";
108
+
reg = <0x120000 0x6000>;
109
+
clocks = <&clk 1 5>, <&clk 1 6>, <&clk 1 18>;
110
+
clock-names = "mg_clk", "mg_core_clk", "axi_clk";
111
+
#address-cells = <1>;
112
+
#size-cells = <0>;
113
+
marvell,system-controller = <&syscon0>;
114
+
115
+
phy@0 {
116
+
reg = <0>;
117
+
#phy-cells = <1>;
118
+
};
119
+
120
+
phy@1 {
121
+
reg = <1>;
122
+
#phy-cells = <1>;
123
+
};
124
+
};
125
+
126
+
- |
127
+
phy@18300 {
128
+
compatible = "marvell,comphy-a3700";
129
+
reg = <0x18300 0x300>,
130
+
<0x1F000 0x400>,
131
+
<0x5C000 0x400>,
132
+
<0xe0178 0x8>;
133
+
reg-names = "comphy",
134
+
"lane1_pcie_gbe",
135
+
"lane0_usb3_gbe",
136
+
"lane2_sata_usb3";
137
+
#address-cells = <1>;
138
+
#size-cells = <0>;
139
+
140
+
comphy0: phy@0 {
141
+
reg = <0>;
142
+
#phy-cells = <1>;
143
+
};
144
+
145
+
comphy1: phy@1 {
146
+
reg = <1>;
147
+
#phy-cells = <1>;
148
+
};
149
+
150
+
comphy2: phy@2 {
151
+
reg = <2>;
152
+
#phy-cells = <1>;
153
+
};
154
+
};
+37
Documentation/devicetree/bindings/phy/marvell,mmp2-usb-phy.yaml
+37
Documentation/devicetree/bindings/phy/marvell,mmp2-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/marvell,mmp2-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Marvell MMP2/PXA USB PHY
8
+
9
+
maintainers:
10
+
- Lubomir Rintel <lkundrak@v3.sk>
11
+
12
+
properties:
13
+
compatible:
14
+
enum:
15
+
- marvell,mmp2-usb-phy
16
+
- marvell,pxa910-usb-phy
17
+
- marvell,pxa168-usb-phy
18
+
19
+
reg:
20
+
maxItems: 1
21
+
22
+
"#phy-cells":
23
+
const: 0
24
+
25
+
required:
26
+
- compatible
27
+
- "#phy-cells"
28
+
29
+
additionalProperties: false
30
+
31
+
examples:
32
+
- |
33
+
usbphy@d4207000 {
34
+
compatible = "marvell,mmp2-usb-phy";
35
+
reg = <0xd4207000 0x40>;
36
+
#phy-cells = <0>;
37
+
};
+47
Documentation/devicetree/bindings/phy/marvell,mvebu-sata-phy.yaml
+47
Documentation/devicetree/bindings/phy/marvell,mvebu-sata-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/marvell,mvebu-sata-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Marvell MVEBU SATA PHY
8
+
9
+
maintainers:
10
+
- Andrew Lunn <andrew@lunn.ch>
11
+
- Gregory Clement <gregory.clement@bootlin.com>
12
+
13
+
properties:
14
+
compatible:
15
+
const: marvell,mvebu-sata-phy
16
+
17
+
reg:
18
+
maxItems: 1
19
+
20
+
clocks:
21
+
maxItems: 1
22
+
23
+
clock-names:
24
+
items:
25
+
- const: sata
26
+
27
+
'#phy-cells':
28
+
const: 0
29
+
30
+
required:
31
+
- compatible
32
+
- reg
33
+
- clocks
34
+
- clock-names
35
+
- '#phy-cells'
36
+
37
+
additionalProperties: false
38
+
39
+
examples:
40
+
- |
41
+
sata-phy@84000 {
42
+
compatible = "marvell,mvebu-sata-phy";
43
+
reg = <0x84000 0x0334>;
44
+
clocks = <&gate_clk 15>;
45
+
clock-names = "sata";
46
+
#phy-cells = <0>;
47
+
};
-5
Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml
-5
Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml
+107
Documentation/devicetree/bindings/phy/motorola,cpcap-usb-phy.yaml
+107
Documentation/devicetree/bindings/phy/motorola,cpcap-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/motorola,cpcap-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Motorola CPCAP PMIC USB PHY
8
+
9
+
maintainers:
10
+
- Tony Lindgren <tony@atomide.com>
11
+
12
+
properties:
13
+
compatible:
14
+
enum:
15
+
- motorola,cpcap-usb-phy
16
+
- motorola,mapphone-cpcap-usb-phy
17
+
18
+
'#phy-cells':
19
+
const: 0
20
+
21
+
interrupts:
22
+
description: CPCAP PMIC interrupts used by the USB PHY
23
+
items:
24
+
- description: id_ground interrupt
25
+
- description: id_float interrupt
26
+
- description: se0conn interrupt
27
+
- description: vbusvld interrupt
28
+
- description: sessvld interrupt
29
+
- description: sessend interrupt
30
+
- description: se1 interrupt
31
+
- description: dm interrupt
32
+
- description: dp interrupt
33
+
34
+
interrupt-names:
35
+
description: Interrupt names
36
+
items:
37
+
- const: id_ground
38
+
- const: id_float
39
+
- const: se0conn
40
+
- const: vbusvld
41
+
- const: sessvld
42
+
- const: sessend
43
+
- const: se1
44
+
- const: dm
45
+
- const: dp
46
+
47
+
io-channels:
48
+
description: IIO ADC channels used by the USB PHY
49
+
items:
50
+
- description: vbus channel
51
+
- description: id channel
52
+
53
+
io-channel-names:
54
+
items:
55
+
- const: vbus
56
+
- const: id
57
+
58
+
vusb-supply: true
59
+
60
+
pinctrl-names:
61
+
items:
62
+
- const: default
63
+
- const: ulpi
64
+
- const: utmi
65
+
- const: uart
66
+
67
+
mode-gpios:
68
+
description: Optional GPIOs for configuring alternate modes
69
+
items:
70
+
- description: "mode selection GPIO #0"
71
+
- description: "mode selection GPIO #1"
72
+
73
+
required:
74
+
- compatible
75
+
- '#phy-cells'
76
+
- interrupts-extended
77
+
- interrupt-names
78
+
- io-channels
79
+
- io-channel-names
80
+
- vusb-supply
81
+
82
+
additionalProperties: false
83
+
84
+
examples:
85
+
- |
86
+
#include <dt-bindings/gpio/gpio.h>
87
+
88
+
phy {
89
+
compatible = "motorola,mapphone-cpcap-usb-phy";
90
+
#phy-cells = <0>;
91
+
interrupts-extended = <
92
+
&cpcap 15 0 &cpcap 14 0 &cpcap 28 0 &cpcap 19 0
93
+
&cpcap 18 0 &cpcap 17 0 &cpcap 16 0 &cpcap 49 0
94
+
&cpcap 48 1
95
+
>;
96
+
interrupt-names = "id_ground", "id_float", "se0conn", "vbusvld",
97
+
"sessvld", "sessend", "se1", "dm", "dp";
98
+
io-channels = <&cpcap_adc 2>, <&cpcap_adc 7>;
99
+
io-channel-names = "vbus", "id";
100
+
vusb-supply = <&vusb>;
101
+
pinctrl-0 = <&usb_gpio_mux_sel1 &usb_gpio_mux_sel2>;
102
+
pinctrl-1 = <&usb_ulpi_pins>;
103
+
pinctrl-2 = <&usb_utmi_pins>;
104
+
pinctrl-3 = <&uart3_pins>;
105
+
pinctrl-names = "default", "ulpi", "utmi", "uart";
106
+
mode-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, <&gpio1 0 GPIO_ACTIVE_HIGH>;
107
+
};
+81
Documentation/devicetree/bindings/phy/motorola,mapphone-mdm6600.yaml
+81
Documentation/devicetree/bindings/phy/motorola,mapphone-mdm6600.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/motorola,mapphone-mdm6600.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Motorola Mapphone MDM6600 USB PHY
8
+
9
+
maintainers:
10
+
- Tony Lindgren <tony@atomide.com>
11
+
12
+
properties:
13
+
compatible:
14
+
items:
15
+
- const: motorola,mapphone-mdm6600
16
+
17
+
enable-gpios:
18
+
description: GPIO to enable the USB PHY
19
+
maxItems: 1
20
+
21
+
power-gpios:
22
+
description: GPIO to power on the device
23
+
maxItems: 1
24
+
25
+
reset-gpios:
26
+
description: GPIO to reset the device
27
+
maxItems: 1
28
+
29
+
motorola,mode-gpios:
30
+
description: Two GPIOs to configure MDM6600 USB start-up mode for normal mode versus USB flashing mode
31
+
items:
32
+
- description: normal mode select GPIO
33
+
- description: USB flashing mode select GPIO
34
+
35
+
motorola,cmd-gpios:
36
+
description: Three GPIOs to control the power state of the MDM6600
37
+
items:
38
+
- description: power state control GPIO 0
39
+
- description: power state control GPIO 1
40
+
- description: power state control GPIO 2
41
+
42
+
motorola,status-gpios:
43
+
description: Three GPIOs to read the power state of the MDM6600
44
+
items:
45
+
- description: power state read GPIO 0
46
+
- description: power state read GPIO 1
47
+
- description: power state read GPIO 2
48
+
49
+
'#phy-cells':
50
+
const: 0
51
+
52
+
required:
53
+
- compatible
54
+
- enable-gpios
55
+
- power-gpios
56
+
- reset-gpios
57
+
- motorola,mode-gpios
58
+
- motorola,cmd-gpios
59
+
- motorola,status-gpios
60
+
61
+
additionalProperties: false
62
+
63
+
examples:
64
+
- |
65
+
#include <dt-bindings/gpio/gpio.h>
66
+
67
+
usb-phy {
68
+
compatible = "motorola,mapphone-mdm6600";
69
+
enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
70
+
power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
71
+
reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
72
+
motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>,
73
+
<&gpio5 21 GPIO_ACTIVE_HIGH>;
74
+
motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>,
75
+
<&gpio4 8 GPIO_ACTIVE_HIGH>,
76
+
<&gpio5 14 GPIO_ACTIVE_HIGH>;
77
+
motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>,
78
+
<&gpio2 21 GPIO_ACTIVE_HIGH>,
79
+
<&gpio2 23 GPIO_ACTIVE_HIGH>;
80
+
#phy-cells = <0>;
81
+
};
-48
Documentation/devicetree/bindings/phy/phy-armada38x-comphy.txt
-48
Documentation/devicetree/bindings/phy/phy-armada38x-comphy.txt
···
1
-
mvebu armada 38x comphy driver
2
-
------------------------------
3
-
4
-
This comphy controller can be found on Marvell Armada 38x. It provides a
5
-
number of shared PHYs used by various interfaces (network, sata, usb,
6
-
PCIe...).
7
-
8
-
Required properties:
9
-
10
-
- compatible: should be "marvell,armada-380-comphy"
11
-
- reg: should contain the comphy register location and length.
12
-
- #address-cells: should be 1.
13
-
- #size-cells: should be 0.
14
-
15
-
Optional properties:
16
-
17
-
- reg-names: must be "comphy" as the first name, and "conf".
18
-
- reg: must contain the comphy register location and length as the first
19
-
pair, followed by an optional configuration register address and
20
-
length pair.
21
-
22
-
A sub-node is required for each comphy lane provided by the comphy.
23
-
24
-
Required properties (child nodes):
25
-
26
-
- reg: comphy lane number.
27
-
- #phy-cells : from the generic phy bindings, must be 1. Defines the
28
-
input port to use for a given comphy lane.
29
-
30
-
Example:
31
-
32
-
comphy: phy@18300 {
33
-
compatible = "marvell,armada-380-comphy";
34
-
reg-names = "comphy", "conf";
35
-
reg = <0x18300 0x100>, <0x18460 4>;
36
-
#address-cells = <1>;
37
-
#size-cells = <0>;
38
-
39
-
cpm_comphy0: phy@0 {
40
-
reg = <0>;
41
-
#phy-cells = <1>;
42
-
};
43
-
44
-
cpm_comphy1: phy@1 {
45
-
reg = <1>;
46
-
#phy-cells = <1>;
47
-
};
48
-
};
-18
Documentation/devicetree/bindings/phy/phy-ath79-usb.txt
-18
Documentation/devicetree/bindings/phy/phy-ath79-usb.txt
···
1
-
* Atheros AR71XX/9XXX USB PHY
2
-
3
-
Required properties:
4
-
- compatible: "qca,ar7100-usb-phy"
5
-
- #phys-cells: should be 0
6
-
- reset-names: "phy"[, "suspend-override"]
7
-
- resets: references to the reset controllers
8
-
9
-
Example:
10
-
11
-
usb-phy {
12
-
compatible = "qca,ar7100-usb-phy";
13
-
14
-
reset-names = "phy", "suspend-override";
15
-
resets = <&rst 4>, <&rst 3>;
16
-
17
-
#phy-cells = <0>;
18
-
};
-40
Documentation/devicetree/bindings/phy/phy-cpcap-usb.txt
-40
Documentation/devicetree/bindings/phy/phy-cpcap-usb.txt
···
1
-
Motorola CPCAP PMIC USB PHY binding
2
-
3
-
Required properties:
4
-
compatible: Shall be either "motorola,cpcap-usb-phy" or
5
-
"motorola,mapphone-cpcap-usb-phy"
6
-
#phy-cells: Shall be 0
7
-
interrupts: CPCAP PMIC interrupts used by the USB PHY
8
-
interrupt-names: Interrupt names
9
-
io-channels: IIO ADC channels used by the USB PHY
10
-
io-channel-names: IIO ADC channel names
11
-
vusb-supply: Regulator for the PHY
12
-
13
-
Optional properties:
14
-
pinctrl: Optional alternate pin modes for the PHY
15
-
pinctrl-names: Names for optional pin modes
16
-
mode-gpios: Optional GPIOs for configuring alternate modes
17
-
18
-
Example:
19
-
cpcap_usb2_phy: phy {
20
-
compatible = "motorola,mapphone-cpcap-usb-phy";
21
-
pinctrl-0 = <&usb_gpio_mux_sel1 &usb_gpio_mux_sel2>;
22
-
pinctrl-1 = <&usb_ulpi_pins>;
23
-
pinctrl-2 = <&usb_utmi_pins>;
24
-
pinctrl-3 = <&uart3_pins>;
25
-
pinctrl-names = "default", "ulpi", "utmi", "uart";
26
-
#phy-cells = <0>;
27
-
interrupts-extended = <
28
-
&cpcap 15 0 &cpcap 14 0 &cpcap 28 0 &cpcap 19 0
29
-
&cpcap 18 0 &cpcap 17 0 &cpcap 16 0 &cpcap 49 0
30
-
&cpcap 48 1
31
-
>;
32
-
interrupt-names =
33
-
"id_ground", "id_float", "se0conn", "vbusvld",
34
-
"sessvld", "sessend", "se1", "dm", "dp";
35
-
mode-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH
36
-
&gpio1 0 GPIO_ACTIVE_HIGH>;
37
-
io-channels = <&cpcap_adc 2>, <&cpcap_adc 7>;
38
-
io-channel-names = "vbus", "id";
39
-
vusb-supply = <&vusb>;
40
-
};
-40
Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt
-40
Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt
···
1
-
TI DA8xx/OMAP-L1xx/AM18xx USB PHY
2
-
3
-
Required properties:
4
-
- compatible: must be "ti,da830-usb-phy".
5
-
- #phy-cells: must be 1.
6
-
7
-
This device controls the PHY for both the USB 1.1 OHCI and USB 2.0 OTG
8
-
controllers on DA8xx SoCs. Consumers of this device should use index 0 for
9
-
the USB 2.0 phy device and index 1 for the USB 1.1 phy device.
10
-
11
-
It also requires a "syscon" node with compatible = "ti,da830-cfgchip", "syscon"
12
-
to access the CFGCHIP2 register.
13
-
14
-
Example:
15
-
16
-
cfgchip: cfgchip@1417c {
17
-
compatible = "ti,da830-cfgchip", "syscon";
18
-
reg = <0x1417c 0x14>;
19
-
};
20
-
21
-
usb_phy: usb-phy {
22
-
compatible = "ti,da830-usb-phy";
23
-
#phy-cells = <1>;
24
-
};
25
-
26
-
usb20: usb@200000 {
27
-
compatible = "ti,da830-musb";
28
-
reg = <0x200000 0x1000>;
29
-
interrupts = <58>;
30
-
phys = <&usb_phy 0>;
31
-
phy-names = "usb-phy";
32
-
};
33
-
34
-
usb11: usb@225000 {
35
-
compatible = "ti,da830-ohci";
36
-
reg = <0x225000 0x1000>;
37
-
interrupts = <59>;
38
-
phys = <&usb_phy 1>;
39
-
phy-names = "usb-phy";
40
-
};
-16
Documentation/devicetree/bindings/phy/phy-hi6220-usb.txt
-16
Documentation/devicetree/bindings/phy/phy-hi6220-usb.txt
···
1
-
Hisilicon hi6220 usb PHY
2
-
-----------------------
3
-
4
-
Required properties:
5
-
- compatible: should be "hisilicon,hi6220-usb-phy"
6
-
- #phy-cells: must be 0
7
-
- hisilicon,peripheral-syscon: phandle of syscon used to control phy.
8
-
Refer to phy/phy-bindings.txt for the generic PHY binding properties
9
-
10
-
Example:
11
-
usb_phy: usbphy {
12
-
compatible = "hisilicon,hi6220-usb-phy";
13
-
#phy-cells = <0>;
14
-
phy-supply = <&fixed_5v_hub>;
15
-
hisilicon,peripheral-syscon = <&sys_ctrl>;
16
-
};
-71
Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
-71
Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
···
1
-
Device tree bindings for HiSilicon INNO USB2 PHY
2
-
3
-
Required properties:
4
-
- compatible: Should be one of the following strings:
5
-
"hisilicon,inno-usb2-phy",
6
-
"hisilicon,hi3798cv200-usb2-phy".
7
-
- reg: Should be the address space for PHY configuration register in peripheral
8
-
controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC.
9
-
- clocks: The phandle and clock specifier pair for INNO USB2 PHY device
10
-
reference clock.
11
-
- resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
12
-
signal.
13
-
- #address-cells: Must be 1.
14
-
- #size-cells: Must be 0.
15
-
16
-
The INNO USB2 PHY device should be a child node of peripheral controller that
17
-
contains the PHY configuration register, and each device supports up to 2 PHY
18
-
ports which are represented as child nodes of INNO USB2 PHY device.
19
-
20
-
Required properties for PHY port node:
21
-
- reg: The PHY port instance number.
22
-
- #phy-cells: Defined by generic PHY bindings. Must be 0.
23
-
- resets: The phandle and reset specifier pair for PHY port reset signal.
24
-
25
-
Refer to phy/phy-bindings.txt for the generic PHY binding properties
26
-
27
-
Example:
28
-
29
-
perictrl: peripheral-controller@8a20000 {
30
-
compatible = "hisilicon,hi3798cv200-perictrl", "simple-mfd";
31
-
reg = <0x8a20000 0x1000>;
32
-
#address-cells = <1>;
33
-
#size-cells = <1>;
34
-
ranges = <0x0 0x8a20000 0x1000>;
35
-
36
-
usb2_phy1: usb2-phy@120 {
37
-
compatible = "hisilicon,hi3798cv200-usb2-phy";
38
-
reg = <0x120 0x4>;
39
-
clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
40
-
resets = <&crg 0xbc 4>;
41
-
#address-cells = <1>;
42
-
#size-cells = <0>;
43
-
44
-
usb2_phy1_port0: phy@0 {
45
-
reg = <0>;
46
-
#phy-cells = <0>;
47
-
resets = <&crg 0xbc 8>;
48
-
};
49
-
50
-
usb2_phy1_port1: phy@1 {
51
-
reg = <1>;
52
-
#phy-cells = <0>;
53
-
resets = <&crg 0xbc 9>;
54
-
};
55
-
};
56
-
57
-
usb2_phy2: usb2-phy@124 {
58
-
compatible = "hisilicon,hi3798cv200-usb2-phy";
59
-
reg = <0x124 0x4>;
60
-
clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
61
-
resets = <&crg 0xbc 6>;
62
-
#address-cells = <1>;
63
-
#size-cells = <0>;
64
-
65
-
usb2_phy2_port0: phy@0 {
66
-
reg = <0>;
67
-
#phy-cells = <0>;
68
-
resets = <&crg 0xbc 10>;
69
-
};
70
-
};
71
-
};
-40
Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
-40
Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
···
1
-
Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
2
-
===========================================
3
-
4
-
This binding describes the USB PHY hardware provided by the RCU module on the
5
-
Lantiq XWAY SoCs.
6
-
7
-
This node has to be a sub node of the Lantiq RCU block.
8
-
9
-
-------------------------------------------------------------------------------
10
-
Required properties (controller (parent) node):
11
-
- compatible : Should be one of
12
-
"lantiq,ase-usb2-phy"
13
-
"lantiq,danube-usb2-phy"
14
-
"lantiq,xrx100-usb2-phy"
15
-
"lantiq,xrx200-usb2-phy"
16
-
"lantiq,xrx300-usb2-phy"
17
-
- reg : Defines the following sets of registers in the parent
18
-
syscon device
19
-
- Offset of the USB PHY configuration register
20
-
- Offset of the USB Analog configuration
21
-
register (only for xrx200 and xrx200)
22
-
- clocks : References to the (PMU) "phy" clk gate.
23
-
- clock-names : Must be "phy"
24
-
- resets : References to the RCU USB configuration reset bits.
25
-
- reset-names : Must be one of the following:
26
-
"phy" (optional)
27
-
"ctrl" (shared)
28
-
29
-
-------------------------------------------------------------------------------
30
-
Example for the USB PHYs on an xRX200 SoC:
31
-
usb_phy0: usb2-phy@18 {
32
-
compatible = "lantiq,xrx200-usb2-phy";
33
-
reg = <0x18 4>, <0x38 4>;
34
-
35
-
clocks = <&pmu PMU_GATE_USB0_PHY>;
36
-
clock-names = "phy";
37
-
resets = <&reset1 4 4>, <&reset0 4 4>;
38
-
reset-names = "phy", "ctrl";
39
-
#phy-cells = <0>;
40
-
};
-29
Documentation/devicetree/bindings/phy/phy-mapphone-mdm6600.txt
-29
Documentation/devicetree/bindings/phy/phy-mapphone-mdm6600.txt
···
1
-
Device tree binding documentation for Motorola Mapphone MDM6600 USB PHY
2
-
3
-
Required properties:
4
-
- compatible Must be "motorola,mapphone-mdm6600"
5
-
- enable-gpios GPIO to enable the USB PHY
6
-
- power-gpios GPIO to power on the device
7
-
- reset-gpios GPIO to reset the device
8
-
- motorola,mode-gpios Two GPIOs to configure MDM6600 USB start-up mode for
9
-
normal mode versus USB flashing mode
10
-
- motorola,cmd-gpios Three GPIOs to control the power state of the MDM6600
11
-
- motorola,status-gpios Three GPIOs to read the power state of the MDM6600
12
-
13
-
Example:
14
-
15
-
usb-phy {
16
-
compatible = "motorola,mapphone-mdm6600";
17
-
enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
18
-
power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
19
-
reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
20
-
motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>,
21
-
<&gpio5 21 GPIO_ACTIVE_HIGH>;
22
-
motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>,
23
-
<&gpio4 8 GPIO_ACTIVE_HIGH>,
24
-
<&gpio5 14 GPIO_ACTIVE_HIGH>;
25
-
motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>,
26
-
<&gpio2 21 GPIO_ACTIVE_HIGH>,
27
-
<&gpio2 23 GPIO_ACTIVE_HIGH>;
28
-
#phy-cells = <0>;
29
-
};
-94
Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
-94
Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
···
1
-
MVEBU comphy drivers
2
-
--------------------
3
-
4
-
COMPHY controllers can be found on the following Marvell MVEBU SoCs:
5
-
* Armada 7k/8k (on the CP110)
6
-
* Armada 3700
7
-
It provides a number of shared PHYs used by various interfaces (network, SATA,
8
-
USB, PCIe...).
9
-
10
-
Required properties:
11
-
12
-
- compatible: should be one of:
13
-
* "marvell,comphy-cp110" for Armada 7k/8k
14
-
* "marvell,comphy-a3700" for Armada 3700
15
-
- reg: should contain the COMPHY register(s) location(s) and length(s).
16
-
* 1 entry for Armada 7k/8k
17
-
* 4 entries for Armada 3700 along with the corresponding reg-names
18
-
properties, memory areas are:
19
-
* Generic COMPHY registers
20
-
* Lane 1 (PCIe/GbE)
21
-
* Lane 0 (USB3/GbE)
22
-
* Lane 2 (SATA/USB3)
23
-
- marvell,system-controller: should contain a phandle to the system
24
-
controller node (only for Armada 7k/8k)
25
-
- #address-cells: should be 1.
26
-
- #size-cells: should be 0.
27
-
28
-
Optional properlties:
29
-
30
-
- clocks: pointers to the reference clocks for this device (CP110 only),
31
-
consequently: MG clock, MG Core clock, AXI clock.
32
-
- clock-names: names of used clocks for CP110 only, must be :
33
-
"mg_clk", "mg_core_clk" and "axi_clk".
34
-
35
-
A sub-node is required for each comphy lane provided by the comphy.
36
-
37
-
Required properties (child nodes):
38
-
39
-
- reg: COMPHY lane number.
40
-
- #phy-cells : from the generic PHY bindings, must be 1. Defines the
41
-
input port to use for a given comphy lane.
42
-
43
-
Examples:
44
-
45
-
CP11X_LABEL(comphy): phy@120000 {
46
-
compatible = "marvell,comphy-cp110";
47
-
reg = <0x120000 0x6000>;
48
-
marvell,system-controller = <&CP11X_LABEL(syscon0)>;
49
-
clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
50
-
<&CP11X_LABEL(clk) 1 18>;
51
-
clock-names = "mg_clk", "mg_core_clk", "axi_clk";
52
-
#address-cells = <1>;
53
-
#size-cells = <0>;
54
-
55
-
CP11X_LABEL(comphy0): phy@0 {
56
-
reg = <0>;
57
-
#phy-cells = <1>;
58
-
};
59
-
60
-
CP11X_LABEL(comphy1): phy@1 {
61
-
reg = <1>;
62
-
#phy-cells = <1>;
63
-
};
64
-
};
65
-
66
-
comphy: phy@18300 {
67
-
compatible = "marvell,comphy-a3700";
68
-
reg = <0x18300 0x300>,
69
-
<0x1F000 0x400>,
70
-
<0x5C000 0x400>,
71
-
<0xe0178 0x8>;
72
-
reg-names = "comphy",
73
-
"lane1_pcie_gbe",
74
-
"lane0_usb3_gbe",
75
-
"lane2_sata_usb3";
76
-
#address-cells = <1>;
77
-
#size-cells = <0>;
78
-
79
-
80
-
comphy0: phy@0 {
81
-
reg = <0>;
82
-
#phy-cells = <1>;
83
-
};
84
-
85
-
comphy1: phy@1 {
86
-
reg = <1>;
87
-
#phy-cells = <1>;
88
-
};
89
-
90
-
comphy2: phy@2 {
91
-
reg = <2>;
92
-
#phy-cells = <1>;
93
-
};
94
-
};
-42
Documentation/devicetree/bindings/phy/phy-mvebu.txt
-42
Documentation/devicetree/bindings/phy/phy-mvebu.txt
···
1
-
* Marvell MVEBU SATA PHY
2
-
3
-
Power control for the SATA phy found on Marvell MVEBU SoCs.
4
-
5
-
This document extends the binding described in phy-bindings.txt
6
-
7
-
Required properties :
8
-
9
-
- reg : Offset and length of the register set for the SATA device
10
-
- compatible : Should be "marvell,mvebu-sata-phy"
11
-
- clocks : phandle of clock and specifier that supplies the device
12
-
- clock-names : Should be "sata"
13
-
14
-
Example:
15
-
sata-phy@84000 {
16
-
compatible = "marvell,mvebu-sata-phy";
17
-
reg = <0x84000 0x0334>;
18
-
clocks = <&gate_clk 15>;
19
-
clock-names = "sata";
20
-
#phy-cells = <0>;
21
-
};
22
-
23
-
Armada 375 USB cluster
24
-
----------------------
25
-
26
-
Armada 375 comes with an USB2 host and device controller and an USB3
27
-
controller. The USB cluster control register allows to manage common
28
-
features of both USB controllers.
29
-
30
-
Required properties:
31
-
32
-
- compatible: "marvell,armada-375-usb-cluster"
33
-
- reg: Should contain usb cluster register location and length.
34
-
- #phy-cells : from the generic phy bindings, must be 1. Possible
35
-
values are 1 (USB2), 2 (USB3).
36
-
37
-
Example:
38
-
usbcluster: usb-cluster@18400 {
39
-
compatible = "marvell,armada-375-usb-cluster";
40
-
reg = <0x18400 0x4>;
41
-
#phy-cells = <1>
42
-
};
-18
Documentation/devicetree/bindings/phy/phy-pxa-usb.txt
-18
Documentation/devicetree/bindings/phy/phy-pxa-usb.txt
···
1
-
Marvell PXA USB PHY
2
-
-------------------
3
-
4
-
Required properties:
5
-
- compatible: one of: "marvell,mmp2-usb-phy", "marvell,pxa910-usb-phy",
6
-
"marvell,pxa168-usb-phy",
7
-
- #phy-cells: must be 0
8
-
9
-
Example:
10
-
usb-phy: usbphy@d4207000 {
11
-
compatible = "marvell,mmp2-usb-phy";
12
-
reg = <0xd4207000 0x40>;
13
-
#phy-cells = <0>;
14
-
status = "okay";
15
-
};
16
-
17
-
This document explains the device tree binding. For general
18
-
information about PHY subsystem refer to Documentation/driver-api/phy/phy.rst
-29
Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
-29
Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt
···
1
-
IMG Pistachio USB PHY
2
-
=====================
3
-
4
-
Required properties:
5
-
--------------------
6
-
- compatible: Must be "img,pistachio-usb-phy".
7
-
- #phy-cells: Must be 0. See ./phy-bindings.txt for details.
8
-
- clocks: Must contain an entry for each entry in clock-names.
9
-
See ../clock/clock-bindings.txt for details.
10
-
- clock-names: Must include "usb_phy".
11
-
- img,cr-top: Must contain a phandle to the CR_TOP syscon node.
12
-
- img,refclk: Indicates the reference clock source for the USB PHY.
13
-
See <dt-bindings/phy/phy-pistachio-usb.h> for a list of valid values.
14
-
15
-
Optional properties:
16
-
--------------------
17
-
- phy-supply: USB VBUS supply. Must supply 5.0V.
18
-
19
-
Example:
20
-
--------
21
-
usb_phy: usb-phy {
22
-
compatible = "img,pistachio-usb-phy";
23
-
clocks = <&clk_core CLK_USB_PHY>;
24
-
clock-names = "usb_phy";
25
-
phy-supply = <&usb_vbus>;
26
-
img,refclk = <REFCLK_CLK_CORE>;
27
-
img,cr-top = <&cr_top>;
28
-
#phy-cells = <0>;
29
-
};
+49
Documentation/devicetree/bindings/phy/qca,ar7100-usb-phy.yaml
+49
Documentation/devicetree/bindings/phy/qca,ar7100-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/qca,ar7100-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Atheros AR71XX/9XXX USB PHY
8
+
9
+
maintainers:
10
+
- Alban Bedel <albeu@free.fr>
11
+
12
+
properties:
13
+
compatible:
14
+
items:
15
+
- const: qca,ar7100-usb-phy
16
+
17
+
reset-names:
18
+
description: Names of reset lines in order.
19
+
minItems: 1
20
+
items:
21
+
- const: phy
22
+
- const: suspend-override
23
+
24
+
resets:
25
+
description: References to the reset controllers.
26
+
minItems: 1
27
+
items:
28
+
- description: Reset controller for phy
29
+
- description: Reset controller for suspend-override
30
+
31
+
'#phy-cells':
32
+
const: 0
33
+
34
+
required:
35
+
- compatible
36
+
- reset-names
37
+
- resets
38
+
- '#phy-cells'
39
+
40
+
additionalProperties: false
41
+
42
+
examples:
43
+
- |
44
+
usb-phy {
45
+
compatible = "qca,ar7100-usb-phy";
46
+
reset-names = "phy", "suspend-override";
47
+
resets = <&rst 4>, <&rst 3>;
48
+
#phy-cells = <0>;
49
+
};
+79
Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml
+79
Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/qcom,m31-eusb2-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm M31 eUSB2 phy
8
+
9
+
maintainers:
10
+
- Wesley Cheng <quic_wcheng@quicinc.com>
11
+
12
+
description:
13
+
M31 based eUSB2 controller, which supports LS/FS/HS usb connectivity
14
+
on Qualcomm chipsets. It is paired with a eUSB2 repeater.
15
+
16
+
properties:
17
+
compatible:
18
+
items:
19
+
- enum:
20
+
- qcom,sm8750-m31-eusb2-phy
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
"#phy-cells":
26
+
const: 0
27
+
28
+
clocks:
29
+
items:
30
+
- description: reference clock
31
+
32
+
clock-names:
33
+
items:
34
+
- const: ref
35
+
36
+
resets:
37
+
maxItems: 1
38
+
39
+
phys:
40
+
maxItems: 1
41
+
description:
42
+
Phandle to eUSB2 repeater
43
+
44
+
vdd-supply:
45
+
description:
46
+
Phandle to 0.88V regulator supply to PHY digital circuit.
47
+
48
+
vdda12-supply:
49
+
description:
50
+
Phandle to 1.2V regulator supply to PHY refclk pll block.
51
+
52
+
required:
53
+
- compatible
54
+
- reg
55
+
- "#phy-cells"
56
+
- clocks
57
+
- clock-names
58
+
- resets
59
+
- vdd-supply
60
+
- vdda12-supply
61
+
62
+
additionalProperties: false
63
+
64
+
examples:
65
+
- |
66
+
usb_1_hsphy: phy@88e3000 {
67
+
compatible = "qcom,sm8750-m31-eusb2-phy";
68
+
reg = <0x88e3000 0x29c>;
69
+
70
+
clocks = <&tcsrcc_usb2_clkref_en>;
71
+
clock-names = "ref";
72
+
73
+
resets = <&gcc_qusb2phy_prim_bcr>;
74
+
75
+
#phy-cells = <0>;
76
+
77
+
vdd-supply = <&vreg_l2d_0p88>;
78
+
vdda12-supply = <&vreg_l3g_1p2>;
79
+
};
+1
-1
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+1
-1
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
···
145
145
compatible:
146
146
contains:
147
147
enum:
148
+
- qcom,qcs615-qmp-gen3x1-pcie-phy
148
149
- qcom,sar2130p-qmp-gen3x2-pcie-phy
149
150
- qcom,sc8180x-qmp-pcie-phy
150
151
- qcom,sdm845-qhp-pcie-phy
···
176
175
compatible:
177
176
contains:
178
177
enum:
179
-
- qcom,qcs615-qmp-gen3x1-pcie-phy
180
178
- qcom,sc8280xp-qmp-gen3x1-pcie-phy
181
179
- qcom,sc8280xp-qmp-gen3x2-pcie-phy
182
180
- qcom,sc8280xp-qmp-gen3x4-pcie-phy
+2
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
+2
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
···
29
29
- qcom,sm8450-qmp-usb3-dp-phy
30
30
- qcom,sm8550-qmp-usb3-dp-phy
31
31
- qcom,sm8650-qmp-usb3-dp-phy
32
+
- qcom,sm8750-qmp-usb3-dp-phy
32
33
- qcom,x1e80100-qmp-usb3-dp-phy
33
34
34
35
reg:
···
134
133
- qcom,sm6350-qmp-usb3-dp-phy
135
134
- qcom,sm8550-qmp-usb3-dp-phy
136
135
- qcom,sm8650-qmp-usb3-dp-phy
136
+
- qcom,sm8750-qmp-usb3-dp-phy
137
137
- qcom,x1e80100-qmp-usb3-dp-phy
138
138
then:
139
139
required:
+1
Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml
+1
Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml
-3
Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml
-3
Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml
···
39
39
description: High-Speed disconnect threshold
40
40
minimum: 0
41
41
maximum: 7
42
-
default: 0
43
42
44
43
qcom,tune-usb2-amplitude:
45
44
$ref: /schemas/types.yaml#/definitions/uint8
46
45
description: High-Speed transmit amplitude
47
46
minimum: 0
48
47
maximum: 15
49
-
default: 8
50
48
51
49
qcom,tune-usb2-preem:
52
50
$ref: /schemas/types.yaml#/definitions/uint8
53
51
description: High-Speed TX pre-emphasis tuning
54
52
minimum: 0
55
53
maximum: 7
56
-
default: 5
57
54
58
55
required:
59
56
- compatible
+4
Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
+4
Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
+25
-4
Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml
+25
-4
Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml
···
29
29
- samsung,s5pv210-mipi-video-phy
30
30
- samsung,exynos5420-mipi-video-phy
31
31
- samsung,exynos5433-mipi-video-phy
32
+
- samsung,exynos7870-mipi-video-phy
32
33
33
34
"#phy-cells":
34
35
const: 1
···
47
46
deprecated: true
48
47
description:
49
48
Phandle to PMU system controller interface, valid for
50
-
samsung,exynos5433-mipi-video-phy (if not a child of PMU).
49
+
samsung,exynos5433-mipi-video-phy and samsung,exynos7870-mipi-video-phy
50
+
(if not a child of PMU).
51
51
52
52
samsung,disp-sysreg:
53
53
$ref: /schemas/types.yaml#/definitions/phandle
54
54
description:
55
55
Phandle to DISP system controller interface, valid for
56
-
samsung,exynos5433-mipi-video-phy.
56
+
samsung,exynos5433-mipi-video-phy and samsung,exynos7870-mipi-video-phy.
57
57
58
58
samsung,cam0-sysreg:
59
59
$ref: /schemas/types.yaml#/definitions/phandle
60
60
description:
61
61
Phandle to CAM0 system controller interface, valid for
62
-
samsung,exynos5433-mipi-video-phy.
62
+
samsung,exynos5433-mipi-video-phy and samsung,exynos7870-mipi-video-phy.
63
63
64
64
samsung,cam1-sysreg:
65
65
$ref: /schemas/types.yaml#/definitions/phandle
···
86
84
samsung,disp-sysreg: false
87
85
samsung,cam0-sysreg: false
88
86
samsung,cam1-sysreg: false
89
-
else:
87
+
88
+
- if:
89
+
properties:
90
+
compatible:
91
+
contains:
92
+
const: samsung,exynos5433-mipi-video-phy
93
+
then:
90
94
properties:
91
95
syscon: false
92
96
required:
93
97
- samsung,disp-sysreg
94
98
- samsung,cam0-sysreg
95
99
- samsung,cam1-sysreg
100
+
101
+
- if:
102
+
properties:
103
+
compatible:
104
+
contains:
105
+
const: samsung,exynos7870-mipi-video-phy
106
+
then:
107
+
properties:
108
+
syscon: false
109
+
samsung,cam1-sysreg: false
110
+
required:
111
+
- samsung,disp-sysreg
112
+
- samsung,cam0-sysreg
96
113
97
114
additionalProperties: false
98
115
+2
Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
+2
Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
···
33
33
- samsung,exynos7-usbdrd-phy
34
34
- samsung,exynos7870-usbdrd-phy
35
35
- samsung,exynos850-usbdrd-phy
36
+
- samsung,exynos990-usbdrd-phy
36
37
37
38
clocks:
38
39
minItems: 1
···
218
217
- samsung,exynos5420-usbdrd-phy
219
218
- samsung,exynos7870-usbdrd-phy
220
219
- samsung,exynos850-usbdrd-phy
220
+
- samsung,exynos990-usbdrd-phy
221
221
then:
222
222
properties:
223
223
clocks:
+53
Documentation/devicetree/bindings/phy/st,spear1310-miphy.yaml
+53
Documentation/devicetree/bindings/phy/st,spear1310-miphy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/st,spear1310-miphy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: ST SPEAr miphy
8
+
9
+
maintainers:
10
+
- Pratyush Anand <pratyush.anand@gmail.com>
11
+
12
+
description:
13
+
ST Microelectronics SPEAr miphy is a phy controller supporting PCIe and SATA.
14
+
15
+
properties:
16
+
compatible:
17
+
enum:
18
+
- st,spear1310-miphy
19
+
- st,spear1340-miphy
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
misc:
25
+
description: Phandle for the syscon node to access misc registers.
26
+
$ref: /schemas/types.yaml#/definitions/phandle
27
+
28
+
'#phy-cells':
29
+
description: >
30
+
Cell[0] indicates interface type: 0 = SATA, 1 = PCIe.
31
+
const: 1
32
+
33
+
phy-id:
34
+
description: Instance id of the phy. Required when multiple PHYs are present.
35
+
$ref: /schemas/types.yaml#/definitions/uint32
36
+
37
+
required:
38
+
- compatible
39
+
- reg
40
+
- misc
41
+
- '#phy-cells'
42
+
43
+
additionalProperties: false
44
+
45
+
examples:
46
+
- |
47
+
miphy@1000 {
48
+
compatible = "st,spear1310-miphy";
49
+
reg = <0x1000 0x100>;
50
+
misc = <&syscon>;
51
+
#phy-cells = <1>;
52
+
phy-id = <0>;
53
+
};
-15
Documentation/devicetree/bindings/phy/st-spear-miphy.txt
-15
Documentation/devicetree/bindings/phy/st-spear-miphy.txt
···
1
-
ST SPEAr miphy DT details
2
-
=========================
3
-
4
-
ST Microelectronics SPEAr miphy is a phy controller supporting PCIe and SATA.
5
-
6
-
Required properties:
7
-
- compatible : should be "st,spear1310-miphy" or "st,spear1340-miphy"
8
-
- reg : offset and length of the PHY register set.
9
-
- misc: phandle for the syscon node to access misc registers
10
-
- #phy-cells : from the generic PHY bindings, must be 1.
11
-
- cell[1]: 0 if phy used for SATA, 1 for PCIe.
12
-
13
-
Optional properties:
14
-
- phy-id: Instance id of the phy. Only required when there are multiple phys
15
-
present on a implementation.
+53
Documentation/devicetree/bindings/phy/ti,da830-usb-phy.yaml
+53
Documentation/devicetree/bindings/phy/ti,da830-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/ti,da830-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: TI DA8xx/OMAP-L1xx/AM18xx USB PHY
8
+
9
+
maintainers:
10
+
- David Lechner <david@lechnology.com>
11
+
12
+
description: >
13
+
This device controls the PHY for both the USB 1.1 OHCI and USB 2.0 OTG
14
+
controllers on DA8xx SoCs.
15
+
16
+
It also requires a "syscon" node with compatible = "ti,da830-cfgchip", "syscon"
17
+
to access the CFGCHIP2 register.
18
+
19
+
properties:
20
+
compatible:
21
+
items:
22
+
- const: ti,da830-usb-phy
23
+
24
+
'#phy-cells':
25
+
const: 1
26
+
description:
27
+
Consumers of this device should use index 0 for the USB 2.0 phy device and
28
+
index 1 for the USB 1.1 phy device.
29
+
30
+
clocks:
31
+
maxItems: 2
32
+
33
+
clock-names:
34
+
items:
35
+
- const: usb0_clk48
36
+
- const: usb1_clk48
37
+
38
+
required:
39
+
- compatible
40
+
- '#phy-cells'
41
+
- clocks
42
+
- clock-names
43
+
44
+
additionalProperties: false
45
+
46
+
examples:
47
+
- |
48
+
usb-phy {
49
+
compatible = "ti,da830-usb-phy";
50
+
#phy-cells = <1>;
51
+
clocks = <&usb_phy_clk 0>, <&usb_phy_clk 1>;
52
+
clock-names = "usb0_clk48", "usb1_clk48";
53
+
};
+58
Documentation/devicetree/bindings/phy/ti,dm8168-usb-phy.yaml
+58
Documentation/devicetree/bindings/phy/ti,dm8168-usb-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/ti,dm8168-usb-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: TI DM8168 USB PHY
8
+
9
+
maintainers:
10
+
- Tony Lindgren <tony@atomide.com>
11
+
12
+
properties:
13
+
compatible:
14
+
const: ti,dm8168-usb-phy
15
+
16
+
reg:
17
+
maxItems: 1
18
+
19
+
reg-names:
20
+
items:
21
+
- const: phy
22
+
23
+
clocks:
24
+
maxItems: 1
25
+
26
+
clock-names:
27
+
items:
28
+
- const: refclk
29
+
30
+
'#phy-cells':
31
+
const: 0
32
+
33
+
syscon:
34
+
$ref: /schemas/types.yaml#/definitions/phandle
35
+
description: Phandle for the syscon node to access misc registers.
36
+
37
+
required:
38
+
- compatible
39
+
- reg
40
+
- reg-names
41
+
- clocks
42
+
- clock-names
43
+
- '#phy-cells'
44
+
- syscon
45
+
46
+
additionalProperties: false
47
+
48
+
examples:
49
+
- |
50
+
usb-phy@20 {
51
+
compatible = "ti,dm8168-usb-phy";
52
+
reg = <0x20 0x8>;
53
+
reg-names = "phy";
54
+
clocks = <&main_fapll 6>;
55
+
clock-names = "refclk";
56
+
#phy-cells = <0>;
57
+
syscon = <&scm_conf>;
58
+
};
+37
Documentation/devicetree/bindings/phy/ti,keystone-usbphy.yaml
+37
Documentation/devicetree/bindings/phy/ti,keystone-usbphy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/ti,keystone-usbphy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: TI Keystone USB PHY
8
+
9
+
maintainers:
10
+
- Nishanth Menon <nm@ti.com>
11
+
- Santosh Shilimkar <ssantosh@kernel.org>
12
+
13
+
description:
14
+
The main purpose of this PHY driver is to enable the USB PHY reference clock
15
+
gate on the Keystone SOC for both the USB2 and USB3 PHY. Otherwise it is just
16
+
an NOP PHY driver. Hence this node is referenced as both the usb2 and usb3
17
+
phy node in the USB Glue layer driver node.
18
+
19
+
properties:
20
+
compatible:
21
+
const: ti,keystone-usbphy
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
required:
27
+
- compatible
28
+
- reg
29
+
30
+
additionalProperties: false
31
+
32
+
examples:
33
+
- |
34
+
usb-phy@2620738 {
35
+
compatible = "ti,keystone-usbphy";
36
+
reg = <0x2620738 32>;
37
+
};
+3
Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
+3
Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
···
32
32
- qcom,ipq8064-dwc3
33
33
- qcom,ipq8074-dwc3
34
34
- qcom,ipq9574-dwc3
35
+
- qcom,milos-dwc3
35
36
- qcom,msm8953-dwc3
36
37
- qcom,msm8994-dwc3
37
38
- qcom,msm8996-dwc3
···
339
338
compatible:
340
339
contains:
341
340
enum:
341
+
- qcom,milos-dwc3
342
342
- qcom,qcm2290-dwc3
343
343
- qcom,qcs615-dwc3
344
344
- qcom,sar2130p-dwc3
···
455
453
compatible:
456
454
contains:
457
455
enum:
456
+
- qcom,milos-dwc3
458
457
- qcom,x1e80100-dwc3
459
458
then:
460
459
properties:
+2
-2
MAINTAINERS
+2
-2
MAINTAINERS
···
3918
3918
S: Maintained
3919
3919
W: https://github.com/AlbanBedel/linux
3920
3920
T: git https://github.com/AlbanBedel/linux.git
3921
-
F: Documentation/devicetree/bindings/phy/phy-ath79-usb.txt
3921
+
F: Documentation/devicetree/bindings/phy/qca,ar7100-usb-phy.yaml
3922
3922
F: drivers/phy/qualcomm/phy-ath79-usb.c
3923
3923
3924
3924
ATHEROS ATH GENERIC UTILITIES
···
14700
14700
M: Miquel Raynal <miquel.raynal@bootlin.com>
14701
14701
S: Maintained
14702
14702
F: Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml
14703
-
F: Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
14703
+
F: Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml
14704
14704
F: drivers/phy/marvell/phy-mvebu-a3700-comphy.c
14705
14705
F: drivers/phy/marvell/phy-mvebu-a3700-utmi.c
14706
14706
-2
drivers/phy/broadcom/phy-bcm-ns2-pcie.c
-2
drivers/phy/broadcom/phy-bcm-ns2-pcie.c
-1
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
-1
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
-2
drivers/phy/broadcom/phy-bcm-sr-pcie.c
-2
drivers/phy/broadcom/phy-bcm-sr-pcie.c
+1
-1
drivers/phy/broadcom/phy-brcm-sata.c
+1
-1
drivers/phy/broadcom/phy-brcm-sata.c
+180
drivers/phy/cadence/phy-cadence-sierra.c
+180
drivers/phy/cadence/phy-cadence-sierra.c
···
58
58
#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2
59
59
#define SIERRA_CMN_PLLLC1_FBDIV_INT_PREG 0xC3
60
60
#define SIERRA_CMN_PLLLC1_DCOCAL_CTRL_PREG 0xC5
61
+
#define SIERRA_CMN_PLLLC1_MODE_PREG 0xC8
62
+
#define SIERRA_CMN_PLLLC1_LF_COEFF_MODE1_PREG 0xC9
61
63
#define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG 0xCA
62
64
#define SIERRA_CMN_PLLLC1_CLK0_PREG 0xCE
65
+
#define SIERRA_CMN_PLLLC1_BWCAL_MODE1_PREG 0xCF
63
66
#define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG 0xD0
64
67
#define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG 0xE2
65
68
···
1544
1541
cdns_sierra_clk_unregister(phy);
1545
1542
}
1546
1543
1544
+
/* USB refclk 100MHz, 20b, SuperSpeed opt2, ext ssc, PLL LC1, multilink */
1545
+
static const struct cdns_reg_pairs usb_100_ext_ssc_plllc1_cmn_regs[] = {
1546
+
{0x002D, SIERRA_CMN_PLLLC1_FBDIV_INT_PREG},
1547
+
{0x2086, SIERRA_CMN_PLLLC1_LF_COEFF_MODE1_PREG},
1548
+
{0x2086, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG},
1549
+
{0x1005, SIERRA_CMN_PLLLC1_CLK0_PREG},
1550
+
{0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE1_PREG},
1551
+
{0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG},
1552
+
{0x0000, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG}
1553
+
};
1554
+
1555
+
/* USB refclk 100MHz, 20b, SuperSpeed opt2, int ssc, PLL LC1, multilink */
1556
+
static const struct cdns_reg_pairs usb_100_int_ssc_plllc1_cmn_regs[] = {
1557
+
{0x002D, SIERRA_CMN_PLLLC1_FBDIV_INT_PREG},
1558
+
{0x000E, SIERRA_CMN_PLLLC1_MODE_PREG},
1559
+
{0x1005, SIERRA_CMN_PLLLC1_CLK0_PREG}
1560
+
};
1561
+
1562
+
static const struct cdns_reg_pairs usb_100_ml_ln_regs[] = {
1563
+
{0xFE0A, SIERRA_DET_STANDEC_A_PREG},
1564
+
{0x000F, SIERRA_DET_STANDEC_B_PREG},
1565
+
{0x55A5, SIERRA_DET_STANDEC_C_PREG},
1566
+
{0x69AD, SIERRA_DET_STANDEC_D_PREG},
1567
+
{0x0241, SIERRA_DET_STANDEC_E_PREG},
1568
+
{0x0010, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
1569
+
{0x0014, SIERRA_PSM_A0IN_TMR_PREG},
1570
+
{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
1571
+
{0x0004, SIERRA_PSC_LN_A3_PREG},
1572
+
{0x0004, SIERRA_PSC_LN_IDLE_PREG},
1573
+
{0x001F, SIERRA_PSC_TX_A0_PREG},
1574
+
{0x0007, SIERRA_PSC_TX_A1_PREG},
1575
+
{0x0003, SIERRA_PSC_TX_A2_PREG},
1576
+
{0x0003, SIERRA_PSC_TX_A3_PREG},
1577
+
{0x0FFF, SIERRA_PSC_RX_A0_PREG},
1578
+
{0x0619, SIERRA_PSC_RX_A1_PREG},
1579
+
{0x0003, SIERRA_PSC_RX_A2_PREG},
1580
+
{0x0001, SIERRA_PSC_RX_A3_PREG},
1581
+
{0x0606, SIERRA_PLLCTRL_FBDIV_MODE01_PREG},
1582
+
{0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},
1583
+
{0x0003, SIERRA_PLLCTRL_GEN_A_PREG},
1584
+
{0x0406, SIERRA_PLLCTRL_GEN_D_PREG},
1585
+
{0x5211, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
1586
+
{0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG},
1587
+
{0x2512, SIERRA_DFE_BIASTRIM_PREG},
1588
+
{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
1589
+
{0x823E, SIERRA_CLKPATHCTRL_TMR_PREG},
1590
+
{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
1591
+
{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
1592
+
{0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
1593
+
{0x023F, SIERRA_RX_CTLE_MAINTENANCE_PREG},
1594
+
{0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},
1595
+
{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
1596
+
{0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
1597
+
{0x8452, SIERRA_CTLELUT_CTRL_PREG},
1598
+
{0x4121, SIERRA_DFE_ECMP_RATESEL_PREG},
1599
+
{0x4121, SIERRA_DFE_SMP_RATESEL_PREG},
1600
+
{0x0002, SIERRA_DEQ_PHALIGN_CTRL},
1601
+
{0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG},
1602
+
{0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG},
1603
+
{0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
1604
+
{0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG},
1605
+
{0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG},
1606
+
{0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG},
1607
+
{0xA9A9, SIERRA_DEQ_VGATUNE_CTRL_PREG},
1608
+
{0x0014, SIERRA_DEQ_GLUT0},
1609
+
{0x0014, SIERRA_DEQ_GLUT1},
1610
+
{0x0014, SIERRA_DEQ_GLUT2},
1611
+
{0x0014, SIERRA_DEQ_GLUT3},
1612
+
{0x0014, SIERRA_DEQ_GLUT4},
1613
+
{0x0014, SIERRA_DEQ_GLUT5},
1614
+
{0x0014, SIERRA_DEQ_GLUT6},
1615
+
{0x0014, SIERRA_DEQ_GLUT7},
1616
+
{0x0014, SIERRA_DEQ_GLUT8},
1617
+
{0x0014, SIERRA_DEQ_GLUT9},
1618
+
{0x0014, SIERRA_DEQ_GLUT10},
1619
+
{0x0014, SIERRA_DEQ_GLUT11},
1620
+
{0x0014, SIERRA_DEQ_GLUT12},
1621
+
{0x0014, SIERRA_DEQ_GLUT13},
1622
+
{0x0014, SIERRA_DEQ_GLUT14},
1623
+
{0x0014, SIERRA_DEQ_GLUT15},
1624
+
{0x0014, SIERRA_DEQ_GLUT16},
1625
+
{0x0BAE, SIERRA_DEQ_ALUT0},
1626
+
{0x0AEB, SIERRA_DEQ_ALUT1},
1627
+
{0x0A28, SIERRA_DEQ_ALUT2},
1628
+
{0x0965, SIERRA_DEQ_ALUT3},
1629
+
{0x08A2, SIERRA_DEQ_ALUT4},
1630
+
{0x07DF, SIERRA_DEQ_ALUT5},
1631
+
{0x071C, SIERRA_DEQ_ALUT6},
1632
+
{0x0659, SIERRA_DEQ_ALUT7},
1633
+
{0x0596, SIERRA_DEQ_ALUT8},
1634
+
{0x0514, SIERRA_DEQ_ALUT9},
1635
+
{0x0492, SIERRA_DEQ_ALUT10},
1636
+
{0x0410, SIERRA_DEQ_ALUT11},
1637
+
{0x038E, SIERRA_DEQ_ALUT12},
1638
+
{0x030C, SIERRA_DEQ_ALUT13},
1639
+
{0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG},
1640
+
{0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG},
1641
+
{0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
1642
+
{0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1643
+
{0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG},
1644
+
{0x0033, SIERRA_DEQ_PICTRL_PREG},
1645
+
{0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG},
1646
+
{0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG},
1647
+
{0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG},
1648
+
{0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG},
1649
+
{0x0005, SIERRA_LFPSDET_SUPPORT_PREG},
1650
+
{0x000F, SIERRA_LFPSFILT_NS_PREG},
1651
+
{0x0009, SIERRA_LFPSFILT_RD_PREG},
1652
+
{0x0001, SIERRA_LFPSFILT_MP_PREG},
1653
+
{0x8013, SIERRA_SDFILT_H2L_A_PREG},
1654
+
{0x8009, SIERRA_SDFILT_L2H_PREG},
1655
+
{0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG},
1656
+
{0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG},
1657
+
{0x4243, SIERRA_RXBUFFER_DFECTRL_PREG}
1658
+
};
1659
+
1660
+
static const struct cdns_sierra_vals usb_100_ext_ssc_plllc1_cmn_vals = {
1661
+
.reg_pairs = usb_100_ext_ssc_plllc1_cmn_regs,
1662
+
.num_regs = ARRAY_SIZE(usb_100_ext_ssc_plllc1_cmn_regs),
1663
+
};
1664
+
1665
+
static const struct cdns_sierra_vals usb_100_int_ssc_plllc1_cmn_vals = {
1666
+
.reg_pairs = usb_100_int_ssc_plllc1_cmn_regs,
1667
+
.num_regs = ARRAY_SIZE(usb_100_int_ssc_plllc1_cmn_regs),
1668
+
};
1669
+
1670
+
static const struct cdns_sierra_vals usb_100_ml_ln_vals = {
1671
+
.reg_pairs = usb_100_ml_ln_regs,
1672
+
.num_regs = ARRAY_SIZE(usb_100_ml_ln_regs),
1673
+
};
1674
+
1547
1675
/* SGMII PHY PMA lane configuration */
1548
1676
static const struct cdns_reg_pairs sgmii_phy_pma_ln_regs[] = {
1549
1677
{0x9010, SIERRA_PHY_PMA_XCVR_CTRL}
···
2647
2513
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2648
2514
[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2649
2515
},
2516
+
[TYPE_USB] = {
2517
+
[NO_SSC] = &pcie_phy_pcs_cmn_vals,
2518
+
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2519
+
[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2520
+
},
2650
2521
},
2651
2522
},
2652
2523
.pma_cmn_vals = {
···
2671
2532
[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
2672
2533
[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
2673
2534
},
2535
+
[TYPE_USB] = {
2536
+
[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
2537
+
[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
2538
+
[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
2539
+
},
2674
2540
},
2675
2541
[TYPE_USB] = {
2676
2542
[TYPE_NONE] = {
2677
2543
[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
2544
+
},
2545
+
[TYPE_PCIE] = {
2546
+
[EXTERNAL_SSC] = &usb_100_ext_ssc_plllc1_cmn_vals,
2547
+
[INTERNAL_SSC] = &usb_100_int_ssc_plllc1_cmn_vals,
2678
2548
},
2679
2549
},
2680
2550
[TYPE_SGMII] = {
···
2721
2573
[EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,
2722
2574
[INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals,
2723
2575
},
2576
+
[TYPE_USB] = {
2577
+
[NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,
2578
+
[EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,
2579
+
[INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals,
2580
+
},
2724
2581
},
2725
2582
[TYPE_USB] = {
2726
2583
[TYPE_NONE] = {
2727
2584
[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
2585
+
},
2586
+
[TYPE_PCIE] = {
2587
+
[EXTERNAL_SSC] = &usb_100_ml_ln_vals,
2588
+
[INTERNAL_SSC] = &usb_100_ml_ln_vals,
2728
2589
},
2729
2590
},
2730
2591
[TYPE_SGMII] = {
···
2777
2620
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2778
2621
[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2779
2622
},
2623
+
[TYPE_USB] = {
2624
+
[NO_SSC] = &pcie_phy_pcs_cmn_vals,
2625
+
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2626
+
[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
2627
+
},
2780
2628
},
2781
2629
},
2782
2630
.phy_pma_ln_vals = {
···
2817
2655
[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
2818
2656
[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
2819
2657
},
2658
+
[TYPE_USB] = {
2659
+
[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
2660
+
[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
2661
+
[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
2662
+
},
2820
2663
},
2821
2664
[TYPE_USB] = {
2822
2665
[TYPE_NONE] = {
2823
2666
[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
2667
+
},
2668
+
[TYPE_PCIE] = {
2669
+
[EXTERNAL_SSC] = &usb_100_ext_ssc_plllc1_cmn_vals,
2670
+
[INTERNAL_SSC] = &usb_100_int_ssc_plllc1_cmn_vals,
2824
2671
},
2825
2672
},
2826
2673
[TYPE_SGMII] = {
···
2864
2693
[EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals,
2865
2694
[INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals,
2866
2695
},
2696
+
[TYPE_USB] = {
2697
+
[NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals,
2698
+
[EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals,
2699
+
[INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals,
2700
+
},
2867
2701
},
2868
2702
[TYPE_USB] = {
2869
2703
[TYPE_NONE] = {
2870
2704
[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
2705
+
},
2706
+
[TYPE_PCIE] = {
2707
+
[EXTERNAL_SSC] = &usb_100_ml_ln_vals,
2708
+
[INTERNAL_SSC] = &usb_100_ml_ln_vals,
2871
2709
},
2872
2710
},
2873
2711
[TYPE_SGMII] = {
+279
-9
drivers/phy/cadence/phy-cadence-torrent.c
+279
-9
drivers/phy/cadence/phy-cadence-torrent.c
···
197
197
#define RX_SDCAL1_INIT_TMR 0x004CU
198
198
#define RX_SDCAL1_ITER_TMR 0x004DU
199
199
#define RX_CDRLF_CNFG 0x0080U
200
+
#define RX_CDRLF_CNFG2 0x0081U
200
201
#define RX_CDRLF_CNFG3 0x0082U
201
202
#define RX_SIGDET_HL_FILT_TMR 0x0090U
202
203
#define RX_REE_GCSM1_CTRL 0x0108U
···
205
204
#define RX_REE_GCSM1_EQENM_PH2 0x010AU
206
205
#define RX_REE_GCSM2_CTRL 0x0110U
207
206
#define RX_REE_PERGCSM_CTRL 0x0118U
207
+
#define RX_REE_PEAK_UTHR 0x0142U
208
+
#define RX_REE_PEAK_LTHR 0x0143U
208
209
#define RX_REE_ATTEN_THR 0x0149U
209
210
#define RX_REE_TAP1_CLIP 0x0171U
210
211
#define RX_REE_TAP2TON_CLIP 0x0172U
···
215
212
#define RX_DIAG_DFE_CTRL 0x01E0U
216
213
#define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U
217
214
#define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U
215
+
#define RX_DIAG_REE_DAC_CTRL 0x01E4U
218
216
#define RX_DIAG_NQST_CTRL 0x01E5U
219
217
#define RX_DIAG_SIGDET_TUNE 0x01E8U
220
218
#define RX_DIAG_PI_RATE 0x01F4U
···
299
295
TYPE_QSGMII,
300
296
TYPE_USB,
301
297
TYPE_USXGMII,
298
+
TYPE_PCIE_ML,
302
299
};
303
300
304
301
enum cdns_torrent_ref_clk {
···
698
693
case TYPE_DP:
699
694
return "DisplayPort";
700
695
case TYPE_PCIE:
696
+
case TYPE_PCIE_ML:
701
697
return "PCIe";
702
698
case TYPE_SGMII:
703
699
return "SGMII";
···
2484
2478
enum cdns_torrent_ssc_mode ssc;
2485
2479
struct regmap *regmap;
2486
2480
u32 num_regs, num_protocols, protocol;
2481
+
u32 num_pcie_links = 0;
2487
2482
2488
2483
num_protocols = hweight32(cdns_phy->protocol_bitmask);
2489
2484
/* Maximum 2 protocols are supported */
···
2517
2510
2518
2511
phy_t1 = fns(cdns_phy->protocol_bitmask, 0);
2519
2512
phy_t2 = fns(cdns_phy->protocol_bitmask, 1);
2513
+
2514
+
/*
2515
+
* PCIe Multilink configuration can be supported along with a
2516
+
* non-PCIe protocol. The existing limitation associated with
2517
+
* the standalone PCIe Multilink configuration still remains,
2518
+
* implying that there can be only two links (subnodes) of the
2519
+
* PHY type PCIe which constitute the PCIe Multilink.
2520
+
*
2521
+
* Such configurations are handled by introducing a new protocol
2522
+
* namely TYPE_PCIE_ML. Both of the PCIe links which have the
2523
+
* protocol as TYPE_PCIE shall be treated as though the protocol
2524
+
* corresponding to them is TYPE_PCIE_ML only for the sake of
2525
+
* configuring the SERDES.
2526
+
*
2527
+
* PCIe Multilink configuration can be identified by checking if
2528
+
* there are exactly two links with phy_type set to TYPE_PCIE.
2529
+
* phy_t1 and phy_t2 are modified in such cases to support the
2530
+
* PCIe Multilink configuration with a non-PCIe protocol.
2531
+
*/
2532
+
for (node = 0; node < cdns_phy->nsubnodes; node++) {
2533
+
if (cdns_phy->phys[node].phy_type == TYPE_PCIE)
2534
+
num_pcie_links++;
2535
+
}
2536
+
2537
+
if (num_pcie_links > 2) {
2538
+
dev_err(dev, "cannot support PCIe Multilink with %u PCIe links\n",
2539
+
num_pcie_links);
2540
+
return -EINVAL;
2541
+
} else if (num_pcie_links == 2) {
2542
+
phy_t1 = TYPE_PCIE_ML;
2543
+
for (node = 0; node < cdns_phy->nsubnodes; node++) {
2544
+
if (cdns_phy->phys[node].phy_type == TYPE_PCIE) {
2545
+
cdns_phy->phys[node].phy_type = TYPE_PCIE_ML;
2546
+
continue;
2547
+
}
2548
+
phy_t2 = cdns_phy->phys[node].phy_type;
2549
+
}
2550
+
}
2520
2551
}
2521
2552
2522
2553
/**
···
2720
2675
reset_control_deassert(cdns_phy->phys[node].lnk_rst);
2721
2676
}
2722
2677
}
2678
+
2679
+
/* Restore TYPE_PCIE_ML to TYPE_PCIE to be compatible with suspend-resume */
2680
+
for (node = 0; node < cdns_phy->nsubnodes; node++)
2681
+
if (cdns_phy->phys[node].phy_type == TYPE_PCIE_ML)
2682
+
cdns_phy->phys[node].phy_type = TYPE_PCIE;
2723
2683
2724
2684
/* Take the PHY out of reset */
2725
2685
ret = reset_control_deassert(cdns_phy->phy_rst);
···
3138
3088
}
3139
3089
3140
3090
if (cdns_phy->nsubnodes > 1)
3141
-
dev_dbg(dev, "Multi-link: %s (%d lanes) & %s (%d lanes)",
3142
-
cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
3143
-
cdns_phy->phys[0].num_lanes,
3144
-
cdns_torrent_get_phy_type(cdns_phy->phys[1].phy_type),
3145
-
cdns_phy->phys[1].num_lanes);
3091
+
dev_dbg(dev, "Multi link configuration:\n");
3146
3092
else
3147
-
dev_dbg(dev, "Single link: %s (%d lanes)",
3148
-
cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
3149
-
cdns_phy->phys[0].num_lanes);
3093
+
dev_dbg(dev, "Single link configuration:\n");
3094
+
3095
+
for (i = 0; i < cdns_phy->nsubnodes; i++)
3096
+
dev_dbg(dev, "%s (%d lanes)",
3097
+
cdns_torrent_get_phy_type(cdns_phy->phys[i].phy_type),
3098
+
cdns_phy->phys[i].num_lanes);
3150
3099
3151
3100
return 0;
3152
3101
···
3179
3130
clk_disable_unprepare(cdns_phy->clk);
3180
3131
cdns_torrent_clk_cleanup(cdns_phy);
3181
3132
}
3133
+
3134
+
/* Multilink PCIe and USB Same SSC link configuration */
3135
+
static const struct cdns_reg_pairs ml_pcie_usb_link_cmn_regs[] = {
3136
+
{0x0002, PHY_PLL_CFG},
3137
+
{0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}
3138
+
};
3139
+
3140
+
static const struct cdns_reg_pairs ml_pcie_usb_xcvr_diag_ln_regs[] = {
3141
+
{0x0100, XCVR_DIAG_HSCLK_SEL},
3142
+
{0x0013, XCVR_DIAG_HSCLK_DIV},
3143
+
{0x0812, XCVR_DIAG_PLLDRC_CTRL}
3144
+
};
3145
+
3146
+
static const struct cdns_reg_pairs usb_ml_pcie_xcvr_diag_ln_regs[] = {
3147
+
{0x0041, XCVR_DIAG_PLLDRC_CTRL},
3148
+
};
3149
+
3150
+
static const struct cdns_torrent_vals ml_pcie_usb_link_cmn_vals = {
3151
+
.reg_pairs = ml_pcie_usb_link_cmn_regs,
3152
+
.num_regs = ARRAY_SIZE(ml_pcie_usb_link_cmn_regs),
3153
+
};
3154
+
3155
+
static const struct cdns_torrent_vals ml_pcie_usb_xcvr_diag_ln_vals = {
3156
+
.reg_pairs = ml_pcie_usb_xcvr_diag_ln_regs,
3157
+
.num_regs = ARRAY_SIZE(ml_pcie_usb_xcvr_diag_ln_regs),
3158
+
};
3159
+
3160
+
static const struct cdns_torrent_vals usb_ml_pcie_xcvr_diag_ln_vals = {
3161
+
.reg_pairs = usb_ml_pcie_xcvr_diag_ln_regs,
3162
+
.num_regs = ARRAY_SIZE(usb_ml_pcie_xcvr_diag_ln_regs),
3163
+
};
3164
+
3165
+
/* Multi link PCIe configuration */
3166
+
static const struct cdns_reg_pairs ml_pcie_link_cmn_regs[] = {
3167
+
{0x0002, PHY_PLL_CFG},
3168
+
{0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
3169
+
};
3170
+
3171
+
static const struct cdns_reg_pairs ml_pcie_xcvr_diag_ln_regs[] = {
3172
+
{0x0100, XCVR_DIAG_HSCLK_SEL},
3173
+
{0x0001, XCVR_DIAG_HSCLK_DIV},
3174
+
{0x0812, XCVR_DIAG_PLLDRC_CTRL}
3175
+
};
3176
+
3177
+
static const struct cdns_torrent_vals ml_pcie_link_cmn_vals = {
3178
+
.reg_pairs = ml_pcie_link_cmn_regs,
3179
+
.num_regs = ARRAY_SIZE(ml_pcie_link_cmn_regs),
3180
+
};
3181
+
3182
+
static const struct cdns_torrent_vals ml_pcie_xcvr_diag_ln_vals = {
3183
+
.reg_pairs = ml_pcie_xcvr_diag_ln_regs,
3184
+
.num_regs = ARRAY_SIZE(ml_pcie_xcvr_diag_ln_regs),
3185
+
};
3186
+
3187
+
/* Multi link PCIe, 100 MHz Ref clk, no SSC */
3188
+
static const struct cdns_reg_pairs ml_pcie_100_no_ssc_cmn_regs[] = {
3189
+
{0x0003, CMN_PLL0_VCOCAL_TCTRL},
3190
+
{0x0003, CMN_PLL1_VCOCAL_TCTRL}
3191
+
};
3192
+
3193
+
static const struct cdns_reg_pairs ml_pcie_100_no_ssc_rx_ln_regs[] = {
3194
+
{0x0019, RX_REE_TAP1_CLIP},
3195
+
{0x0019, RX_REE_TAP2TON_CLIP},
3196
+
{0x0008, RX_REE_PEAK_UTHR},
3197
+
{0x018E, RX_CDRLF_CNFG},
3198
+
{0x2E33, RX_CDRLF_CNFG2},
3199
+
{0x0001, RX_DIAG_ACYA},
3200
+
{0x0C21, RX_DIAG_DFE_AMP_TUNE_2},
3201
+
{0x0002, RX_DIAG_DFE_AMP_TUNE_3},
3202
+
{0x0005, RX_DIAG_REE_DAC_CTRL}
3203
+
};
3204
+
3205
+
static const struct cdns_torrent_vals ml_pcie_100_no_ssc_cmn_vals = {
3206
+
.reg_pairs = ml_pcie_100_no_ssc_cmn_regs,
3207
+
.num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_cmn_regs),
3208
+
};
3209
+
3210
+
static const struct cdns_torrent_vals ml_pcie_100_no_ssc_rx_ln_vals = {
3211
+
.reg_pairs = ml_pcie_100_no_ssc_rx_ln_regs,
3212
+
.num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_rx_ln_regs),
3213
+
};
3214
+
3215
+
/* Multi link PCIe, 100 MHz Ref clk, internal SSC */
3216
+
static const struct cdns_reg_pairs ml_pcie_100_int_ssc_cmn_regs[] = {
3217
+
{0x0004, CMN_PLL0_DSM_DIAG_M0},
3218
+
{0x0004, CMN_PLL1_DSM_DIAG_M0},
3219
+
{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3220
+
{0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3221
+
{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3222
+
{0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3223
+
{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3224
+
{0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3225
+
{0x0064, CMN_PLL0_INTDIV_M0},
3226
+
{0x0050, CMN_PLL1_INTDIV_M0},
3227
+
{0x0002, CMN_PLL0_FRACDIVH_M0},
3228
+
{0x0002, CMN_PLL1_FRACDIVH_M0},
3229
+
{0x0044, CMN_PLL0_HIGH_THR_M0},
3230
+
{0x0036, CMN_PLL1_HIGH_THR_M0},
3231
+
{0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3232
+
{0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3233
+
{0x0001, CMN_PLL0_SS_CTRL1_M0},
3234
+
{0x0001, CMN_PLL1_SS_CTRL1_M0},
3235
+
{0x011B, CMN_PLL0_SS_CTRL2_M0},
3236
+
{0x011B, CMN_PLL1_SS_CTRL2_M0},
3237
+
{0x006E, CMN_PLL0_SS_CTRL3_M0},
3238
+
{0x0058, CMN_PLL1_SS_CTRL3_M0},
3239
+
{0x000E, CMN_PLL0_SS_CTRL4_M0},
3240
+
{0x0012, CMN_PLL1_SS_CTRL4_M0},
3241
+
{0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3242
+
{0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3243
+
{0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3244
+
{0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3245
+
{0x0003, CMN_PLL0_VCOCAL_TCTRL},
3246
+
{0x0003, CMN_PLL1_VCOCAL_TCTRL},
3247
+
{0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3248
+
{0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3249
+
{0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3250
+
{0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3251
+
{0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3252
+
{0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
3253
+
};
3254
+
3255
+
static const struct cdns_torrent_vals ml_pcie_100_int_ssc_cmn_vals = {
3256
+
.reg_pairs = ml_pcie_100_int_ssc_cmn_regs,
3257
+
.num_regs = ARRAY_SIZE(ml_pcie_100_int_ssc_cmn_regs),
3258
+
};
3182
3259
3183
3260
/* SGMII and QSGMII link configuration */
3184
3261
static const struct cdns_reg_pairs sgmii_qsgmii_link_cmn_regs[] = {
···
4217
4042
{0x0C02, RX_REE_ATTEN_THR},
4218
4043
{0x0330, RX_REE_SMGM_CTRL1},
4219
4044
{0x0300, RX_REE_SMGM_CTRL2},
4045
+
{0x0000, RX_REE_PEAK_UTHR},
4046
+
{0x01F5, RX_REE_PEAK_LTHR},
4220
4047
{0x0019, RX_REE_TAP1_CLIP},
4221
4048
{0x0019, RX_REE_TAP2TON_CLIP},
4222
4049
{0x1004, RX_DIAG_SIGDET_TUNE},
···
4708
4531
.num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
4709
4532
};
4710
4533
4711
-
/* Multi link PCIe, 100 MHz Ref clk, internal SSC */
4534
+
/* For PCIe (with some other protocol), 100 MHz Ref clk, internal SSC */
4712
4535
static const struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
4713
4536
{0x0004, CMN_PLL0_DSM_DIAG_M0},
4714
4537
{0x0004, CMN_PLL0_DSM_DIAG_M1},
···
4847
4670
{CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &usb_dp_link_cmn_vals},
4848
4671
4849
4672
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL},
4673
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_PCIE), &ml_pcie_link_cmn_vals},
4850
4674
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_link_cmn_vals},
4851
4675
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_link_cmn_vals},
4852
4676
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_link_cmn_vals},
4853
4677
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_link_cmn_vals},
4854
4678
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USXGMII), &pcie_usxgmii_link_cmn_vals},
4679
+
4680
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE_ML, TYPE_USB), &ml_pcie_usb_link_cmn_vals},
4855
4681
4856
4682
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_NONE), &sl_sgmii_link_cmn_vals},
4857
4683
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_PCIE), &pcie_sgmii_link_cmn_vals},
···
4870
4690
4871
4691
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &sl_usb_link_cmn_vals},
4872
4692
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &pcie_usb_link_cmn_vals},
4693
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE_ML), &ml_pcie_usb_link_cmn_vals},
4873
4694
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_sgmii_link_cmn_vals},
4874
4695
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_sgmii_link_cmn_vals},
4875
4696
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_dp_link_cmn_vals},
···
4887
4706
{CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &dp_usb_xcvr_diag_ln_vals},
4888
4707
4889
4708
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL},
4709
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_PCIE), &ml_pcie_xcvr_diag_ln_vals},
4890
4710
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_xcvr_diag_ln_vals},
4891
4711
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_xcvr_diag_ln_vals},
4892
4712
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_xcvr_diag_ln_vals},
4893
4713
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_xcvr_diag_ln_vals},
4894
4714
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USXGMII), &pcie_usxgmii_xcvr_diag_ln_vals},
4715
+
4716
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE_ML, TYPE_USB), &ml_pcie_usb_xcvr_diag_ln_vals},
4895
4717
4896
4718
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_NONE), &sl_sgmii_xcvr_diag_ln_vals},
4897
4719
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_PCIE), &sgmii_pcie_xcvr_diag_ln_vals},
···
4910
4726
4911
4727
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &sl_usb_xcvr_diag_ln_vals},
4912
4728
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &usb_pcie_xcvr_diag_ln_vals},
4729
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE_ML), &usb_ml_pcie_xcvr_diag_ln_vals},
4913
4730
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_sgmii_xcvr_diag_ln_vals},
4914
4731
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_sgmii_xcvr_diag_ln_vals},
4915
4732
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_dp_xcvr_diag_ln_vals},
···
4924
4739
static const struct cdns_torrent_vals_entry pcs_cmn_vals_entries[] = {
4925
4740
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &usb_phy_pcs_cmn_vals},
4926
4741
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &usb_phy_pcs_cmn_vals},
4742
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE_ML), &usb_phy_pcs_cmn_vals},
4927
4743
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_phy_pcs_cmn_vals},
4928
4744
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_phy_pcs_cmn_vals},
4929
4745
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_phy_pcs_cmn_vals},
···
4942
4756
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
4943
4757
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &sl_pcie_100_int_ssc_cmn_vals},
4944
4758
4759
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals},
4760
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals},
4761
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals},
4762
+
4945
4763
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},
4946
4764
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
4947
4765
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
···
4959
4769
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
4960
4770
4961
4771
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
4772
+
4773
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals},
4774
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals},
4775
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals},
4962
4776
4963
4777
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sl_sgmii_100_no_ssc_cmn_vals},
4964
4778
···
4995
4801
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_cmn_vals},
4996
4802
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_cmn_vals},
4997
4803
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_int_ssc_cmn_vals},
4804
+
4805
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_cmn_vals},
4806
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_cmn_vals},
4807
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_cmn_vals},
4998
4808
4999
4809
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},
5000
4810
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},
···
5036
4838
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
5037
4839
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
5038
4840
4841
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), NULL},
4842
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), NULL},
4843
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), NULL},
4844
+
5039
4845
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
5040
4846
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
5041
4847
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
···
5053
4851
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), NULL},
5054
4852
5055
4853
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
4854
+
4855
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), NULL},
4856
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), NULL},
4857
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), NULL},
5056
4858
5057
4859
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals},
5058
4860
···
5089
4883
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
5090
4884
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
5091
4885
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4886
+
4887
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4888
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4889
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
5092
4890
5093
4891
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
5094
4892
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
···
5130
4920
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5131
4921
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5132
4922
4923
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
4924
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
4925
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
4926
+
5133
4927
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
5134
4928
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5135
4929
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
···
5147
4933
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5148
4934
5149
4935
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4936
+
4937
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
4938
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
4939
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
5150
4940
5151
4941
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
5152
4942
···
5183
4965
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
5184
4966
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
5185
4967
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4968
+
4969
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
4970
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4971
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
5186
4972
5187
4973
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
5188
4974
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
···
5260
5038
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
5261
5039
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
5262
5040
5041
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), NULL},
5042
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), NULL},
5043
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), NULL},
5044
+
5263
5045
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
5264
5046
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
5265
5047
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
···
5277
5051
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), NULL},
5278
5052
5279
5053
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
5054
+
5055
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), NULL},
5056
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), NULL},
5057
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), NULL},
5280
5058
5281
5059
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
5282
5060
···
5313
5083
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
5314
5084
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
5315
5085
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
5086
+
5087
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
5088
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
5089
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
5316
5090
5317
5091
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
5318
5092
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
···
5388
5154
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
5389
5155
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &sl_pcie_100_int_ssc_cmn_vals},
5390
5156
5157
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals},
5158
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals},
5159
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals},
5160
+
5391
5161
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},
5392
5162
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
5393
5163
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
···
5405
5167
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
5406
5168
5407
5169
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
5170
+
5171
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals},
5172
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals},
5173
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals},
5408
5174
5409
5175
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sl_sgmii_100_no_ssc_cmn_vals},
5410
5176
···
5441
5199
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_cmn_vals},
5442
5200
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_cmn_vals},
5443
5201
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_int_ssc_cmn_vals},
5202
+
5203
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_cmn_vals},
5204
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_cmn_vals},
5205
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_cmn_vals},
5444
5206
5445
5207
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},
5446
5208
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},
···
5482
5236
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
5483
5237
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
5484
5238
5239
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), NULL},
5240
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), NULL},
5241
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), NULL},
5242
+
5485
5243
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
5486
5244
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
5487
5245
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
···
5499
5249
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), NULL},
5500
5250
5501
5251
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
5252
+
5253
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), NULL},
5254
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), NULL},
5255
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), NULL},
5502
5256
5503
5257
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
5504
5258
···
5535
5281
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
5536
5282
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
5537
5283
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
5284
+
5285
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
5286
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
5287
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
5538
5288
5539
5289
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
5540
5290
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
···
5576
5318
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5577
5319
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5578
5320
5321
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
5322
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5323
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5324
+
5579
5325
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
5580
5326
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5581
5327
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
···
5593
5331
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5594
5332
5595
5333
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
5334
+
5335
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
5336
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5337
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5596
5338
5597
5339
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
5598
5340
···
5629
5363
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
5630
5364
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
5631
5365
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
5366
+
5367
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
5368
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
5369
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
5632
5370
5633
5371
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
5634
5372
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
-1
drivers/phy/marvell/phy-pxa-usb.c
-1
drivers/phy/marvell/phy-pxa-usb.c
+37
-28
drivers/phy/mediatek/phy-mtk-tphy.c
+37
-28
drivers/phy/mediatek/phy-mtk-tphy.c
···
210
210
#define P2F_USB_FM_VALID BIT(0)
211
211
#define P2F_RG_FRCK_EN BIT(8)
212
212
213
-
#define U3P_REF_CLK 26 /* MHZ */
214
-
#define U3P_SLEW_RATE_COEF 28
215
213
#define U3P_SR_COEF_DIVISOR 1000
216
214
#define U3P_FM_DET_CYCLE_CNT 1024
217
215
···
275
277
MTK_PHY_V3,
276
278
};
277
279
280
+
/**
281
+
* mtk_phy_pdata - SoC specific platform data
282
+
* @avoid_rx_sen_degradation: Avoid TX Sensitivity level degradation (MT6795/8173 only)
283
+
* @sw_pll_48m_to_26m: Workaround for V3 IP (MT8195) - switch the 48MHz PLL from
284
+
* fractional mode to integer to output 26MHz for U2PHY
285
+
* @sw_efuse_supported: Switches off eFuse auto-load from PHY and applies values
286
+
* read from different nvmem (usually different eFuse array)
287
+
* that is pointed at in the device tree node for this PHY
288
+
* @slew_ref_clk_mhz: Default reference clock (in MHz) for slew rate calibration
289
+
* @slew_rate_coefficient: Coefficient for slew rate calibration
290
+
* @version: PHY IP Version
291
+
*/
278
292
struct mtk_phy_pdata {
279
-
/* avoid RX sensitivity level degradation only for mt8173 */
280
293
bool avoid_rx_sen_degradation;
281
-
/*
282
-
* workaround only for mt8195, HW fix it for others of V3,
283
-
* u2phy should use integer mode instead of fractional mode of
284
-
* 48M PLL, fix it by switching PLL to 26M from default 48M
285
-
*/
286
294
bool sw_pll_48m_to_26m;
287
-
/*
288
-
* Some SoCs (e.g. mt8195) drop a bit when use auto load efuse,
289
-
* support sw way, also support it for v2/v3 optionally.
290
-
*/
291
295
bool sw_efuse_supported;
296
+
u8 slew_ref_clock_mhz;
297
+
u8 slew_rate_coefficient;
292
298
enum mtk_phy_version version;
293
299
};
294
300
···
688
686
int fm_out;
689
687
u32 tmp;
690
688
691
-
/* HW V3 doesn't support slew rate cal anymore */
692
-
if (tphy->pdata->version == MTK_PHY_V3)
693
-
return;
694
-
695
-
/* use force value */
696
-
if (instance->eye_src)
689
+
/*
690
+
* If a fixed HS slew rate (EYE) value was supplied, don't run the
691
+
* calibration sequence and prefer using that value instead; also,
692
+
* if there is no reference clock for slew calibration or there is
693
+
* no slew coefficient, this means that the slew rate calibration
694
+
* sequence is not supported.
695
+
*/
696
+
if (instance->eye_src || !tphy->src_ref_clk || !tphy->src_coef)
697
697
return;
698
698
699
699
/* enable USB ring oscillator */
···
1520
1516
1521
1517
static const struct mtk_phy_pdata tphy_v1_pdata = {
1522
1518
.avoid_rx_sen_degradation = false,
1519
+
.slew_ref_clock_mhz = 26,
1520
+
.slew_rate_coefficient = 28,
1523
1521
.version = MTK_PHY_V1,
1524
1522
};
1525
1523
1526
1524
static const struct mtk_phy_pdata tphy_v2_pdata = {
1527
1525
.avoid_rx_sen_degradation = false,
1528
1526
.sw_efuse_supported = true,
1527
+
.slew_ref_clock_mhz = 26,
1528
+
.slew_rate_coefficient = 28,
1529
1529
.version = MTK_PHY_V2,
1530
1530
};
1531
1531
···
1540
1532
1541
1533
static const struct mtk_phy_pdata mt8173_pdata = {
1542
1534
.avoid_rx_sen_degradation = true,
1535
+
.slew_ref_clock_mhz = 26,
1536
+
.slew_rate_coefficient = 28,
1543
1537
.version = MTK_PHY_V1,
1544
1538
};
1545
1539
···
1571
1561
struct resource *sif_res;
1572
1562
struct mtk_tphy *tphy;
1573
1563
struct resource res;
1574
-
int port;
1564
+
int port, ret;
1575
1565
1576
1566
tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL);
1577
1567
if (!tphy)
···
1601
1591
}
1602
1592
}
1603
1593
1604
-
if (tphy->pdata->version < MTK_PHY_V3) {
1605
-
tphy->src_ref_clk = U3P_REF_CLK;
1606
-
tphy->src_coef = U3P_SLEW_RATE_COEF;
1607
-
/* update parameters of slew rate calibrate if exist */
1608
-
device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
1609
-
&tphy->src_ref_clk);
1610
-
device_property_read_u32(dev, "mediatek,src-coef",
1611
-
&tphy->src_coef);
1612
-
}
1594
+
/* Optional properties for slew calibration variation */
1595
+
ret = device_property_read_u32(dev, "mediatek,src-ref-clk-mhz", &tphy->src_ref_clk);
1596
+
if (ret)
1597
+
tphy->src_ref_clk = tphy->pdata->slew_ref_clock_mhz;
1598
+
1599
+
ret = device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);
1600
+
if (ret)
1601
+
tphy->src_coef = tphy->pdata->slew_rate_coefficient;
1613
1602
1614
1603
port = 0;
1615
1604
for_each_child_of_node_scoped(np, child_np) {
+25
-21
drivers/phy/phy-snps-eusb2.c
+25
-21
drivers/phy/phy-snps-eusb2.c
···
256
256
}
257
257
258
258
if (!config) {
259
-
dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", ref_clk_freq);
259
+
dev_err(&phy->phy->dev, "unsupported ref_clk_freq: %lu\n", ref_clk_freq);
260
260
return -EINVAL;
261
261
}
262
262
···
293
293
}
294
294
295
295
if (!config) {
296
-
dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", ref_clk_freq);
296
+
dev_err(&phy->phy->dev, "unsupported ref_clk_freq: %lu\n", ref_clk_freq);
297
297
return -EINVAL;
298
298
}
299
299
···
392
392
393
393
snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_1,
394
394
PHY_CFG_PLL_CPBIAS_CNTRL_MASK,
395
-
FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 0x1));
395
+
FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 0x0));
396
396
397
397
snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_4,
398
398
PHY_CFG_PLL_INT_CNTRL_MASK,
···
437
437
snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_HS_PHY_CTRL2,
438
438
USB2_SUSPEND_N_SEL, 0);
439
439
440
+
snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG0,
441
+
CMN_CTRL_OVERRIDE_EN, 0);
442
+
440
443
return 0;
441
444
}
442
445
···
464
461
465
462
ret = phy_init(phy->repeater);
466
463
if (ret) {
467
-
dev_err(&p->dev, "repeater init failed. %d\n", ret);
464
+
dev_err(&p->dev, "repeater init failed: %d\n", ret);
468
465
goto disable_vreg;
469
466
}
470
467
471
468
ret = clk_bulk_prepare_enable(phy->data->num_clks, phy->clks);
472
469
if (ret) {
473
-
dev_err(&p->dev, "failed to enable ref clock, %d\n", ret);
474
-
goto disable_vreg;
470
+
dev_err(&p->dev, "failed to enable ref clock: %d\n", ret);
471
+
goto exit_repeater;
475
472
}
476
473
477
474
ret = reset_control_assert(phy->phy_reset);
478
475
if (ret) {
479
-
dev_err(&p->dev, "failed to assert phy_reset, %d\n", ret);
480
-
goto disable_ref_clk;
476
+
dev_err(&p->dev, "failed to assert phy_reset: %d\n", ret);
477
+
goto disable_clks;
481
478
}
482
479
483
480
usleep_range(100, 150);
484
481
485
482
ret = reset_control_deassert(phy->phy_reset);
486
483
if (ret) {
487
-
dev_err(&p->dev, "failed to de-assert phy_reset, %d\n", ret);
488
-
goto disable_ref_clk;
484
+
dev_err(&p->dev, "failed to de-assert phy_reset: %d\n", ret);
485
+
goto disable_clks;
489
486
}
490
487
491
488
ret = phy->data->phy_init(p);
492
489
if (ret)
493
-
goto disable_ref_clk;
490
+
goto disable_clks;
494
491
495
492
return 0;
496
493
497
-
disable_ref_clk:
494
+
disable_clks:
498
495
clk_bulk_disable_unprepare(phy->data->num_clks, phy->clks);
499
-
496
+
exit_repeater:
497
+
phy_exit(phy->repeater);
500
498
disable_vreg:
501
499
regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs);
502
500
···
508
504
{
509
505
struct snps_eusb2_hsphy *phy = phy_get_drvdata(p);
510
506
511
-
clk_disable_unprepare(phy->ref_clk);
507
+
clk_bulk_disable_unprepare(phy->data->num_clks, phy->clks);
512
508
513
509
regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs);
514
510
···
555
551
if (!phy->clks)
556
552
return -ENOMEM;
557
553
558
-
for (int i = 0; i < phy->data->num_clks; ++i)
554
+
for (i = 0; i < phy->data->num_clks; ++i)
559
555
phy->clks[i].id = phy->data->clk_names[i];
560
556
561
557
ret = devm_clk_bulk_get(dev, phy->data->num_clks, phy->clks);
···
564
560
"failed to get phy clock(s)\n");
565
561
566
562
phy->ref_clk = NULL;
567
-
for (int i = 0; i < phy->data->num_clks; ++i) {
563
+
for (i = 0; i < phy->data->num_clks; ++i) {
568
564
if (!strcmp(phy->clks[i].id, "ref")) {
569
565
phy->ref_clk = phy->clks[i].clk;
570
566
break;
···
586
582
return dev_err_probe(dev, ret,
587
583
"failed to get regulator supplies\n");
588
584
589
-
phy->repeater = devm_of_phy_optional_get(dev, np, 0);
585
+
phy->repeater = devm_of_phy_optional_get(dev, np, NULL);
590
586
if (IS_ERR(phy->repeater))
591
587
return dev_err_probe(dev, PTR_ERR(phy->repeater),
592
588
"failed to get repeater\n");
593
589
594
590
generic_phy = devm_phy_create(dev, NULL, &snps_eusb2_hsphy_ops);
595
591
if (IS_ERR(generic_phy)) {
596
-
dev_err(dev, "failed to create phy %d\n", ret);
592
+
dev_err(dev, "failed to create phy: %d\n", ret);
597
593
return PTR_ERR(generic_phy);
598
594
}
599
595
···
603
599
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
604
600
if (IS_ERR(phy_provider))
605
601
return PTR_ERR(phy_provider);
606
-
607
-
dev_info(dev, "Registered Snps-eUSB2 phy\n");
608
602
609
603
return 0;
610
604
}
···
614
612
}, {
615
613
.compatible = "samsung,exynos2200-eusb2-phy",
616
614
.data = &exynos2200_snps_eusb2_phy,
617
-
}, { },
615
+
}, {
616
+
/* sentinel */
617
+
}
618
618
};
619
619
MODULE_DEVICE_TABLE(of, snps_eusb2_hsphy_of_match_table);
620
620
+13
-3
drivers/phy/qualcomm/Kconfig
+13
-3
drivers/phy/qualcomm/Kconfig
···
126
126
USB IPs on MSM SOCs.
127
127
128
128
config PHY_QCOM_EUSB2_REPEATER
129
-
tristate "Qualcomm SNPS eUSB2 Repeater Driver"
129
+
tristate "Qualcomm PMIC eUSB2 Repeater Driver"
130
130
depends on OF && (ARCH_QCOM || COMPILE_TEST)
131
131
select GENERIC_PHY
132
132
help
133
-
Enable support for the USB high-speed SNPS eUSB2 repeater on Qualcomm
134
-
PMICs. The repeater is paired with a Synopsys eUSB2 Phy
133
+
Enable support for the USB high-speed eUSB2 repeater on Qualcomm
134
+
PMICs. The repeater is paired with a Synopsys or M31 eUSB2 Phy
135
135
on Qualcomm SOCs.
136
136
137
137
config PHY_QCOM_M31_USB
···
157
157
is used with PCIe controllers on Qualcomm IPQ5332 chips. It
158
158
handles PHY initialization, clock management required after
159
159
resetting the hardware and power management.
160
+
161
+
config PHY_QCOM_M31_EUSB
162
+
tristate "Qualcomm M31 eUSB2 PHY driver support"
163
+
depends on USB && (ARCH_QCOM || COMPILE_TEST)
164
+
select GENERIC_PHY
165
+
help
166
+
Enable this to support M31 EUSB2 PHY transceivers on Qualcomm
167
+
chips with DWC3 USB core. It supports initializing and cleaning
168
+
up of the associated USB repeater that is paired with the eUSB2
169
+
PHY.
160
170
161
171
config PHY_QCOM_USB_HS
162
172
tristate "Qualcomm USB HS PHY module"
+1
drivers/phy/qualcomm/Makefile
+1
drivers/phy/qualcomm/Makefile
···
5
5
obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
6
6
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
7
7
obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o
8
+
obj-$(CONFIG_PHY_QCOM_M31_EUSB) += phy-qcom-m31-eusb2.o
8
9
obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
9
10
10
11
obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o phy-qcom-qmp-usbc.o
+30
-55
drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
+30
-55
drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
···
37
37
#define EUSB2_TUNE_EUSB_EQU 0x5A
38
38
#define EUSB2_TUNE_EUSB_HS_COMP_CUR 0x5B
39
39
40
-
enum eusb2_reg_layout {
41
-
TUNE_EUSB_HS_COMP_CUR,
42
-
TUNE_EUSB_EQU,
43
-
TUNE_EUSB_SLEW,
44
-
TUNE_USB2_HS_COMP_CUR,
45
-
TUNE_USB2_PREEM,
46
-
TUNE_USB2_EQU,
47
-
TUNE_USB2_SLEW,
48
-
TUNE_SQUELCH_U,
49
-
TUNE_HSDISC,
50
-
TUNE_RES_FSDIF,
51
-
TUNE_IUSB2,
52
-
TUNE_USB2_CROSSOVER,
53
-
NUM_TUNE_FIELDS,
54
-
55
-
FORCE_VAL_5 = NUM_TUNE_FIELDS,
56
-
FORCE_EN_5,
57
-
58
-
EN_CTL1,
59
-
60
-
RPTR_STATUS,
61
-
LAYOUT_SIZE,
40
+
struct eusb2_repeater_init_tbl_reg {
41
+
unsigned int reg;
42
+
unsigned int value;
62
43
};
63
44
64
45
struct eusb2_repeater_cfg {
65
-
const u32 *init_tbl;
46
+
const struct eusb2_repeater_init_tbl_reg *init_tbl;
66
47
int init_tbl_num;
67
48
const char * const *vreg_list;
68
49
int num_vregs;
···
63
82
"vdd18", "vdd3",
64
83
};
65
84
66
-
static const u32 pm8550b_init_tbl[NUM_TUNE_FIELDS] = {
67
-
[TUNE_IUSB2] = 0x8,
68
-
[TUNE_SQUELCH_U] = 0x3,
69
-
[TUNE_USB2_PREEM] = 0x5,
85
+
static const struct eusb2_repeater_init_tbl_reg pm8550b_init_tbl[] = {
86
+
{ EUSB2_TUNE_IUSB2, 0x8 },
87
+
{ EUSB2_TUNE_SQUELCH_U, 0x3 },
88
+
{ EUSB2_TUNE_USB2_PREEM, 0x5 },
70
89
};
71
90
72
-
static const u32 smb2360_init_tbl[NUM_TUNE_FIELDS] = {
73
-
[TUNE_IUSB2] = 0x5,
74
-
[TUNE_SQUELCH_U] = 0x3,
75
-
[TUNE_USB2_PREEM] = 0x2,
91
+
static const struct eusb2_repeater_init_tbl_reg smb2360_init_tbl[] = {
92
+
{ EUSB2_TUNE_IUSB2, 0x5 },
93
+
{ EUSB2_TUNE_SQUELCH_U, 0x3 },
94
+
{ EUSB2_TUNE_USB2_PREEM, 0x2 },
76
95
};
77
96
78
97
static const struct eusb2_repeater_cfg pm8550b_eusb2_cfg = {
···
110
129
struct eusb2_repeater *rptr = phy_get_drvdata(phy);
111
130
struct device_node *np = rptr->dev->of_node;
112
131
struct regmap *regmap = rptr->regmap;
113
-
const u32 *init_tbl = rptr->cfg->init_tbl;
114
-
u8 tune_usb2_preem = init_tbl[TUNE_USB2_PREEM];
115
-
u8 tune_hsdisc = init_tbl[TUNE_HSDISC];
116
-
u8 tune_iusb2 = init_tbl[TUNE_IUSB2];
117
132
u32 base = rptr->base;
118
-
u32 val;
133
+
u32 poll_val;
119
134
int ret;
120
-
121
-
of_property_read_u8(np, "qcom,tune-usb2-amplitude", &tune_iusb2);
122
-
of_property_read_u8(np, "qcom,tune-usb2-disc-thres", &tune_hsdisc);
123
-
of_property_read_u8(np, "qcom,tune-usb2-preem", &tune_usb2_preem);
135
+
u8 val;
124
136
125
137
ret = regulator_bulk_enable(rptr->cfg->num_vregs, rptr->vregs);
126
138
if (ret)
···
121
147
122
148
regmap_write(regmap, base + EUSB2_EN_CTL1, EUSB2_RPTR_EN);
123
149
124
-
regmap_write(regmap, base + EUSB2_TUNE_EUSB_HS_COMP_CUR, init_tbl[TUNE_EUSB_HS_COMP_CUR]);
125
-
regmap_write(regmap, base + EUSB2_TUNE_EUSB_EQU, init_tbl[TUNE_EUSB_EQU]);
126
-
regmap_write(regmap, base + EUSB2_TUNE_EUSB_SLEW, init_tbl[TUNE_EUSB_SLEW]);
127
-
regmap_write(regmap, base + EUSB2_TUNE_USB2_HS_COMP_CUR, init_tbl[TUNE_USB2_HS_COMP_CUR]);
128
-
regmap_write(regmap, base + EUSB2_TUNE_USB2_EQU, init_tbl[TUNE_USB2_EQU]);
129
-
regmap_write(regmap, base + EUSB2_TUNE_USB2_SLEW, init_tbl[TUNE_USB2_SLEW]);
130
-
regmap_write(regmap, base + EUSB2_TUNE_SQUELCH_U, init_tbl[TUNE_SQUELCH_U]);
131
-
regmap_write(regmap, base + EUSB2_TUNE_RES_FSDIF, init_tbl[TUNE_RES_FSDIF]);
132
-
regmap_write(regmap, base + EUSB2_TUNE_USB2_CROSSOVER, init_tbl[TUNE_USB2_CROSSOVER]);
150
+
/* Write registers from init table */
151
+
for (int i = 0; i < rptr->cfg->init_tbl_num; i++)
152
+
regmap_write(regmap, base + rptr->cfg->init_tbl[i].reg,
153
+
rptr->cfg->init_tbl[i].value);
133
154
134
-
regmap_write(regmap, base + EUSB2_TUNE_USB2_PREEM, tune_usb2_preem);
135
-
regmap_write(regmap, base + EUSB2_TUNE_HSDISC, tune_hsdisc);
136
-
regmap_write(regmap, base + EUSB2_TUNE_IUSB2, tune_iusb2);
155
+
/* Override registers from devicetree values */
156
+
if (!of_property_read_u8(np, "qcom,tune-usb2-amplitude", &val))
157
+
regmap_write(regmap, base + EUSB2_TUNE_USB2_PREEM, val);
137
158
138
-
ret = regmap_read_poll_timeout(regmap, base + EUSB2_RPTR_STATUS, val, val & RPTR_OK, 10, 5);
159
+
if (!of_property_read_u8(np, "qcom,tune-usb2-disc-thres", &val))
160
+
regmap_write(regmap, base + EUSB2_TUNE_HSDISC, val);
161
+
162
+
if (!of_property_read_u8(np, "qcom,tune-usb2-preem", &val))
163
+
regmap_write(regmap, base + EUSB2_TUNE_IUSB2, val);
164
+
165
+
/* Wait for status OK */
166
+
ret = regmap_read_poll_timeout(regmap, base + EUSB2_RPTR_STATUS, poll_val,
167
+
poll_val & RPTR_OK, 10, 5);
139
168
if (ret)
140
169
dev_err(rptr->dev, "initialization timed-out\n");
141
170
···
240
263
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
241
264
if (IS_ERR(phy_provider))
242
265
return PTR_ERR(phy_provider);
243
-
244
-
dev_info(dev, "Registered Qcom-eUSB2 repeater\n");
245
266
246
267
return 0;
247
268
}
+324
drivers/phy/qualcomm/phy-qcom-m31-eusb2.c
+324
drivers/phy/qualcomm/phy-qcom-m31-eusb2.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/bitfield.h>
7
+
#include <linux/clk.h>
8
+
#include <linux/delay.h>
9
+
#include <linux/err.h>
10
+
#include <linux/io.h>
11
+
#include <linux/kernel.h>
12
+
#include <linux/module.h>
13
+
#include <linux/of.h>
14
+
#include <linux/phy/phy.h>
15
+
#include <linux/platform_device.h>
16
+
#include <linux/reset.h>
17
+
#include <linux/slab.h>
18
+
19
+
#include <linux/regulator/consumer.h>
20
+
21
+
#define USB_PHY_UTMI_CTRL0 (0x3c)
22
+
#define SLEEPM BIT(0)
23
+
24
+
#define USB_PHY_UTMI_CTRL5 (0x50)
25
+
#define POR BIT(1)
26
+
27
+
#define USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
28
+
#define SIDDQ_SEL BIT(1)
29
+
#define SIDDQ BIT(2)
30
+
#define FSEL GENMASK(6, 4)
31
+
#define FSEL_38_4_MHZ_VAL (0x6)
32
+
33
+
#define USB_PHY_HS_PHY_CTRL2 (0x64)
34
+
#define USB2_SUSPEND_N BIT(2)
35
+
#define USB2_SUSPEND_N_SEL BIT(3)
36
+
37
+
#define USB_PHY_CFG0 (0x94)
38
+
#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1)
39
+
40
+
#define USB_PHY_CFG1 (0x154)
41
+
#define PLL_EN BIT(0)
42
+
43
+
#define USB_PHY_FSEL_SEL (0xb8)
44
+
#define FSEL_SEL BIT(0)
45
+
46
+
#define USB_PHY_XCFGI_39_32 (0x16c)
47
+
#define HSTX_PE GENMASK(3, 2)
48
+
49
+
#define USB_PHY_XCFGI_71_64 (0x17c)
50
+
#define HSTX_SWING GENMASK(3, 0)
51
+
52
+
#define USB_PHY_XCFGI_31_24 (0x168)
53
+
#define HSTX_SLEW GENMASK(2, 0)
54
+
55
+
#define USB_PHY_XCFGI_7_0 (0x15c)
56
+
#define PLL_LOCK_TIME GENMASK(1, 0)
57
+
58
+
#define M31_EUSB_PHY_INIT_CFG(o, b, v) \
59
+
{ \
60
+
.off = o, \
61
+
.mask = b, \
62
+
.val = v, \
63
+
}
64
+
65
+
struct m31_phy_tbl_entry {
66
+
u32 off;
67
+
u32 mask;
68
+
u32 val;
69
+
};
70
+
71
+
struct m31_eusb2_priv_data {
72
+
const struct m31_phy_tbl_entry *setup_seq;
73
+
unsigned int setup_seq_nregs;
74
+
const struct m31_phy_tbl_entry *override_seq;
75
+
unsigned int override_seq_nregs;
76
+
const struct m31_phy_tbl_entry *reset_seq;
77
+
unsigned int reset_seq_nregs;
78
+
unsigned int fsel;
79
+
};
80
+
81
+
static const struct m31_phy_tbl_entry m31_eusb2_setup_tbl[] = {
82
+
M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 1),
83
+
M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, POR, 1),
84
+
M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG1, PLL_EN, 1),
85
+
M31_EUSB_PHY_INIT_CFG(USB_PHY_FSEL_SEL, FSEL_SEL, 1),
86
+
};
87
+
88
+
static const struct m31_phy_tbl_entry m31_eusb_phy_override_tbl[] = {
89
+
M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_39_32, HSTX_PE, 0),
90
+
M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_71_64, HSTX_SWING, 7),
91
+
M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_31_24, HSTX_SLEW, 0),
92
+
M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_7_0, PLL_LOCK_TIME, 0),
93
+
};
94
+
95
+
static const struct m31_phy_tbl_entry m31_eusb_phy_reset_tbl[] = {
96
+
M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 1),
97
+
M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N, 1),
98
+
M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL0, SLEEPM, 1),
99
+
M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ_SEL, 1),
100
+
M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ, 0),
101
+
M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, POR, 0),
102
+
M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 0),
103
+
M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0),
104
+
};
105
+
106
+
static const struct regulator_bulk_data m31_eusb_phy_vregs[] = {
107
+
{ .supply = "vdd" },
108
+
{ .supply = "vdda12" },
109
+
};
110
+
111
+
#define M31_EUSB_NUM_VREGS ARRAY_SIZE(m31_eusb_phy_vregs)
112
+
113
+
struct m31eusb2_phy {
114
+
struct phy *phy;
115
+
void __iomem *base;
116
+
const struct m31_eusb2_priv_data *data;
117
+
enum phy_mode mode;
118
+
119
+
struct regulator_bulk_data *vregs;
120
+
struct clk *clk;
121
+
struct reset_control *reset;
122
+
123
+
struct phy *repeater;
124
+
};
125
+
126
+
static int m31eusb2_phy_write_readback(void __iomem *base, u32 offset,
127
+
const u32 mask, u32 val)
128
+
{
129
+
u32 write_val;
130
+
u32 tmp;
131
+
132
+
tmp = readl(base + offset);
133
+
tmp &= ~mask;
134
+
write_val = tmp | val;
135
+
136
+
writel(write_val, base + offset);
137
+
138
+
tmp = readl(base + offset);
139
+
tmp &= mask;
140
+
141
+
if (tmp != val) {
142
+
pr_err("write: %x to offset: %x FAILED\n", val, offset);
143
+
return -EINVAL;
144
+
}
145
+
146
+
return 0;
147
+
}
148
+
149
+
static int m31eusb2_phy_write_sequence(struct m31eusb2_phy *phy,
150
+
const struct m31_phy_tbl_entry *tbl,
151
+
int num)
152
+
{
153
+
int i;
154
+
int ret;
155
+
156
+
for (i = 0 ; i < num; i++, tbl++) {
157
+
dev_dbg(&phy->phy->dev, "Offset:%x BitMask:%x Value:%x",
158
+
tbl->off, tbl->mask, tbl->val);
159
+
160
+
ret = m31eusb2_phy_write_readback(phy->base,
161
+
tbl->off, tbl->mask,
162
+
tbl->val << __ffs(tbl->mask));
163
+
if (ret < 0)
164
+
return ret;
165
+
}
166
+
167
+
return 0;
168
+
}
169
+
170
+
static int m31eusb2_phy_set_mode(struct phy *uphy, enum phy_mode mode, int submode)
171
+
{
172
+
struct m31eusb2_phy *phy = phy_get_drvdata(uphy);
173
+
174
+
phy->mode = mode;
175
+
176
+
return phy_set_mode_ext(phy->repeater, mode, submode);
177
+
}
178
+
179
+
static int m31eusb2_phy_init(struct phy *uphy)
180
+
{
181
+
struct m31eusb2_phy *phy = phy_get_drvdata(uphy);
182
+
const struct m31_eusb2_priv_data *data = phy->data;
183
+
int ret;
184
+
185
+
ret = regulator_bulk_enable(M31_EUSB_NUM_VREGS, phy->vregs);
186
+
if (ret) {
187
+
dev_err(&uphy->dev, "failed to enable regulator, %d\n", ret);
188
+
return ret;
189
+
}
190
+
191
+
ret = phy_init(phy->repeater);
192
+
if (ret) {
193
+
dev_err(&uphy->dev, "repeater init failed. %d\n", ret);
194
+
goto disable_vreg;
195
+
}
196
+
197
+
ret = clk_prepare_enable(phy->clk);
198
+
if (ret) {
199
+
dev_err(&uphy->dev, "failed to enable cfg ahb clock, %d\n", ret);
200
+
goto disable_repeater;
201
+
}
202
+
203
+
/* Perform phy reset */
204
+
reset_control_assert(phy->reset);
205
+
udelay(5);
206
+
reset_control_deassert(phy->reset);
207
+
208
+
m31eusb2_phy_write_sequence(phy, data->setup_seq, data->setup_seq_nregs);
209
+
m31eusb2_phy_write_readback(phy->base,
210
+
USB_PHY_HS_PHY_CTRL_COMMON0, FSEL,
211
+
FIELD_PREP(FSEL, data->fsel));
212
+
m31eusb2_phy_write_sequence(phy, data->override_seq, data->override_seq_nregs);
213
+
m31eusb2_phy_write_sequence(phy, data->reset_seq, data->reset_seq_nregs);
214
+
215
+
return 0;
216
+
217
+
disable_repeater:
218
+
phy_exit(phy->repeater);
219
+
disable_vreg:
220
+
regulator_bulk_disable(M31_EUSB_NUM_VREGS, phy->vregs);
221
+
222
+
return 0;
223
+
}
224
+
225
+
static int m31eusb2_phy_exit(struct phy *uphy)
226
+
{
227
+
struct m31eusb2_phy *phy = phy_get_drvdata(uphy);
228
+
229
+
clk_disable_unprepare(phy->clk);
230
+
regulator_bulk_disable(M31_EUSB_NUM_VREGS, phy->vregs);
231
+
phy_exit(phy->repeater);
232
+
233
+
return 0;
234
+
}
235
+
236
+
static const struct phy_ops m31eusb2_phy_gen_ops = {
237
+
.init = m31eusb2_phy_init,
238
+
.exit = m31eusb2_phy_exit,
239
+
.set_mode = m31eusb2_phy_set_mode,
240
+
.owner = THIS_MODULE,
241
+
};
242
+
243
+
static int m31eusb2_phy_probe(struct platform_device *pdev)
244
+
{
245
+
struct phy_provider *phy_provider;
246
+
const struct m31_eusb2_priv_data *data;
247
+
struct device *dev = &pdev->dev;
248
+
struct m31eusb2_phy *phy;
249
+
int ret;
250
+
251
+
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
252
+
if (!phy)
253
+
return -ENOMEM;
254
+
255
+
data = device_get_match_data(dev);
256
+
if (!data)
257
+
return -EINVAL;
258
+
phy->data = data;
259
+
260
+
phy->base = devm_platform_ioremap_resource(pdev, 0);
261
+
if (IS_ERR(phy->base))
262
+
return PTR_ERR(phy->base);
263
+
264
+
phy->reset = devm_reset_control_get_exclusive(dev, NULL);
265
+
if (IS_ERR(phy->reset))
266
+
return PTR_ERR(phy->reset);
267
+
268
+
phy->clk = devm_clk_get(dev, NULL);
269
+
if (IS_ERR(phy->clk))
270
+
return dev_err_probe(dev, PTR_ERR(phy->clk),
271
+
"failed to get clk\n");
272
+
273
+
phy->phy = devm_phy_create(dev, NULL, &m31eusb2_phy_gen_ops);
274
+
if (IS_ERR(phy->phy))
275
+
return dev_err_probe(dev, PTR_ERR(phy->phy),
276
+
"failed to create phy\n");
277
+
278
+
ret = devm_regulator_bulk_get_const(dev, M31_EUSB_NUM_VREGS,
279
+
m31_eusb_phy_vregs, &phy->vregs);
280
+
if (ret)
281
+
return dev_err_probe(dev, ret,
282
+
"failed to get regulator supplies\n");
283
+
284
+
phy_set_drvdata(phy->phy, phy);
285
+
286
+
phy->repeater = devm_of_phy_get_by_index(dev, dev->of_node, 0);
287
+
if (IS_ERR(phy->repeater))
288
+
return dev_err_probe(dev, PTR_ERR(phy->repeater),
289
+
"failed to get repeater\n");
290
+
291
+
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
292
+
293
+
return PTR_ERR_OR_ZERO(phy_provider);
294
+
}
295
+
296
+
static const struct m31_eusb2_priv_data m31_eusb_v1_data = {
297
+
.setup_seq = m31_eusb2_setup_tbl,
298
+
.setup_seq_nregs = ARRAY_SIZE(m31_eusb2_setup_tbl),
299
+
.override_seq = m31_eusb_phy_override_tbl,
300
+
.override_seq_nregs = ARRAY_SIZE(m31_eusb_phy_override_tbl),
301
+
.reset_seq = m31_eusb_phy_reset_tbl,
302
+
.reset_seq_nregs = ARRAY_SIZE(m31_eusb_phy_reset_tbl),
303
+
.fsel = FSEL_38_4_MHZ_VAL,
304
+
};
305
+
306
+
static const struct of_device_id m31eusb2_phy_id_table[] = {
307
+
{ .compatible = "qcom,sm8750-m31-eusb2-phy", .data = &m31_eusb_v1_data },
308
+
{ },
309
+
};
310
+
MODULE_DEVICE_TABLE(of, m31eusb2_phy_id_table);
311
+
312
+
static struct platform_driver m31eusb2_phy_driver = {
313
+
.probe = m31eusb2_phy_probe,
314
+
.driver = {
315
+
.name = "qcom-m31eusb2-phy",
316
+
.of_match_table = m31eusb2_phy_id_table,
317
+
},
318
+
};
319
+
320
+
module_platform_driver(m31eusb2_phy_driver);
321
+
322
+
MODULE_AUTHOR("Wesley Cheng <quic_wcheng@quicinc.com>");
323
+
MODULE_DESCRIPTION("eUSB2 Qualcomm M31 HSPHY driver");
324
+
MODULE_LICENSE("GPL");
+10
-6
drivers/phy/qualcomm/phy-qcom-m31.c
+10
-6
drivers/phy/qualcomm/phy-qcom-m31.c
···
58
58
#define USB2_0_TX_ENABLE BIT(2)
59
59
60
60
#define USB2PHY_USB_PHY_M31_XCFGI_4 0xc8
61
-
#define HSTX_SLEW_RATE_565PS GENMASK(1, 0)
61
+
#define HSTX_SLEW_RATE_400PS GENMASK(2, 0)
62
62
#define PLL_CHARGING_PUMP_CURRENT_35UA GENMASK(4, 3)
63
63
#define ODT_VALUE_38_02_OHM GENMASK(7, 6)
64
64
65
65
#define USB2PHY_USB_PHY_M31_XCFGI_5 0xcc
66
-
#define ODT_VALUE_45_02_OHM BIT(2)
67
66
#define HSTX_PRE_EMPHASIS_LEVEL_0_55MA BIT(0)
67
+
68
+
#define USB2PHY_USB_PHY_M31_XCFGI_9 0xdc
69
+
#define HSTX_CURRENT_17_1MA_385MV BIT(1)
68
70
69
71
#define USB2PHY_USB_PHY_M31_XCFGI_11 0xe4
70
72
#define XCFG_COARSE_TUNE_NUM BIT(1)
···
166
164
},
167
165
{
168
166
USB2PHY_USB_PHY_M31_XCFGI_4,
169
-
HSTX_SLEW_RATE_565PS | PLL_CHARGING_PUMP_CURRENT_35UA | ODT_VALUE_38_02_OHM,
167
+
HSTX_SLEW_RATE_400PS | PLL_CHARGING_PUMP_CURRENT_35UA | ODT_VALUE_38_02_OHM,
170
168
0
171
169
},
172
170
{
···
176
174
},
177
175
{
178
176
USB2PHY_USB_PHY_M31_XCFGI_5,
179
-
ODT_VALUE_45_02_OHM | HSTX_PRE_EMPHASIS_LEVEL_0_55MA,
177
+
HSTX_PRE_EMPHASIS_LEVEL_0_55MA,
180
178
4
179
+
},
180
+
{
181
+
USB2PHY_USB_PHY_M31_XCFGI_9,
182
+
HSTX_CURRENT_17_1MA_385MV,
181
183
},
182
184
{
183
185
USB_PHY_UTMI_CTRL5,
···
311
305
phy_set_drvdata(qphy->phy, qphy);
312
306
313
307
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
314
-
if (!IS_ERR(phy_provider))
315
-
dev_info(dev, "Registered M31 USB phy\n");
316
308
317
309
return PTR_ERR_OR_ZERO(phy_provider);
318
310
}
+224
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+224
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
···
32
32
#include "phy-qcom-qmp-pcs-usb-v4.h"
33
33
#include "phy-qcom-qmp-pcs-usb-v5.h"
34
34
#include "phy-qcom-qmp-pcs-usb-v6.h"
35
+
#include "phy-qcom-qmp-pcs-usb-v8.h"
35
36
36
37
#include "phy-qcom-qmp-dp-com-v3.h"
37
38
···
211
210
[QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_N4_TX_TX_EMP_POST1_LVL,
212
211
[QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_N4_TX_HIGHZ_DRVR_EN,
213
212
[QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN,
213
+
};
214
+
215
+
static const unsigned int qmp_v8_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
216
+
[QPHY_SW_RESET] = QPHY_V8_PCS_SW_RESET,
217
+
[QPHY_START_CTRL] = QPHY_V8_PCS_START_CONTROL,
218
+
[QPHY_PCS_STATUS] = QPHY_V8_PCS_PCS_STATUS1,
219
+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V8_PCS_POWER_DOWN_CONTROL,
220
+
221
+
/* In PCS_USB */
222
+
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL,
223
+
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR,
224
+
225
+
[QPHY_COM_RESETSM_CNTRL] = QSERDES_V8_COM_RESETSM_CNTRL,
226
+
[QPHY_COM_C_READY_STATUS] = QSERDES_V8_COM_C_READY_STATUS,
227
+
[QPHY_COM_CMN_STATUS] = QSERDES_V8_COM_CMN_STATUS,
228
+
[QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN,
229
+
230
+
[QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS,
231
+
[QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV,
232
+
233
+
[QPHY_TX_TX_POL_INV] = QSERDES_V8_TX_TX_POL_INV,
234
+
[QPHY_TX_TX_DRV_LVL] = QSERDES_V8_TX_TX_DRV_LVL,
235
+
[QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V8_TX_TX_EMP_POST1_LVL,
236
+
[QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V8_TX_HIGHZ_DRVR_EN,
237
+
[QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V8_TX_TRANSCEIVER_BIAS_EN,
214
238
};
215
239
216
240
static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
···
1497
1471
QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG5, 0x10),
1498
1472
};
1499
1473
1474
+
static const struct qmp_phy_init_tbl sm8750_usb3_serdes_tbl[] = {
1475
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
1476
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1, 0x01),
1477
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE1, 0x02),
1478
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE1, 0x16),
1479
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE1, 0x36),
1480
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORECLK_DIV_MODE1, 0x04),
1481
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE1, 0x16),
1482
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE1, 0x41),
1483
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE1, 0x41),
1484
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE1, 0x00),
1485
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE1, 0x55),
1486
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE1, 0x75),
1487
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE1, 0x01),
1488
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_SEL_1, 0x01),
1489
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE1, 0x25),
1490
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE1, 0x02),
1491
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
1492
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
1493
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
1494
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
1495
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
1496
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1497
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE0, 0x02),
1498
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE0, 0x16),
1499
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE0, 0x36),
1500
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE0, 0x08),
1501
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE0, 0x1a),
1502
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE0, 0x41),
1503
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE0, 0x00),
1504
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE0, 0x55),
1505
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE0, 0x75),
1506
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE0, 0x01),
1507
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE0, 0x25),
1508
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE0, 0x02),
1509
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_BG_TIMER, 0x0a),
1510
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_EN_CENTER, 0x01),
1511
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER1, 0x62),
1512
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER2, 0x02),
1513
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_BUF_ENABLE, 0x0c),
1514
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_EN_SEL, 0x1a),
1515
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_CFG, 0x14),
1516
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_MAP, 0x04),
1517
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORE_CLK_EN, 0x20),
1518
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_CONFIG_1, 0x16),
1519
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
1520
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4a),
1521
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3, 0x36),
1522
+
QMP_PHY_INIT_CFG(QSERDES_V8_COM_ADDITIONAL_MISC, 0x0c),
1523
+
};
1524
+
1525
+
static const struct qmp_phy_init_tbl sm8750_usb3_tx_tbl[] = {
1526
+
QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_TX, 0x00),
1527
+
QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_RX, 0x00),
1528
+
QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1529
+
QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
1530
+
QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_1, 0xf5),
1531
+
QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_3, 0x11),
1532
+
QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_4, 0x31),
1533
+
QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_5, 0x5f),
1534
+
QMP_PHY_INIT_CFG(QSERDES_V8_TX_RCV_DETECT_LVL_2, 0x12),
1535
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x21, 1),
1536
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x05, 2),
1537
+
};
1538
+
1539
+
static const struct qmp_phy_init_tbl sm8750_usb3_rx_tbl[] = {
1540
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FO_GAIN, 0x0a),
1541
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_GAIN, 0x06),
1542
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1543
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1544
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1545
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1546
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_PI_CONTROLS, 0x99),
1547
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH1, 0x08),
1548
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH2, 0x08),
1549
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN1, 0x00),
1550
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN2, 0x0a),
1551
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_AUX_DATA_TCOARSE_TFINE, 0x20),
1552
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL1, 0x54),
1553
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL2, 0x0f),
1554
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_GM_CAL, 0x13),
1555
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1556
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1557
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1558
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_LOW, 0x07),
1559
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1560
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
1561
+
1562
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_ENABLES, 0x0c),
1563
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CNTRL, 0x04),
1564
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1565
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_LOW, 0x3f),
1566
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH, 0xbf),
1567
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH2, 0xff),
1568
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH3, 0xdf),
1569
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH4, 0xed),
1570
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_LOW, 0x19),
1571
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH, 0x09),
1572
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH2, 0x91),
1573
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH3, 0xb7),
1574
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH4, 0xaa),
1575
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_EN_TIMER, 0x04),
1576
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1577
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_DCC_CTRL1, 0x0c),
1578
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_VTH_CODE, 0x10),
1579
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_CTRL1, 0x14),
1580
+
QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_TRIM, 0x08),
1581
+
};
1582
+
1583
+
static const struct qmp_phy_init_tbl sm8750_usb3_pcs_tbl[] = {
1584
+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1585
+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG2, 0x89),
1586
+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG3, 0x20),
1587
+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG6, 0x13),
1588
+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_REFGEN_REQ_CONFIG1, 0x21),
1589
+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_RX_SIGDET_LVL, 0x55),
1590
+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1591
+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1592
+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_CDR_RESET_TIME, 0x0a),
1593
+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1594
+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1595
+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_PCS_TX_RX_CONFIG, 0x0c),
1596
+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG1, 0x4b),
1597
+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG5, 0x10),
1598
+
};
1599
+
1600
+
static const struct qmp_phy_init_tbl sm8750_usb3_pcs_usb_tbl[] = {
1601
+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1602
+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2, 0x07),
1603
+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_L, 0x40),
1604
+
QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_H, 0x00),
1605
+
};
1606
+
1500
1607
static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = {
1501
1608
QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1502
1609
QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
···
1938
1779
.usb3_pcs_usb = 0x1700,
1939
1780
.dp_serdes = 0x2000,
1940
1781
.dp_dp_phy = 0x2200,
1782
+
};
1783
+
1784
+
static const struct qmp_combo_offsets qmp_combo_offsets_v8 = {
1785
+
.com = 0x0000,
1786
+
.txa = 0x1400,
1787
+
.rxa = 0x1600,
1788
+
.txb = 0x1800,
1789
+
.rxb = 0x1a00,
1790
+
.usb3_serdes = 0x1000,
1791
+
.usb3_pcs_misc = 0x1c00,
1792
+
.usb3_pcs = 0x1e00,
1793
+
.usb3_pcs_usb = 0x2100,
1794
+
.dp_serdes = 0x3000,
1795
+
.dp_txa = 0x3400,
1796
+
.dp_txb = 0x3800,
1797
+
.dp_dp_phy = 0x3c00,
1941
1798
};
1942
1799
1943
1800
static const struct qmp_phy_cfg sar2130p_usb3dpphy_cfg = {
···
2449
2274
.calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
2450
2275
2451
2276
.regs = qmp_v6_usb3phy_regs_layout,
2277
+
.reset_list = msm8996_usb3phy_reset_l,
2278
+
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2279
+
.vreg_list = qmp_phy_vreg_l,
2280
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2281
+
};
2282
+
2283
+
static const struct qmp_phy_cfg sm8750_usb3dpphy_cfg = {
2284
+
.offsets = &qmp_combo_offsets_v8,
2285
+
2286
+
.serdes_tbl = sm8750_usb3_serdes_tbl,
2287
+
.serdes_tbl_num = ARRAY_SIZE(sm8750_usb3_serdes_tbl),
2288
+
.tx_tbl = sm8750_usb3_tx_tbl,
2289
+
.tx_tbl_num = ARRAY_SIZE(sm8750_usb3_tx_tbl),
2290
+
.rx_tbl = sm8750_usb3_rx_tbl,
2291
+
.rx_tbl_num = ARRAY_SIZE(sm8750_usb3_rx_tbl),
2292
+
.pcs_tbl = sm8750_usb3_pcs_tbl,
2293
+
.pcs_tbl_num = ARRAY_SIZE(sm8750_usb3_pcs_tbl),
2294
+
.pcs_usb_tbl = sm8750_usb3_pcs_usb_tbl,
2295
+
.pcs_usb_tbl_num = ARRAY_SIZE(sm8750_usb3_pcs_usb_tbl),
2296
+
2297
+
.dp_serdes_tbl = qmp_v6_dp_serdes_tbl,
2298
+
.dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
2299
+
.dp_tx_tbl = qmp_v6_dp_tx_tbl,
2300
+
.dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
2301
+
2302
+
.serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr,
2303
+
.serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
2304
+
.serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr,
2305
+
.serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
2306
+
.serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2,
2307
+
.serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
2308
+
.serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3,
2309
+
.serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
2310
+
2311
+
.swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr,
2312
+
.pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr,
2313
+
.swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
2314
+
.pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
2315
+
2316
+
.dp_aux_init = qmp_v4_dp_aux_init,
2317
+
.configure_dp_tx = qmp_v4_configure_dp_tx,
2318
+
.configure_dp_phy = qmp_v4_configure_dp_phy,
2319
+
.calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
2320
+
2321
+
.regs = qmp_v8_usb3phy_regs_layout,
2452
2322
.reset_list = msm8996_usb3phy_reset_l,
2453
2323
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2454
2324
.vreg_list = qmp_phy_vreg_l,
···
4134
3914
{
4135
3915
.compatible = "qcom,sm8650-qmp-usb3-dp-phy",
4136
3916
.data = &sm8650_usb3dpphy_cfg,
3917
+
},
3918
+
{
3919
+
.compatible = "qcom,sm8750-qmp-usb3-dp-phy",
3920
+
.data = &sm8750_usb3dpphy_cfg,
4137
3921
},
4138
3922
{
4139
3923
.compatible = "qcom,x1e80100-qmp-usb3-dp-phy",
+48
-41
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+48
-41
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
···
2639
2639
};
2640
2640
2641
2641
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rx_alt_tbl[] = {
2642
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
2642
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x07),
2643
2643
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2644
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9a),
2644
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b),
2645
2645
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),
2646
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92),
2646
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xe4),
2647
2647
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),
2648
2648
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),
2649
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x99),
2650
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
2651
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a),
2649
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00),
2650
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20),
2651
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b),
2652
2652
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb),
2653
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92),
2653
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xe4),
2654
2654
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec),
2655
2655
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),
2656
2656
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),
2657
2657
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
2658
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3),
2658
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xb3),
2659
2659
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8),
2660
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xec),
2661
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd6),
2662
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83),
2663
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf5),
2664
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x5e),
2660
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xed),
2661
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xe5),
2662
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x8d),
2663
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xd6),
2664
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7e),
2665
2665
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
2666
2666
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
2667
2667
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
···
2680
2680
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08),
2681
2681
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),
2682
2682
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),
2683
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08),
2684
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
2683
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x03),
2684
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x08),
2685
2685
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c),
2686
2686
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
2687
2687
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
2688
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05),
2688
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x01),
2689
2689
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
2690
2690
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
2691
2691
};
···
2699
2699
};
2700
2700
2701
2701
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_misc_tbl[] = {
2702
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V5_20_PCS_G3_RXEQEVAL_TIME, 0x27),
2703
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V5_20_PCS_G4_RXEQEVAL_TIME, 0x27),
2702
2704
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
2703
2705
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
2704
2706
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
···
2713
2711
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2714
2712
};
2715
2713
2716
-
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl[] = {
2714
+
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_alt_tbl[] = {
2717
2715
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
2718
2716
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
2719
2717
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
2720
2718
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66),
2719
+
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LOCK_DETECT_CONFIG1, 0xff),
2720
+
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LOCK_DETECT_CONFIG2, 0x89),
2721
+
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG1, 0x00),
2722
+
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG2, 0x50),
2723
+
};
2724
+
2725
+
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
2726
+
QMP_PHY_INIT_CFG(QSERDES_v5_LN_SHRD_UCDR_PI_CTRL2, 0x00),
2721
2727
};
2722
2728
2723
2729
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rx_alt_tbl[] = {
···
2749
2739
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
2750
2740
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
2751
2741
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
2752
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x99),
2742
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b),
2753
2743
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),
2754
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92),
2744
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xd2),
2755
2745
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),
2756
2746
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),
2757
2747
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00),
2758
2748
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20),
2759
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a),
2749
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b),
2760
2750
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xb6),
2761
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92),
2751
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xd2),
2762
2752
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xf0),
2763
2753
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),
2764
2754
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),
2765
2755
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
2766
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3),
2756
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xb3),
2767
2757
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf6),
2768
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xee),
2769
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd2),
2758
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xe4),
2759
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xe6),
2770
2760
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83),
2771
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf9),
2772
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x3d),
2761
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xd6),
2762
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7e),
2773
2763
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
2774
2764
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
2775
2765
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
···
2777
2767
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),
2778
2768
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
2779
2769
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),
2780
-
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08),
2781
-
};
2782
-
2783
-
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl[] = {
2784
-
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
2785
-
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
2786
-
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
2787
-
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66),
2770
+
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x06),
2788
2771
};
2789
2772
2790
2773
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl[] = {
···
3194
3191
.rx = 0x0200,
3195
3192
.tx2 = 0x0800,
3196
3193
.rx2 = 0x0a00,
3194
+
.ln_shrd = 0x0e00,
3197
3195
};
3198
3196
3199
3197
static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_30 = {
···
3402
3398
.tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
3403
3399
.rx = qcs8300_qmp_gen4x2_pcie_rx_alt_tbl,
3404
3400
.rx_num = ARRAY_SIZE(qcs8300_qmp_gen4x2_pcie_rx_alt_tbl),
3405
-
.pcs = sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl,
3406
-
.pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl),
3401
+
.pcs = sa8775p_qmp_gen4_pcie_pcs_alt_tbl,
3402
+
.pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl),
3407
3403
.pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
3408
3404
.pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
3409
3405
},
···
4071
4067
.tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
4072
4068
.rx = sa8775p_qmp_gen4x2_pcie_rx_alt_tbl,
4073
4069
.rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rx_alt_tbl),
4074
-
.pcs = sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl,
4075
-
.pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl),
4076
-
.pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
4070
+
.pcs = sa8775p_qmp_gen4_pcie_pcs_alt_tbl,
4071
+
.pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl),
4072
+
.pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
4077
4073
.pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
4078
4074
.pcs_lane1 = sdx65_qmp_pcie_pcs_lane1_tbl,
4079
4075
.pcs_lane1_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl),
4076
+
.ln_shrd = sa8775p_qmp_gen4x2_pcie_ln_shrd_tbl,
4077
+
.ln_shrd_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ln_shrd_tbl),
4078
+
4080
4079
},
4081
4080
4082
4081
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
···
4119
4112
.tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
4120
4113
.rx = sa8775p_qmp_gen4x4_pcie_rx_alt_tbl,
4121
4114
.rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rx_alt_tbl),
4122
-
.pcs = sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl,
4123
-
.pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl),
4115
+
.pcs = sa8775p_qmp_gen4_pcie_pcs_alt_tbl,
4116
+
.pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl),
4124
4117
.pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
4125
4118
.pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
4126
4119
},
+2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
+2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
···
13
13
#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
14
14
#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
15
15
#define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0
16
+
#define QPHY_PCIE_V5_20_PCS_G3_RXEQEVAL_TIME 0x0f0
17
+
#define QPHY_PCIE_V5_20_PCS_G4_RXEQEVAL_TIME 0x0f4
16
18
#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
17
19
#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
18
20
#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
+38
drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v8.h
+38
drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v8.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_PCS_USB_V8_H_
7
+
#define QCOM_PHY_QMP_PCS_USB_V8_H_
8
+
9
+
#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG1 0x00
10
+
#define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_STATUS 0x04
11
+
#define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL 0x08
12
+
#define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL2 0x0c
13
+
#define QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x10
14
+
#define QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR 0x14
15
+
#define QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL 0x18
16
+
#define QPHY_V8_PCS_USB_LFPS_TX_ECSTART 0x1c
17
+
#define QPHY_V8_PCS_USB_LFPS_PER_TIMER_VAL 0x20
18
+
#define QPHY_V8_PCS_USB_LFPS_TX_END_CNT_U3_START 0x24
19
+
#define QPHY_V8_PCS_USB_LFPS_CONFIG1 0x28
20
+
#define QPHY_V8_PCS_USB_RXEQTRAINING_LOCK_TIME 0x2c
21
+
#define QPHY_V8_PCS_USB_RXEQTRAINING_WAIT_TIME 0x30
22
+
#define QPHY_V8_PCS_USB_RXEQTRAINING_CTLE_TIME 0x34
23
+
#define QPHY_V8_PCS_USB_RXEQTRAINING_WAIT_TIME_S2 0x38
24
+
#define QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2 0x3c
25
+
#define QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_L 0x40
26
+
#define QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_H 0x44
27
+
#define QPHY_V8_PCS_USB_ARCVR_DTCT_EN_PERIOD 0x48
28
+
#define QPHY_V8_PCS_USB_ARCVR_DTCT_CM_DLY 0x4c
29
+
#define QPHY_V8_PCS_USB_TXONESZEROS_RUN_LENGTH 0x50
30
+
#define QPHY_V8_PCS_USB_ALFPS_DEGLITCH_VAL 0x54
31
+
#define QPHY_V8_PCS_USB_SIGDET_STARTUP_TIMER_VAL 0x58
32
+
#define QPHY_V8_PCS_USB_TEST_CONTROL 0x5c
33
+
#define QPHY_V8_PCS_USB_RXTERMINATION_DLY_SEL 0x60
34
+
#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG2 0x64
35
+
#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG3 0x68
36
+
#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG4 0x6c
37
+
38
+
#endif
+4
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h
+4
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h
···
8
8
9
9
#define QPHY_V5_20_PCS_INSIG_SW_CTRL7 0x060
10
10
#define QPHY_V5_20_PCS_INSIG_MX_CTRL7 0x07c
11
+
#define QPHY_V5_20_PCS_LOCK_DETECT_CONFIG1 0x0c4
12
+
#define QPHY_V5_20_PCS_LOCK_DETECT_CONFIG2 0x0c8
11
13
#define QPHY_V5_20_PCS_G3S2_PRE_GAIN 0x170
12
14
#define QPHY_V5_20_PCS_RX_SIGDET_LVL 0x188
15
+
#define QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG1 0x1b8
16
+
#define QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG2 0x1bc
13
17
#define QPHY_V5_20_PCS_EQ_CONFIG2 0x1d8
14
18
#define QPHY_V5_20_PCS_EQ_CONFIG4 0x1e0
15
19
#define QPHY_V5_20_PCS_EQ_CONFIG5 0x1e4
+32
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v8.h
+32
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v8.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_PCS_V8_H_
7
+
#define QCOM_PHY_QMP_PCS_V8_H_
8
+
9
+
/* Only for QMP V8 PHY - USB/PCIe PCS registers */
10
+
#define QPHY_V8_PCS_SW_RESET 0x000
11
+
#define QPHY_V8_PCS_PCS_STATUS1 0x014
12
+
#define QPHY_V8_PCS_POWER_DOWN_CONTROL 0x040
13
+
#define QPHY_V8_PCS_START_CONTROL 0x044
14
+
#define QPHY_V8_PCS_POWER_STATE_CONFIG1 0x090
15
+
#define QPHY_V8_PCS_LOCK_DETECT_CONFIG1 0x0c4
16
+
#define QPHY_V8_PCS_LOCK_DETECT_CONFIG2 0x0c8
17
+
#define QPHY_V8_PCS_LOCK_DETECT_CONFIG3 0x0cc
18
+
#define QPHY_V8_PCS_LOCK_DETECT_CONFIG6 0x0d8
19
+
#define QPHY_V8_PCS_REFGEN_REQ_CONFIG1 0x0dc
20
+
#define QPHY_V8_PCS_RX_SIGDET_LVL 0x188
21
+
#define QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
22
+
#define QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
23
+
#define QPHY_V8_PCS_RATE_SLEW_CNTRL1 0x198
24
+
#define QPHY_V8_PCS_CDR_RESET_TIME 0x1b0
25
+
#define QPHY_V8_PCS_ALIGN_DETECT_CONFIG1 0x1c0
26
+
#define QPHY_V8_PCS_ALIGN_DETECT_CONFIG2 0x1c4
27
+
#define QPHY_V8_PCS_PCS_TX_RX_CONFIG 0x1d0
28
+
#define QPHY_V8_PCS_EQ_CONFIG1 0x1dc
29
+
#define QPHY_V8_PCS_EQ_CONFIG2 0x1e0
30
+
#define QPHY_V8_PCS_EQ_CONFIG5 0x1ec
31
+
32
+
#endif
+64
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h
+64
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_QSERDES_COM_V8_H_
7
+
#define QCOM_PHY_QMP_QSERDES_COM_V8_H_
8
+
9
+
/* Only for QMP V8 PHY - QSERDES COM registers */
10
+
#define QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1 0x000
11
+
#define QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1 0x004
12
+
#define QSERDES_V8_COM_SSC_STEP_SIZE3_MODE1 0x008
13
+
#define QSERDES_V8_COM_CP_CTRL_MODE1 0x010
14
+
#define QSERDES_V8_COM_PLL_RCTRL_MODE1 0x014
15
+
#define QSERDES_V8_COM_PLL_CCTRL_MODE1 0x018
16
+
#define QSERDES_V8_COM_CORECLK_DIV_MODE1 0x01c
17
+
#define QSERDES_V8_COM_LOCK_CMP1_MODE1 0x020
18
+
#define QSERDES_V8_COM_LOCK_CMP2_MODE1 0x024
19
+
#define QSERDES_V8_COM_DEC_START_MODE1 0x028
20
+
#define QSERDES_V8_COM_DEC_START_MSB_MODE1 0x02c
21
+
#define QSERDES_V8_COM_DIV_FRAC_START1_MODE1 0x030
22
+
#define QSERDES_V8_COM_DIV_FRAC_START2_MODE1 0x034
23
+
#define QSERDES_V8_COM_DIV_FRAC_START3_MODE1 0x038
24
+
#define QSERDES_V8_COM_HSCLK_SEL_1 0x03c
25
+
#define QSERDES_V8_COM_VCO_TUNE1_MODE1 0x048
26
+
#define QSERDES_V8_COM_VCO_TUNE2_MODE1 0x04c
27
+
#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x050
28
+
#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x054
29
+
#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x058
30
+
#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x05c
31
+
#define QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0 0x060
32
+
#define QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0 0x064
33
+
#define QSERDES_V8_COM_CP_CTRL_MODE0 0x070
34
+
#define QSERDES_V8_COM_PLL_RCTRL_MODE0 0x074
35
+
#define QSERDES_V8_COM_PLL_CCTRL_MODE0 0x078
36
+
#define QSERDES_V8_COM_LOCK_CMP1_MODE0 0x080
37
+
#define QSERDES_V8_COM_LOCK_CMP2_MODE0 0x084
38
+
#define QSERDES_V8_COM_DEC_START_MODE0 0x088
39
+
#define QSERDES_V8_COM_DEC_START_MSB_MODE0 0x08c
40
+
#define QSERDES_V8_COM_DIV_FRAC_START1_MODE0 0x090
41
+
#define QSERDES_V8_COM_DIV_FRAC_START2_MODE0 0x094
42
+
#define QSERDES_V8_COM_DIV_FRAC_START3_MODE0 0x098
43
+
#define QSERDES_V8_COM_VCO_TUNE1_MODE0 0x0a8
44
+
#define QSERDES_V8_COM_VCO_TUNE2_MODE0 0x0ac
45
+
#define QSERDES_V8_COM_BG_TIMER 0x0bc
46
+
#define QSERDES_V8_COM_SSC_EN_CENTER 0x0c0
47
+
#define QSERDES_V8_COM_SSC_PER1 0x0cc
48
+
#define QSERDES_V8_COM_SSC_PER2 0x0d0
49
+
#define QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN 0x0dc
50
+
#define QSERDES_V8_COM_SYSCLK_BUF_ENABLE 0x0e8
51
+
#define QSERDES_V8_COM_SYSCLK_EN_SEL 0x110
52
+
#define QSERDES_V8_COM_RESETSM_CNTRL 0x118
53
+
#define QSERDES_V8_COM_LOCK_CMP_CFG 0x124
54
+
#define QSERDES_V8_COM_VCO_TUNE_MAP 0x140
55
+
#define QSERDES_V8_COM_CORE_CLK_EN 0x170
56
+
#define QSERDES_V8_COM_CMN_CONFIG_1 0x174
57
+
#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4
58
+
#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8
59
+
#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac
60
+
#define QSERDES_V8_COM_ADDITIONAL_MISC 0x1b4
61
+
#define QSERDES_V8_COM_CMN_STATUS 0x2c8
62
+
#define QSERDES_V8_COM_C_READY_STATUS 0x2f0
63
+
64
+
#endif
+11
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v5.h
+11
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v5.h
+68
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v8.h
+68
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v8.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V8_H_
7
+
#define QCOM_PHY_QMP_QSERDES_TXRX_V8_H_
8
+
9
+
#define QSERDES_V8_TX_TX_EMP_POST1_LVL 0x00c
10
+
#define QSERDES_V8_TX_TX_DRV_LVL 0x014
11
+
#define QSERDES_V8_TX_RES_CODE_LANE_TX 0x034
12
+
#define QSERDES_V8_TX_RES_CODE_LANE_RX 0x038
13
+
#define QSERDES_V8_TX_RES_CODE_LANE_OFFSET_TX 0x03c
14
+
#define QSERDES_V8_TX_RES_CODE_LANE_OFFSET_RX 0x040
15
+
#define QSERDES_V8_TX_TRANSCEIVER_BIAS_EN 0x054
16
+
#define QSERDES_V8_TX_HIGHZ_DRVR_EN 0x058
17
+
#define QSERDES_V8_TX_TX_POL_INV 0x05c
18
+
#define QSERDES_V8_TX_LANE_MODE_1 0x084
19
+
#define QSERDES_V8_TX_LANE_MODE_2 0x088
20
+
#define QSERDES_V8_TX_LANE_MODE_3 0x08c
21
+
#define QSERDES_V8_TX_LANE_MODE_4 0x090
22
+
#define QSERDES_V8_TX_LANE_MODE_5 0x094
23
+
#define QSERDES_V8_TX_RCV_DETECT_LVL_2 0x0a4
24
+
#define QSERDES_V8_TX_PI_QEC_CTRL 0x0e4
25
+
26
+
#define QSERDES_V8_RX_UCDR_FO_GAIN 0x008
27
+
#define QSERDES_V8_RX_UCDR_SO_GAIN 0x014
28
+
#define QSERDES_V8_RX_UCDR_SVS_FO_GAIN 0x020
29
+
#define QSERDES_V8_RX_UCDR_FASTLOCK_FO_GAIN 0x030
30
+
#define QSERDES_V8_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
31
+
#define QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
32
+
#define QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
33
+
#define QSERDES_V8_RX_UCDR_PI_CONTROLS 0x044
34
+
#define QSERDES_V8_RX_UCDR_SB2_THRESH1 0x04c
35
+
#define QSERDES_V8_RX_UCDR_SB2_THRESH2 0x050
36
+
#define QSERDES_V8_RX_UCDR_SB2_GAIN1 0x054
37
+
#define QSERDES_V8_RX_UCDR_SB2_GAIN2 0x058
38
+
#define QSERDES_V8_RX_AUX_DATA_TCOARSE_TFINE 0x060
39
+
#define QSERDES_V8_RX_VGA_CAL_CNTRL1 0x0d4
40
+
#define QSERDES_V8_RX_VGA_CAL_CNTRL2 0x0d8
41
+
#define QSERDES_V8_RX_GM_CAL 0x0dc
42
+
#define QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
43
+
#define QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
44
+
#define QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
45
+
#define QSERDES_V8_RX_RX_IDAC_TSETTLE_LOW 0x0f8
46
+
#define QSERDES_V8_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
47
+
#define QSERDES_V8_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
48
+
#define QSERDES_V8_RX_SIGDET_ENABLES 0x118
49
+
#define QSERDES_V8_RX_SIGDET_CNTRL 0x11c
50
+
#define QSERDES_V8_RX_SIGDET_DEGLITCH_CNTRL 0x124
51
+
#define QSERDES_V8_RX_RX_MODE_00_LOW 0x15c
52
+
#define QSERDES_V8_RX_RX_MODE_00_HIGH 0x160
53
+
#define QSERDES_V8_RX_RX_MODE_00_HIGH2 0x164
54
+
#define QSERDES_V8_RX_RX_MODE_00_HIGH3 0x168
55
+
#define QSERDES_V8_RX_RX_MODE_00_HIGH4 0x16c
56
+
#define QSERDES_V8_RX_RX_MODE_01_LOW 0x170
57
+
#define QSERDES_V8_RX_RX_MODE_01_HIGH 0x174
58
+
#define QSERDES_V8_RX_RX_MODE_01_HIGH2 0x178
59
+
#define QSERDES_V8_RX_RX_MODE_01_HIGH3 0x17c
60
+
#define QSERDES_V8_RX_RX_MODE_01_HIGH4 0x180
61
+
#define QSERDES_V8_RX_DFE_EN_TIMER 0x1a0
62
+
#define QSERDES_V8_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
63
+
#define QSERDES_V8_RX_DCC_CTRL1 0x1a8
64
+
#define QSERDES_V8_RX_VTH_CODE 0x1b0
65
+
#define QSERDES_V8_RX_SIGDET_CAL_CTRL1 0x1e4
66
+
#define QSERDES_V8_RX_SIGDET_CAL_TRIM 0x1f8
67
+
68
+
#endif
+42
-99
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+42
-99
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
···
1758
1758
qmp_ufs_init_all(qmp, &cfg->tbls_hs_b);
1759
1759
}
1760
1760
1761
-
static int qmp_ufs_com_init(struct qmp_ufs *qmp)
1761
+
static int qmp_ufs_power_on(struct phy *phy)
1762
1762
{
1763
+
struct qmp_ufs *qmp = phy_get_drvdata(phy);
1763
1764
const struct qmp_phy_cfg *cfg = qmp->cfg;
1764
1765
void __iomem *pcs = qmp->pcs;
1765
1766
int ret;
···
1776
1775
goto err_disable_regulators;
1777
1776
1778
1777
qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
1779
-
1780
1778
return 0;
1781
1779
1782
1780
err_disable_regulators:
1783
1781
regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1784
-
1785
1782
return ret;
1786
1783
}
1787
1784
1788
-
static int qmp_ufs_com_exit(struct qmp_ufs *qmp)
1789
-
{
1790
-
const struct qmp_phy_cfg *cfg = qmp->cfg;
1791
-
1792
-
reset_control_assert(qmp->ufs_reset);
1793
-
1794
-
clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
1795
-
1796
-
regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1797
-
1798
-
return 0;
1799
-
}
1800
-
1801
-
static int qmp_ufs_init(struct phy *phy)
1802
-
{
1803
-
struct qmp_ufs *qmp = phy_get_drvdata(phy);
1804
-
const struct qmp_phy_cfg *cfg = qmp->cfg;
1805
-
int ret;
1806
-
dev_vdbg(qmp->dev, "Initializing QMP phy\n");
1807
-
1808
-
if (cfg->no_pcs_sw_reset) {
1809
-
/*
1810
-
* Get UFS reset, which is delayed until now to avoid a
1811
-
* circular dependency where UFS needs its PHY, but the PHY
1812
-
* needs this UFS reset.
1813
-
*/
1814
-
if (!qmp->ufs_reset) {
1815
-
qmp->ufs_reset =
1816
-
devm_reset_control_get_exclusive(qmp->dev,
1817
-
"ufsphy");
1818
-
1819
-
if (IS_ERR(qmp->ufs_reset)) {
1820
-
ret = PTR_ERR(qmp->ufs_reset);
1821
-
dev_err(qmp->dev,
1822
-
"failed to get UFS reset: %d\n",
1823
-
ret);
1824
-
1825
-
qmp->ufs_reset = NULL;
1826
-
return ret;
1827
-
}
1828
-
}
1829
-
1830
-
ret = reset_control_assert(qmp->ufs_reset);
1831
-
if (ret)
1832
-
return ret;
1833
-
}
1834
-
1835
-
ret = qmp_ufs_com_init(qmp);
1836
-
if (ret)
1837
-
return ret;
1838
-
1839
-
return 0;
1840
-
}
1841
-
1842
-
static int qmp_ufs_power_on(struct phy *phy)
1785
+
static int qmp_ufs_phy_calibrate(struct phy *phy)
1843
1786
{
1844
1787
struct qmp_ufs *qmp = phy_get_drvdata(phy);
1845
1788
const struct qmp_phy_cfg *cfg = qmp->cfg;
···
1791
1846
void __iomem *status;
1792
1847
unsigned int val;
1793
1848
int ret;
1849
+
1850
+
ret = reset_control_assert(qmp->ufs_reset);
1851
+
if (ret)
1852
+
return ret;
1794
1853
1795
1854
qmp_ufs_init_registers(qmp, cfg);
1796
1855
···
1825
1876
struct qmp_ufs *qmp = phy_get_drvdata(phy);
1826
1877
const struct qmp_phy_cfg *cfg = qmp->cfg;
1827
1878
1828
-
/* PHY reset */
1829
-
if (!cfg->no_pcs_sw_reset)
1830
-
qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1831
-
1832
-
/* stop SerDes */
1833
-
qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START);
1834
-
1835
1879
/* Put PHY into POWER DOWN state: active low */
1836
1880
qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
1837
1881
SW_PWRDN);
1838
1882
1839
-
return 0;
1840
-
}
1883
+
clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
1841
1884
1842
-
static int qmp_ufs_exit(struct phy *phy)
1843
-
{
1844
-
struct qmp_ufs *qmp = phy_get_drvdata(phy);
1845
-
1846
-
qmp_ufs_com_exit(qmp);
1885
+
regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1847
1886
1848
1887
return 0;
1849
-
}
1850
-
1851
-
static int qmp_ufs_enable(struct phy *phy)
1852
-
{
1853
-
int ret;
1854
-
1855
-
ret = qmp_ufs_init(phy);
1856
-
if (ret)
1857
-
return ret;
1858
-
1859
-
ret = qmp_ufs_power_on(phy);
1860
-
if (ret)
1861
-
qmp_ufs_exit(phy);
1862
-
1863
-
return ret;
1864
-
}
1865
-
1866
-
static int qmp_ufs_disable(struct phy *phy)
1867
-
{
1868
-
int ret;
1869
-
1870
-
ret = qmp_ufs_power_off(phy);
1871
-
if (ret)
1872
-
return ret;
1873
-
return qmp_ufs_exit(phy);
1874
1888
}
1875
1889
1876
1890
static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
···
1852
1940
return 0;
1853
1941
}
1854
1942
1943
+
static int qmp_ufs_phy_init(struct phy *phy)
1944
+
{
1945
+
struct qmp_ufs *qmp = phy_get_drvdata(phy);
1946
+
const struct qmp_phy_cfg *cfg = qmp->cfg;
1947
+
int ret;
1948
+
1949
+
if (!cfg->no_pcs_sw_reset)
1950
+
return 0;
1951
+
1952
+
/*
1953
+
* Get UFS reset, which is delayed until now to avoid a
1954
+
* circular dependency where UFS needs its PHY, but the PHY
1955
+
* needs this UFS reset.
1956
+
*/
1957
+
if (!qmp->ufs_reset) {
1958
+
qmp->ufs_reset =
1959
+
devm_reset_control_get_exclusive(qmp->dev, "ufsphy");
1960
+
1961
+
if (IS_ERR(qmp->ufs_reset)) {
1962
+
ret = PTR_ERR(qmp->ufs_reset);
1963
+
dev_err(qmp->dev, "failed to get PHY reset: %d\n", ret);
1964
+
qmp->ufs_reset = NULL;
1965
+
return ret;
1966
+
}
1967
+
}
1968
+
1969
+
return 0;
1970
+
}
1971
+
1855
1972
static const struct phy_ops qcom_qmp_ufs_phy_ops = {
1856
-
.power_on = qmp_ufs_enable,
1857
-
.power_off = qmp_ufs_disable,
1973
+
.init = qmp_ufs_phy_init,
1974
+
.power_on = qmp_ufs_power_on,
1975
+
.power_off = qmp_ufs_power_off,
1976
+
.calibrate = qmp_ufs_phy_calibrate,
1858
1977
.set_mode = qmp_ufs_set_mode,
1859
1978
.owner = THIS_MODULE,
1860
1979
};
+6
drivers/phy/qualcomm/phy-qcom-qmp.h
+6
drivers/phy/qualcomm/phy-qcom-qmp.h
···
25
25
#include "phy-qcom-qmp-qserdes-txrx-v6.h"
26
26
#include "phy-qcom-qmp-qserdes-txrx-v6_20.h"
27
27
#include "phy-qcom-qmp-qserdes-txrx-v6_n4.h"
28
+
#include "phy-qcom-qmp-qserdes-ln-shrd-v5.h"
28
29
#include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
29
30
30
31
#include "phy-qcom-qmp-qserdes-com-v7.h"
31
32
#include "phy-qcom-qmp-qserdes-txrx-v7.h"
33
+
34
+
#include "phy-qcom-qmp-qserdes-com-v8.h"
35
+
#include "phy-qcom-qmp-qserdes-txrx-v8.h"
32
36
33
37
#include "phy-qcom-qmp-qserdes-pll.h"
34
38
···
55
51
#include "phy-qcom-qmp-pcs-v6_20.h"
56
52
57
53
#include "phy-qcom-qmp-pcs-v7.h"
54
+
55
+
#include "phy-qcom-qmp-pcs-v8.h"
58
56
59
57
/* QPHY_SW_RESET bit */
60
58
#define SW_RESET BIT(0)
+1
-3
drivers/phy/qualcomm/phy-qcom-qusb2.c
+1
-3
drivers/phy/qualcomm/phy-qcom-qusb2.c
···
1114
1114
phy_set_drvdata(generic_phy, qphy);
1115
1115
1116
1116
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1117
-
if (!IS_ERR(phy_provider))
1118
-
dev_info(dev, "Registered Qcom-QUSB2 phy\n");
1119
-
else
1117
+
if (IS_ERR(phy_provider))
1120
1118
pm_runtime_disable(dev);
1121
1119
1122
1120
return PTR_ERR_OR_ZERO(phy_provider);
+7
-8
drivers/phy/rockchip/phy-rockchip-pcie.c
+7
-8
drivers/phy/rockchip/phy-rockchip-pcie.c
···
30
30
#define PHY_CFG_ADDR_SHIFT 1
31
31
#define PHY_CFG_DATA_MASK 0xf
32
32
#define PHY_CFG_ADDR_MASK 0x3f
33
-
#define PHY_CFG_RD_MASK 0x3ff
34
33
#define PHY_CFG_WR_ENABLE 1
35
-
#define PHY_CFG_WR_DISABLE 1
34
+
#define PHY_CFG_WR_DISABLE 0
36
35
#define PHY_CFG_WR_SHIFT 0
37
36
#define PHY_CFG_WR_MASK 1
38
37
#define PHY_CFG_PLL_LOCK 0x10
···
159
160
160
161
guard(mutex)(&rk_phy->pcie_mutex);
161
162
163
+
regmap_write(rk_phy->reg_base,
164
+
rk_phy->phy_data->pcie_laneoff,
165
+
HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
166
+
PHY_LANE_IDLE_MASK,
167
+
PHY_LANE_IDLE_A_SHIFT + inst->index));
168
+
162
169
if (rk_phy->pwr_cnt++) {
163
170
return 0;
164
171
}
···
180
175
HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
181
176
PHY_CFG_ADDR_MASK,
182
177
PHY_CFG_ADDR_SHIFT));
183
-
184
-
regmap_write(rk_phy->reg_base,
185
-
rk_phy->phy_data->pcie_laneoff,
186
-
HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
187
-
PHY_LANE_IDLE_MASK,
188
-
PHY_LANE_IDLE_A_SHIFT + inst->index));
189
178
190
179
/*
191
180
* No documented timeout value for phy operation below,
+52
drivers/phy/samsung/phy-exynos-mipi-video.c
+52
drivers/phy/samsung/phy-exynos-mipi-video.c
···
213
213
},
214
214
};
215
215
216
+
static const struct mipi_phy_device_desc exynos7870_mipi_phy = {
217
+
.num_regmaps = 3,
218
+
.regmap_names = {
219
+
"samsung,pmu-syscon",
220
+
"samsung,disp-sysreg",
221
+
"samsung,cam0-sysreg"
222
+
},
223
+
.num_phys = 4,
224
+
.phys = {
225
+
{
226
+
/* EXYNOS_MIPI_PHY_ID_CSIS0 */
227
+
.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
228
+
.enable_val = EXYNOS4_PHY_ENABLE,
229
+
.enable_reg = EXYNOS7870_MIPI_PHY_CONTROL0,
230
+
.enable_map = EXYNOS_MIPI_REGMAP_PMU,
231
+
.resetn_val = BIT(0),
232
+
.resetn_reg = 0,
233
+
.resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
234
+
}, {
235
+
/* EXYNOS_MIPI_PHY_ID_DSIM0 */
236
+
.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
237
+
.enable_val = EXYNOS4_PHY_ENABLE,
238
+
.enable_reg = EXYNOS7870_MIPI_PHY_CONTROL0,
239
+
.enable_map = EXYNOS_MIPI_REGMAP_PMU,
240
+
.resetn_val = BIT(0),
241
+
.resetn_reg = 0,
242
+
.resetn_map = EXYNOS_MIPI_REGMAP_DISP,
243
+
}, {
244
+
/* EXYNOS_MIPI_PHY_ID_CSIS1 */
245
+
.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
246
+
.enable_val = EXYNOS4_PHY_ENABLE,
247
+
.enable_reg = EXYNOS7870_MIPI_PHY_CONTROL1,
248
+
.enable_map = EXYNOS_MIPI_REGMAP_PMU,
249
+
.resetn_val = BIT(1),
250
+
.resetn_reg = 0,
251
+
.resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
252
+
}, {
253
+
/* EXYNOS_MIPI_PHY_ID_CSIS2 */
254
+
.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
255
+
.enable_val = EXYNOS4_PHY_ENABLE,
256
+
.enable_reg = EXYNOS7870_MIPI_PHY_CONTROL2,
257
+
.enable_map = EXYNOS_MIPI_REGMAP_PMU,
258
+
.resetn_val = BIT(2),
259
+
.resetn_reg = 0,
260
+
.resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
261
+
},
262
+
},
263
+
};
264
+
216
265
struct exynos_mipi_video_phy {
217
266
struct regmap *regmaps[EXYNOS_MIPI_REGMAPS_NUM];
218
267
int num_phys;
···
400
351
}, {
401
352
.compatible = "samsung,exynos5433-mipi-video-phy",
402
353
.data = &exynos5433_mipi_phy,
354
+
}, {
355
+
.compatible = "samsung,exynos7870-mipi-video-phy",
356
+
.data = &exynos7870_mipi_phy,
403
357
},
404
358
{ /* sentinel */ },
405
359
};
+32
drivers/phy/samsung/phy-exynos5-usbdrd.c
+32
drivers/phy/samsung/phy-exynos5-usbdrd.c
···
2025
2025
.n_regulators = ARRAY_SIZE(exynos5_regulator_names),
2026
2026
};
2027
2027
2028
+
static const struct exynos5_usbdrd_phy_tuning exynos990_tunes_utmi_postinit[] = {
2029
+
PHY_TUNING_ENTRY_PHY(EXYNOS850_DRD_HSPPARACON,
2030
+
(HSPPARACON_TXVREF |
2031
+
HSPPARACON_TXPREEMPAMP | HSPPARACON_SQRX |
2032
+
HSPPARACON_COMPDIS),
2033
+
(FIELD_PREP_CONST(HSPPARACON_TXVREF, 7) |
2034
+
FIELD_PREP_CONST(HSPPARACON_TXPREEMPAMP, 3) |
2035
+
FIELD_PREP_CONST(HSPPARACON_SQRX, 5) |
2036
+
FIELD_PREP_CONST(HSPPARACON_COMPDIS, 7))),
2037
+
PHY_TUNING_ENTRY_LAST
2038
+
};
2039
+
2040
+
static const struct exynos5_usbdrd_phy_tuning *exynos990_tunes[PTS_MAX] = {
2041
+
[PTS_UTMI_POSTINIT] = exynos990_tunes_utmi_postinit,
2042
+
};
2043
+
2044
+
static const struct exynos5_usbdrd_phy_drvdata exynos990_usbdrd_phy = {
2045
+
.phy_cfg = phy_cfg_exynos850,
2046
+
.phy_ops = &exynos850_usbdrd_phy_ops,
2047
+
.phy_tunes = exynos990_tunes,
2048
+
.pmu_offset_usbdrd0_phy = EXYNOS990_PHY_CTRL_USB20,
2049
+
.clk_names = exynos5_clk_names,
2050
+
.n_clks = ARRAY_SIZE(exynos5_clk_names),
2051
+
.core_clk_names = exynos5_core_clk_names,
2052
+
.n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
2053
+
.regulator_names = exynos5_regulator_names,
2054
+
.n_regulators = ARRAY_SIZE(exynos5_regulator_names),
2055
+
};
2056
+
2028
2057
static const struct exynos5_usbdrd_phy_config phy_cfg_gs101[] = {
2029
2058
{
2030
2059
.id = EXYNOS5_DRDPHY_UTMI,
···
2257
2228
}, {
2258
2229
.compatible = "samsung,exynos850-usbdrd-phy",
2259
2230
.data = &exynos850_usbdrd_phy
2231
+
}, {
2232
+
.compatible = "samsung,exynos990-usbdrd-phy",
2233
+
.data = &exynos990_usbdrd_phy
2260
2234
},
2261
2235
{ },
2262
2236
};
-2
drivers/phy/st/phy-stih407-usb.c
-2
drivers/phy/st/phy-stih407-usb.c
+2
-2
drivers/phy/st/phy-stm32-usbphyc.c
+2
-2
drivers/phy/st/phy-stm32-usbphyc.c
···
757
757
}
758
758
759
759
version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
760
-
dev_info(dev, "registered rev:%lu.%lu\n",
761
-
FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
760
+
dev_dbg(dev, "registered rev: %lu.%lu\n",
761
+
FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
762
762
763
763
return 0;
764
764
-1
drivers/phy/ti/phy-twl4030-usb.c
-1
drivers/phy/ti/phy-twl4030-usb.c
+35
-31
drivers/ufs/host/ufs-qcom.c
+35
-31
drivers/ufs/host/ufs-qcom.c
···
532
532
goto out_disable_phy;
533
533
}
534
534
535
+
ret = phy_calibrate(phy);
536
+
if (ret) {
537
+
dev_err(hba->dev, "Failed to calibrate PHY: %d\n", ret);
538
+
goto out_disable_phy;
539
+
}
540
+
535
541
ufs_qcom_select_unipro_mode(host);
536
542
537
543
return 0;
···
732
726
enum ufs_notify_change_status status)
733
727
{
734
728
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
735
-
struct phy *phy = host->generic_phy;
736
729
737
730
if (status == PRE_CHANGE)
738
731
return 0;
739
732
740
-
if (ufs_qcom_is_link_off(hba)) {
741
-
/*
742
-
* Disable the tx/rx lane symbol clocks before PHY is
743
-
* powered down as the PLL source should be disabled
744
-
* after downstream clocks are disabled.
745
-
*/
733
+
if (!ufs_qcom_is_link_active(hba))
746
734
ufs_qcom_disable_lane_clks(host);
747
-
phy_power_off(phy);
748
735
749
-
/* reset the connected UFS device during power down */
736
+
737
+
/* reset the connected UFS device during power down */
738
+
if (ufs_qcom_is_link_off(hba) && host->device_reset)
750
739
ufs_qcom_device_reset_ctrl(hba, true);
751
-
752
-
} else if (!ufs_qcom_is_link_active(hba)) {
753
-
ufs_qcom_disable_lane_clks(host);
754
-
}
755
740
756
741
return ufs_qcom_ice_suspend(host);
757
742
}
···
750
753
static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
751
754
{
752
755
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
753
-
struct phy *phy = host->generic_phy;
754
756
int err;
755
757
756
-
if (ufs_qcom_is_link_off(hba)) {
757
-
err = phy_power_on(phy);
758
-
if (err) {
759
-
dev_err(hba->dev, "%s: failed PHY power on: %d\n",
760
-
__func__, err);
761
-
return err;
762
-
}
763
-
764
-
err = ufs_qcom_enable_lane_clks(host);
765
-
if (err)
766
-
return err;
767
-
768
-
} else if (!ufs_qcom_is_link_active(hba)) {
769
-
err = ufs_qcom_enable_lane_clks(host);
770
-
if (err)
771
-
return err;
772
-
}
758
+
err = ufs_qcom_enable_lane_clks(host);
759
+
if (err)
760
+
return err;
773
761
774
762
return ufs_qcom_ice_resume(host);
775
763
}
···
1133
1151
* @on: If true, enable clocks else disable them.
1134
1152
* @status: PRE_CHANGE or POST_CHANGE notify
1135
1153
*
1154
+
* There are certain clocks which comes from the PHY so it needs
1155
+
* to be managed together along with controller clocks which also
1156
+
* provides a better power saving. Hence keep phy_power_off/on calls
1157
+
* in ufs_qcom_setup_clocks, so that PHY's regulators & clks can be
1158
+
* turned on/off along with UFS's clocks.
1159
+
*
1136
1160
* Return: 0 on success, non-zero on failure.
1137
1161
*/
1138
1162
static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
1139
1163
enum ufs_notify_change_status status)
1140
1164
{
1141
1165
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1166
+
struct phy *phy;
1167
+
int err;
1142
1168
1143
1169
/*
1144
1170
* In case ufs_qcom_init() is not yet done, simply ignore.
···
1155
1165
*/
1156
1166
if (!host)
1157
1167
return 0;
1168
+
1169
+
phy = host->generic_phy;
1158
1170
1159
1171
switch (status) {
1160
1172
case PRE_CHANGE:
···
1167
1175
/* disable device ref_clk */
1168
1176
ufs_qcom_dev_ref_clk_ctrl(host, false);
1169
1177
}
1178
+
1179
+
err = phy_power_off(phy);
1180
+
if (err) {
1181
+
dev_err(hba->dev, "phy power off failed, ret=%d\n", err);
1182
+
return err;
1183
+
}
1170
1184
}
1171
1185
break;
1172
1186
case POST_CHANGE:
1173
1187
if (on) {
1188
+
err = phy_power_on(phy);
1189
+
if (err) {
1190
+
dev_err(hba->dev, "phy power on failed, ret = %d\n", err);
1191
+
return err;
1192
+
}
1193
+
1174
1194
/* enable the device ref clock for HS mode*/
1175
1195
if (ufshcd_is_hs_mode(&hba->pwr_info))
1176
1196
ufs_qcom_dev_ref_clk_ctrl(host, true);
+8
include/linux/soc/samsung/exynos-regs-pmu.h
+8
include/linux/soc/samsung/exynos-regs-pmu.h
···
662
662
#define EXYNOS5433_PAD_RETENTION_UFS_OPTION (0x3268)
663
663
#define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION (0x32A8)
664
664
665
+
/* For Exynos990 */
666
+
#define EXYNOS990_PHY_CTRL_USB20 (0x72C)
667
+
668
+
/* For Exynos7870 */
669
+
#define EXYNOS7870_MIPI_PHY_CONTROL0 (0x070c)
670
+
#define EXYNOS7870_MIPI_PHY_CONTROL1 (0x0714)
671
+
#define EXYNOS7870_MIPI_PHY_CONTROL2 (0x0734)
672
+
665
673
/* For Tensor GS101 */
666
674
/* PMU ALIVE */
667
675
#define GS101_SYSIP_DAT0 (0x810)