tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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phy: qcom-qmp: Add support for SDX65 QMP PHY

Add support for USB3 QMP PHY found in SDX65 platform. SDX65 uses
version 5.0.0 of the QMP PHY IP.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/1649740652-17515-3-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Rohit Agarwal and committed by
Vinod Koul 8585b1be aa1855a7

+76
+76
drivers/phy/qualcomm/phy-qcom-qmp.c
··· 2535 2535 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 2536 2536 }; 2537 2537 2538 + static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = { 2539 + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 2540 + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 2541 + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 2542 + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 2543 + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 2544 + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 2545 + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b), 2546 + }; 2547 + 2548 + static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = { 2549 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 2550 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 2551 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 2552 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 2553 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 2554 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 2555 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 2556 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 2557 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 2558 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 2559 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 2560 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 2561 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 2562 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 2563 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 2564 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 2565 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 2566 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 2567 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 2568 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 2569 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 2570 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 2571 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 2572 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 2573 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 2574 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 2575 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 2576 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2577 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 2578 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 2579 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 2580 + }; 2581 + 2538 2582 static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { 2539 2583 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), 2540 2584 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), ··· 4259 4215 .has_pwrdn_delay = true, 4260 4216 .pwrdn_delay_min = 995, /* us */ 4261 4217 .pwrdn_delay_max = 1005, /* us */ 4218 + }; 4219 + 4220 + static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { 4221 + .type = PHY_TYPE_USB3, 4222 + .nlanes = 1, 4223 + 4224 + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 4225 + .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 4226 + .tx_tbl = sdx65_usb3_uniphy_tx_tbl, 4227 + .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl), 4228 + .rx_tbl = sdx65_usb3_uniphy_rx_tbl, 4229 + .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl), 4230 + .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, 4231 + .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), 4232 + .clk_list = qmp_v4_sdx55_usbphy_clk_l, 4233 + .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), 4234 + .reset_list = msm8996_usb3phy_reset_l, 4235 + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 4236 + .vreg_list = qmp_phy_vreg_l, 4237 + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4238 + .regs = sm8350_usb3_uniphy_regs_layout, 4239 + 4240 + .start_ctrl = SERDES_START | PCS_START, 4241 + .pwrdn_ctrl = SW_PWRDN, 4242 + .phy_status = PHYSTATUS, 4243 + 4244 + .has_pwrdn_delay = true, 4245 + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 4246 + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 4262 4247 }; 4263 4248 4264 4249 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { ··· 6122 6049 }, { 6123 6050 .compatible = "qcom,sdx55-qmp-usb3-uni-phy", 6124 6051 .data = &sdx55_usb3_uniphy_cfg, 6052 + }, { 6053 + .compatible = "qcom,sdx65-qmp-usb3-uni-phy", 6054 + .data = &sdx65_usb3_uniphy_cfg, 6125 6055 }, { 6126 6056 .compatible = "qcom,sm8350-qmp-usb3-phy", 6127 6057 .data = &sm8350_usb3phy_cfg,