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Merge tag 'x86-cleanups-2025-01-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 cleanups from Ingo Molnar:
"Miscellaneous x86 cleanups and typo fixes, and also the removal of
the 'disablelapic' boot parameter"

* tag 'x86-cleanups-2025-01-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/ioapic: Remove a stray tab in the IO-APIC type string
x86/cpufeatures: Remove "AMD" from the comments to the AMD-specific leaf
Documentation/kernel-parameters: Fix a typo in kvm.enable_virt_at_load text
x86/cpu: Fix typo in x86_match_cpu()'s doc
x86/apic: Remove "disablelapic" cmdline option
Documentation: Merge x86-specific boot options doc into kernel-parameters.txt
x86/ioremap: Remove unused size parameter in remapping functions
x86/ioremap: Simplify setup_data mapping variants
x86/boot/compressed: Remove unused header includes from kaslr.c

Linus Torvalds 858df1de 6c4aa896

+278 -435
-3
Documentation/admin-guide/kernel-parameters.rst
··· 194 194 WDT Watchdog support is enabled. 195 195 X86-32 X86-32, aka i386 architecture is enabled. 196 196 X86-64 X86-64 architecture is enabled. 197 - More X86-64 boot options can be found in 198 - Documentation/arch/x86/x86_64/boot-options.rst. 199 197 X86 Either 32-bit or 64-bit x86 (same as X86-32+X86-64) 200 198 X86_UV SGI UV support is enabled. 201 199 XEN Xen support is enabled ··· 211 213 need or coordination with <Documentation/arch/x86/boot.rst>. 212 214 213 215 There are also arch-specific kernel-parameters not documented here. 214 - See for example <Documentation/arch/x86/x86_64/boot-options.rst>. 215 216 216 217 Note that ALL kernel parameters listed below are CASE SENSITIVE, and that 217 218 a trailing = on the name of any parameter states that that parameter will
+226 -13
Documentation/admin-guide/kernel-parameters.txt
··· 21 21 strictly ACPI specification compliant. 22 22 rsdt -- prefer RSDT over (default) XSDT 23 23 copy_dsdt -- copy DSDT to memory 24 + nocmcff -- Disable firmware first mode for corrected 25 + errors. This disables parsing the HEST CMC error 26 + source to check if firmware has set the FF flag. This 27 + may result in duplicate corrected error reports. 24 28 nospcr -- disable console in ACPI SPCR table as 25 29 default _serial_ console on ARM64 26 30 For ARM64, ONLY "acpi=off", "acpi=on", "acpi=force" or ··· 409 405 not play well with APC CPU idle - disable it if you have 410 406 APC and your system crashes randomly. 411 407 408 + apic [APIC,X86-64] Use IO-APIC. Default. 409 + 412 410 apic= [APIC,X86,EARLY] Advanced Programmable Interrupt Controller 413 411 Change the output verbosity while booting 414 412 Format: { quiet (default) | verbose | debug } ··· 429 423 none: External NMI is masked for all CPUs. This is 430 424 useful so that a dump capture kernel won't be 431 425 shot down by NMI 426 + 427 + apicpmtimer Do APIC timer calibration using the pmtimer. Implies 428 + apicmaintimer. Useful when your PIT timer is totally 429 + broken. 432 430 433 431 autoconf= [IPV6] 434 432 See Documentation/networking/ipv6.rst. ··· 1736 1726 1737 1727 off: Disable GDS mitigation. 1738 1728 1729 + gbpages [X86] Use GB pages for kernel direct mappings. 1730 + 1739 1731 gcov_persist= [GCOV] When non-zero (default), profiling data for 1740 1732 kernel modules is saved and remains accessible via 1741 1733 debugfs, even when the module is unloaded/reloaded. ··· 2020 2008 2021 2009 idle= [X86,EARLY] 2022 2010 Format: idle=poll, idle=halt, idle=nomwait 2023 - Poll forces a polling idle loop that can slightly 2024 - improve the performance of waking up a idle CPU, but 2025 - will use a lot of power and make the system run hot. 2026 - Not recommended. 2011 + 2012 + idle=poll: Don't do power saving in the idle loop 2013 + using HLT, but poll for rescheduling event. This will 2014 + make the CPUs eat a lot more power, but may be useful 2015 + to get slightly better performance in multiprocessor 2016 + benchmarks. It also makes some profiling using 2017 + performance counters more accurate. Please note that 2018 + on systems with MONITOR/MWAIT support (like Intel 2019 + EM64T CPUs) this option has no performance advantage 2020 + over the normal idle loop. It may also interact badly 2021 + with hyperthreading. 2022 + 2027 2023 idle=halt: Halt is forced to be used for CPU idle. 2028 2024 In such case C2/C3 won't be used again. 2025 + 2029 2026 idle=nomwait: Disable mwait for CPU C-states 2030 2027 2031 2028 idxd.sva= [HW] ··· 2332 2311 relaxed 2333 2312 2334 2313 iommu= [X86,EARLY] 2314 + 2335 2315 off 2316 + Don't initialize and use any kind of IOMMU. 2317 + 2336 2318 force 2319 + Force the use of the hardware IOMMU even when 2320 + it is not actually needed (e.g. because < 3 GB 2321 + memory). 2322 + 2337 2323 noforce 2324 + Don't force hardware IOMMU usage when it is not 2325 + needed. (default). 2326 + 2338 2327 biomerge 2339 2328 panic 2340 2329 nopanic 2341 2330 merge 2342 2331 nomerge 2332 + 2343 2333 soft 2344 - pt [X86] 2345 - nopt [X86] 2346 - nobypass [PPC/POWERNV] 2334 + Use software bounce buffering (SWIOTLB) (default for 2335 + Intel machines). This can be used to prevent the usage 2336 + of an available hardware IOMMU. 2337 + 2338 + [X86] 2339 + pt 2340 + [X86] 2341 + nopt 2342 + [PPC/POWERNV] 2343 + nobypass 2347 2344 Disable IOMMU bypass, using IOMMU for PCI devices. 2345 + 2346 + [X86] 2347 + AMD Gart HW IOMMU-specific options: 2348 + 2349 + <size> 2350 + Set the size of the remapping area in bytes. 2351 + 2352 + allowed 2353 + Overwrite iommu off workarounds for specific chipsets 2354 + 2355 + fullflush 2356 + Flush IOMMU on each allocation (default). 2357 + 2358 + nofullflush 2359 + Don't use IOMMU fullflush. 2360 + 2361 + memaper[=<order>] 2362 + Allocate an own aperture over RAM with size 2363 + 32MB<<order. (default: order=1, i.e. 64MB) 2364 + 2365 + merge 2366 + Do scatter-gather (SG) merging. Implies "force" 2367 + (experimental). 2368 + 2369 + nomerge 2370 + Don't do scatter-gather (SG) merging. 2371 + 2372 + noaperture 2373 + Ask the IOMMU not to touch the aperture for AGP. 2374 + 2375 + noagp 2376 + Don't initialize the AGP driver and use full aperture. 2377 + 2378 + panic 2379 + Always panic when IOMMU overflows. 2348 2380 2349 2381 iommu.forcedac= [ARM64,X86,EARLY] Control IOVA allocation for PCI devices. 2350 2382 Format: { "0" | "1" } ··· 2769 2695 VMs, i.e. on the 0=>1 and 1=>0 transitions of the 2770 2696 number of VMs. 2771 2697 2772 - Enabling virtualization at module lode avoids potential 2698 + Enabling virtualization at module load avoids potential 2773 2699 latency for creation of the 0=>1 VM, as KVM serializes 2774 2700 virtualization enabling across all online CPUs. The 2775 2701 "cost" of enabling virtualization when KVM is loaded, ··· 3333 3259 devices can be requested on-demand with the 3334 3260 /dev/loop-control interface. 3335 3261 3336 - mce [X86-32] Machine Check Exception 3262 + mce= [X86-{32,64}] 3337 3263 3338 - mce=option [X86-64] See Documentation/arch/x86/x86_64/boot-options.rst 3264 + Please see Documentation/arch/x86/x86_64/machinecheck.rst for sysfs runtime tunables. 3265 + 3266 + off 3267 + disable machine check 3268 + 3269 + no_cmci 3270 + disable CMCI(Corrected Machine Check Interrupt) that 3271 + Intel processor supports. Usually this disablement is 3272 + not recommended, but it might be handy if your 3273 + hardware is misbehaving. 3274 + 3275 + Note that you'll get more problems without CMCI than 3276 + with due to the shared banks, i.e. you might get 3277 + duplicated error logs. 3278 + 3279 + dont_log_ce 3280 + don't make logs for corrected errors. All events 3281 + reported as corrected are silently cleared by OS. This 3282 + option will be useful if you have no interest in any 3283 + of corrected errors. 3284 + 3285 + ignore_ce 3286 + disable features for corrected errors, e.g. 3287 + polling timer and CMCI. All events reported as 3288 + corrected are not cleared by OS and remained in its 3289 + error banks. 3290 + 3291 + Usually this disablement is not recommended, however 3292 + if there is an agent checking/clearing corrected 3293 + errors (e.g. BIOS or hardware monitoring 3294 + applications), conflicting with OS's error handling, 3295 + and you cannot deactivate the agent, then this option 3296 + will be a help. 3297 + 3298 + no_lmce 3299 + do not opt-in to Local MCE delivery. Use legacy method 3300 + to broadcast MCEs. 3301 + 3302 + bootlog 3303 + enable logging of machine checks left over from 3304 + booting. Disabled by default on AMD Fam10h and older 3305 + because some BIOS leave bogus ones. 3306 + 3307 + If your BIOS doesn't do that it's a good idea to 3308 + enable though to make sure you log even machine check 3309 + events that result in a reboot. On Intel systems it is 3310 + enabled by default. 3311 + 3312 + nobootlog 3313 + disable boot machine check logging. 3314 + 3315 + monarchtimeout (number) 3316 + sets the time in us to wait for other CPUs on machine 3317 + checks. 0 to disable. 3318 + 3319 + bios_cmci_threshold 3320 + don't overwrite the bios-set CMCI threshold. This boot 3321 + option prevents Linux from overwriting the CMCI 3322 + threshold set by the bios. Without this option, Linux 3323 + always sets the CMCI threshold to 1. Enabling this may 3324 + make memory predictive failure analysis less effective 3325 + if the bios sets thresholds for memory errors since we 3326 + will not see details for all errors. 3327 + 3328 + recovery 3329 + force-enable recoverable machine check code paths 3330 + 3331 + Everything else is in sysfs now. 3332 + 3339 3333 3340 3334 md= [HW] RAID subsystems devices and level 3341 3335 See Documentation/admin-guide/md.rst. ··· 4029 3887 noapic [SMP,APIC,EARLY] Tells the kernel to not make use of any 4030 3888 IOAPICs that may be present in the system. 4031 3889 3890 + noapictimer [APIC,X86] Don't set up the APIC timer 3891 + 4032 3892 noautogroup Disable scheduler automatic task group creation. 4033 3893 4034 3894 nocache [ARM,EARLY] ··· 4078 3934 register save and restore. The kernel will only save 4079 3935 legacy floating-point registers on task switch. 4080 3936 3937 + nogbpages [X86] Do not use GB pages for kernel direct mappings. 3938 + 4081 3939 no_hash_pointers 4082 3940 [KNL,EARLY] 4083 3941 Force pointers printed to the console or buffers to be ··· 4105 3959 correctly or when doing power measurements to evaluate 4106 3960 the impact of the sleep instructions. This is also 4107 3961 useful when using JTAG debugger. 3962 + 3963 + nohpet [X86] Don't use the HPET timer. 4108 3964 4109 3965 nohugeiomap [KNL,X86,PPC,ARM64,EARLY] Disable kernel huge I/O mappings. 4110 3966 ··· 4259 4111 4260 4112 nosync [HW,M68K] Disables sync negotiation for all devices. 4261 4113 4262 - no_timer_check [X86,APIC] Disables the code which tests for 4263 - broken timer IRQ sources. 4114 + no_timer_check [X86,APIC] Disables the code which tests for broken 4115 + timer IRQ sources, i.e., the IO-APIC timer. This can 4116 + work around problems with incorrect timer 4117 + initialization on some boards. 4264 4118 4265 4119 no_uaccess_flush 4266 4120 [PPC,EARLY] Don't flush the L1-D cache after accessing user data. ··· 4341 4191 [KNL, ARM64, RISCV, X86, EARLY] 4342 4192 If given as an integer followed by 'U', it will 4343 4193 divide each physical node into N emulated nodes. 4194 + 4195 + numa=noacpi [X86] Don't parse the SRAT table for NUMA setup 4196 + 4197 + numa=nohmat [X86] Don't parse the HMAT table for NUMA setup, or 4198 + soft-reserved memory partitioning. 4344 4199 4345 4200 numa_balancing= [KNL,ARM64,PPC,RISCV,S390,X86] Enable or disable automatic 4346 4201 NUMA balancing. ··· 5870 5715 reboot_cpu is s[mp]#### with #### being the processor 5871 5716 to be used for rebooting. 5872 5717 5718 + acpi 5719 + Use the ACPI RESET_REG in the FADT. If ACPI is not 5720 + configured or the ACPI reset does not work, the reboot 5721 + path attempts the reset using the keyboard controller. 5722 + 5723 + bios 5724 + Use the CPU reboot vector for warm reset 5725 + 5726 + cold 5727 + Set the cold reboot flag 5728 + 5729 + default 5730 + There are some built-in platform specific "quirks" 5731 + - you may see: "reboot: <name> series board detected. 5732 + Selecting <type> for reboots." In the case where you 5733 + think the quirk is in error (e.g. you have newer BIOS, 5734 + or newer board) using this option will ignore the 5735 + built-in quirk table, and use the generic default 5736 + reboot actions. 5737 + 5738 + efi 5739 + Use efi reset_system runtime service. If EFI is not 5740 + configured or the EFI reset does not work, the reboot 5741 + path attempts the reset using the keyboard controller. 5742 + 5743 + force 5744 + Don't stop other CPUs on reboot. This can make reboot 5745 + more reliable in some cases. 5746 + 5747 + kbd 5748 + Use the keyboard controller. cold reset (default) 5749 + 5750 + pci 5751 + Use a write to the PCI config space register 0xcf9 to 5752 + trigger reboot. 5753 + 5754 + triple 5755 + Force a triple fault (init) 5756 + 5757 + warm 5758 + Don't set the cold reboot flag 5759 + 5760 + Using warm reset will be much faster especially on big 5761 + memory systems because the BIOS will not go through 5762 + the memory check. Disadvantage is that not all 5763 + hardware will be completely reinitialized on reboot so 5764 + there may be boot problems on some systems. 5765 + 5766 + 5873 5767 refscale.holdoff= [KNL] 5874 5768 Set test-start holdoff period. The purpose of 5875 5769 this parameter is to delay the start of the ··· 6310 6106 6311 6107 serialnumber [BUGS=X86-32] 6312 6108 6313 - sev=option[,option...] [X86-64] See Documentation/arch/x86/x86_64/boot-options.rst 6109 + sev=option[,option...] [X86-64] 6110 + 6111 + debug 6112 + Enable debug messages. 6113 + 6114 + nosnp 6115 + Do not enable SEV-SNP (applies to host/hypervisor 6116 + only). Setting 'nosnp' avoids the RMP check overhead 6117 + in memory accesses when users do not want to run 6118 + SEV-SNP guests. 6314 6119 6315 6120 shapers= [NET] 6316 6121 Maximal number of shapers.
-312
Documentation/arch/x86/x86_64/boot-options.rst
··· 1 - .. SPDX-License-Identifier: GPL-2.0 2 - 3 - =========================== 4 - AMD64 Specific Boot Options 5 - =========================== 6 - 7 - There are many others (usually documented in driver documentation), but 8 - only the AMD64 specific ones are listed here. 9 - 10 - Machine check 11 - ============= 12 - Please see Documentation/arch/x86/x86_64/machinecheck.rst for sysfs runtime tunables. 13 - 14 - mce=off 15 - Disable machine check 16 - mce=no_cmci 17 - Disable CMCI(Corrected Machine Check Interrupt) that 18 - Intel processor supports. Usually this disablement is 19 - not recommended, but it might be handy if your hardware 20 - is misbehaving. 21 - Note that you'll get more problems without CMCI than with 22 - due to the shared banks, i.e. you might get duplicated 23 - error logs. 24 - mce=dont_log_ce 25 - Don't make logs for corrected errors. All events reported 26 - as corrected are silently cleared by OS. 27 - This option will be useful if you have no interest in any 28 - of corrected errors. 29 - mce=ignore_ce 30 - Disable features for corrected errors, e.g. polling timer 31 - and CMCI. All events reported as corrected are not cleared 32 - by OS and remained in its error banks. 33 - Usually this disablement is not recommended, however if 34 - there is an agent checking/clearing corrected errors 35 - (e.g. BIOS or hardware monitoring applications), conflicting 36 - with OS's error handling, and you cannot deactivate the agent, 37 - then this option will be a help. 38 - mce=no_lmce 39 - Do not opt-in to Local MCE delivery. Use legacy method 40 - to broadcast MCEs. 41 - mce=bootlog 42 - Enable logging of machine checks left over from booting. 43 - Disabled by default on AMD Fam10h and older because some BIOS 44 - leave bogus ones. 45 - If your BIOS doesn't do that it's a good idea to enable though 46 - to make sure you log even machine check events that result 47 - in a reboot. On Intel systems it is enabled by default. 48 - mce=nobootlog 49 - Disable boot machine check logging. 50 - mce=monarchtimeout (number) 51 - monarchtimeout: 52 - Sets the time in us to wait for other CPUs on machine checks. 0 53 - to disable. 54 - mce=bios_cmci_threshold 55 - Don't overwrite the bios-set CMCI threshold. This boot option 56 - prevents Linux from overwriting the CMCI threshold set by the 57 - bios. Without this option, Linux always sets the CMCI 58 - threshold to 1. Enabling this may make memory predictive failure 59 - analysis less effective if the bios sets thresholds for memory 60 - errors since we will not see details for all errors. 61 - mce=recovery 62 - Force-enable recoverable machine check code paths 63 - 64 - nomce (for compatibility with i386) 65 - same as mce=off 66 - 67 - Everything else is in sysfs now. 68 - 69 - APICs 70 - ===== 71 - 72 - apic 73 - Use IO-APIC. Default 74 - 75 - noapic 76 - Don't use the IO-APIC. 77 - 78 - disableapic 79 - Don't use the local APIC 80 - 81 - nolapic 82 - Don't use the local APIC (alias for i386 compatibility) 83 - 84 - pirq=... 85 - See Documentation/arch/x86/i386/IO-APIC.rst 86 - 87 - noapictimer 88 - Don't set up the APIC timer 89 - 90 - no_timer_check 91 - Don't check the IO-APIC timer. This can work around 92 - problems with incorrect timer initialization on some boards. 93 - 94 - apicpmtimer 95 - Do APIC timer calibration using the pmtimer. Implies 96 - apicmaintimer. Useful when your PIT timer is totally broken. 97 - 98 - Timing 99 - ====== 100 - 101 - notsc 102 - Deprecated, use tsc=unstable instead. 103 - 104 - nohpet 105 - Don't use the HPET timer. 106 - 107 - Idle loop 108 - ========= 109 - 110 - idle=poll 111 - Don't do power saving in the idle loop using HLT, but poll for rescheduling 112 - event. This will make the CPUs eat a lot more power, but may be useful 113 - to get slightly better performance in multiprocessor benchmarks. It also 114 - makes some profiling using performance counters more accurate. 115 - Please note that on systems with MONITOR/MWAIT support (like Intel EM64T 116 - CPUs) this option has no performance advantage over the normal idle loop. 117 - It may also interact badly with hyperthreading. 118 - 119 - Rebooting 120 - ========= 121 - 122 - reboot=b[ios] | t[riple] | k[bd] | a[cpi] | e[fi] | p[ci] [, [w]arm | [c]old] 123 - bios 124 - Use the CPU reboot vector for warm reset 125 - warm 126 - Don't set the cold reboot flag 127 - cold 128 - Set the cold reboot flag 129 - triple 130 - Force a triple fault (init) 131 - kbd 132 - Use the keyboard controller. cold reset (default) 133 - acpi 134 - Use the ACPI RESET_REG in the FADT. If ACPI is not configured or 135 - the ACPI reset does not work, the reboot path attempts the reset 136 - using the keyboard controller. 137 - efi 138 - Use efi reset_system runtime service. If EFI is not configured or 139 - the EFI reset does not work, the reboot path attempts the reset using 140 - the keyboard controller. 141 - pci 142 - Use a write to the PCI config space register 0xcf9 to trigger reboot. 143 - 144 - Using warm reset will be much faster especially on big memory 145 - systems because the BIOS will not go through the memory check. 146 - Disadvantage is that not all hardware will be completely reinitialized 147 - on reboot so there may be boot problems on some systems. 148 - 149 - reboot=force 150 - Don't stop other CPUs on reboot. This can make reboot more reliable 151 - in some cases. 152 - 153 - reboot=default 154 - There are some built-in platform specific "quirks" - you may see: 155 - "reboot: <name> series board detected. Selecting <type> for reboots." 156 - In the case where you think the quirk is in error (e.g. you have 157 - newer BIOS, or newer board) using this option will ignore the built-in 158 - quirk table, and use the generic default reboot actions. 159 - 160 - NUMA 161 - ==== 162 - 163 - numa=off 164 - Only set up a single NUMA node spanning all memory. 165 - 166 - numa=noacpi 167 - Don't parse the SRAT table for NUMA setup 168 - 169 - numa=nohmat 170 - Don't parse the HMAT table for NUMA setup, or soft-reserved memory 171 - partitioning. 172 - 173 - ACPI 174 - ==== 175 - 176 - acpi=off 177 - Don't enable ACPI 178 - acpi=ht 179 - Use ACPI boot table parsing, but don't enable ACPI interpreter 180 - acpi=force 181 - Force ACPI on (currently not needed) 182 - acpi=strict 183 - Disable out of spec ACPI workarounds. 184 - acpi_sci={edge,level,high,low} 185 - Set up ACPI SCI interrupt. 186 - acpi=noirq 187 - Don't route interrupts 188 - acpi=nocmcff 189 - Disable firmware first mode for corrected errors. This 190 - disables parsing the HEST CMC error source to check if 191 - firmware has set the FF flag. This may result in 192 - duplicate corrected error reports. 193 - 194 - PCI 195 - === 196 - 197 - pci=off 198 - Don't use PCI 199 - pci=conf1 200 - Use conf1 access. 201 - pci=conf2 202 - Use conf2 access. 203 - pci=rom 204 - Assign ROMs. 205 - pci=assign-busses 206 - Assign busses 207 - pci=irqmask=MASK 208 - Set PCI interrupt mask to MASK 209 - pci=lastbus=NUMBER 210 - Scan up to NUMBER busses, no matter what the mptable says. 211 - pci=noacpi 212 - Don't use ACPI to set up PCI interrupt routing. 213 - 214 - IOMMU (input/output memory management unit) 215 - =========================================== 216 - Multiple x86-64 PCI-DMA mapping implementations exist, for example: 217 - 218 - 1. <kernel/dma/direct.c>: use no hardware/software IOMMU at all 219 - (e.g. because you have < 3 GB memory). 220 - Kernel boot message: "PCI-DMA: Disabling IOMMU" 221 - 222 - 2. <arch/x86/kernel/amd_gart_64.c>: AMD GART based hardware IOMMU. 223 - Kernel boot message: "PCI-DMA: using GART IOMMU" 224 - 225 - 3. <arch/x86_64/kernel/pci-swiotlb.c> : Software IOMMU implementation. Used 226 - e.g. if there is no hardware IOMMU in the system and it is need because 227 - you have >3GB memory or told the kernel to us it (iommu=soft)) 228 - Kernel boot message: "PCI-DMA: Using software bounce buffering 229 - for IO (SWIOTLB)" 230 - 231 - :: 232 - 233 - iommu=[<size>][,noagp][,off][,force][,noforce] 234 - [,memaper[=<order>]][,merge][,fullflush][,nomerge] 235 - [,noaperture] 236 - 237 - General iommu options: 238 - 239 - off 240 - Don't initialize and use any kind of IOMMU. 241 - noforce 242 - Don't force hardware IOMMU usage when it is not needed. (default). 243 - force 244 - Force the use of the hardware IOMMU even when it is 245 - not actually needed (e.g. because < 3 GB memory). 246 - soft 247 - Use software bounce buffering (SWIOTLB) (default for 248 - Intel machines). This can be used to prevent the usage 249 - of an available hardware IOMMU. 250 - 251 - iommu options only relevant to the AMD GART hardware IOMMU: 252 - 253 - <size> 254 - Set the size of the remapping area in bytes. 255 - allowed 256 - Overwrite iommu off workarounds for specific chipsets. 257 - fullflush 258 - Flush IOMMU on each allocation (default). 259 - nofullflush 260 - Don't use IOMMU fullflush. 261 - memaper[=<order>] 262 - Allocate an own aperture over RAM with size 32MB<<order. 263 - (default: order=1, i.e. 64MB) 264 - merge 265 - Do scatter-gather (SG) merging. Implies "force" (experimental). 266 - nomerge 267 - Don't do scatter-gather (SG) merging. 268 - noaperture 269 - Ask the IOMMU not to touch the aperture for AGP. 270 - noagp 271 - Don't initialize the AGP driver and use full aperture. 272 - panic 273 - Always panic when IOMMU overflows. 274 - 275 - iommu options only relevant to the software bounce buffering (SWIOTLB) IOMMU 276 - implementation: 277 - 278 - swiotlb=<slots>[,force,noforce] 279 - <slots> 280 - Prereserve that many 2K slots for the software IO bounce buffering. 281 - force 282 - Force all IO through the software TLB. 283 - noforce 284 - Do not initialize the software TLB. 285 - 286 - 287 - Miscellaneous 288 - ============= 289 - 290 - nogbpages 291 - Do not use GB pages for kernel direct mappings. 292 - gbpages 293 - Use GB pages for kernel direct mappings. 294 - 295 - 296 - AMD SEV (Secure Encrypted Virtualization) 297 - ========================================= 298 - Options relating to AMD SEV, specified via the following format: 299 - 300 - :: 301 - 302 - sev=option1[,option2] 303 - 304 - The available options are: 305 - 306 - debug 307 - Enable debug messages. 308 - 309 - nosnp 310 - Do not enable SEV-SNP (applies to host/hypervisor only). Setting 311 - 'nosnp' avoids the RMP check overhead in memory accesses when 312 - users do not want to run SEV-SNP guests.
+1 -1
Documentation/arch/x86/x86_64/fake-numa-for-cpusets.rst
··· 18 18 Documentation/admin-guide/cgroup-v1/cpusets.rst. 19 19 There are a number of different configurations you can use for your needs. For 20 20 more information on the numa=fake command line option and its various ways of 21 - configuring fake nodes, see Documentation/arch/x86/x86_64/boot-options.rst. 21 + configuring fake nodes, see Documentation/admin-guide/kernel-parameters.txt 22 22 23 23 For the purposes of this introduction, we'll assume a very primitive NUMA 24 24 emulation setup of "numa=fake=4*512,". This will split our system memory into
-1
Documentation/arch/x86/x86_64/index.rst
··· 7 7 .. toctree:: 8 8 :maxdepth: 2 9 9 10 - boot-options 11 10 uefi 12 11 mm 13 12 5level-paging
+1 -1
arch/x86/Kconfig.debug
··· 97 97 code. When you use it make sure you have a big enough 98 98 IOMMU/AGP aperture. Most of the options enabled by this can 99 99 be set more finegrained using the iommu= command line 100 - options. See Documentation/arch/x86/x86_64/boot-options.rst for more 100 + options. See Documentation/admin-guide/kernel-parameters.txt for more 101 101 details. 102 102 103 103 config IOMMU_LEAK
-4
arch/x86/boot/compressed/kaslr.c
··· 25 25 #include "efi.h" 26 26 27 27 #include <generated/compile.h> 28 - #include <linux/module.h> 29 - #include <linux/uts.h> 30 - #include <linux/utsname.h> 31 - #include <linux/ctype.h> 32 28 #include <generated/utsversion.h> 33 29 #include <generated/utsrelease.h> 34 30
+6 -6
arch/x86/include/asm/cpufeatures.h
··· 443 443 #define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* Speculative Store Bypass Disable */ 444 444 445 445 /* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */ 446 - #define X86_FEATURE_SME (19*32+ 0) /* "sme" AMD Secure Memory Encryption */ 447 - #define X86_FEATURE_SEV (19*32+ 1) /* "sev" AMD Secure Encrypted Virtualization */ 446 + #define X86_FEATURE_SME (19*32+ 0) /* "sme" Secure Memory Encryption */ 447 + #define X86_FEATURE_SEV (19*32+ 1) /* "sev" Secure Encrypted Virtualization */ 448 448 #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* VM Page Flush MSR is supported */ 449 - #define X86_FEATURE_SEV_ES (19*32+ 3) /* "sev_es" AMD Secure Encrypted Virtualization - Encrypted State */ 450 - #define X86_FEATURE_SEV_SNP (19*32+ 4) /* "sev_snp" AMD Secure Encrypted Virtualization - Secure Nested Paging */ 449 + #define X86_FEATURE_SEV_ES (19*32+ 3) /* "sev_es" Secure Encrypted Virtualization - Encrypted State */ 450 + #define X86_FEATURE_SEV_SNP (19*32+ 4) /* "sev_snp" Secure Encrypted Virtualization - Secure Nested Paging */ 451 451 #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* Virtual TSC_AUX */ 452 - #define X86_FEATURE_SME_COHERENT (19*32+10) /* AMD hardware-enforced cache coherency */ 453 - #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" AMD SEV-ES full debug state swap support */ 452 + #define X86_FEATURE_SME_COHERENT (19*32+10) /* hardware-enforced cache coherency */ 453 + #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" SEV-ES full debug state swap support */ 454 454 #define X86_FEATURE_RMPREAD (19*32+21) /* RMPREAD instruction */ 455 455 #define X86_FEATURE_SEGMENTED_RMP (19*32+23) /* Segmented RMP support */ 456 456 #define X86_FEATURE_SVSM (19*32+28) /* "svsm" SVSM present */
+1 -8
arch/x86/kernel/apic/apic.c
··· 2582 2582 /* 2583 2583 * APIC command line parameters 2584 2584 */ 2585 - static int __init setup_disableapic(char *arg) 2585 + static int __init setup_nolapic(char *arg) 2586 2586 { 2587 2587 apic_is_disabled = true; 2588 2588 setup_clear_cpu_cap(X86_FEATURE_APIC); 2589 2589 return 0; 2590 - } 2591 - early_param("disableapic", setup_disableapic); 2592 - 2593 - /* same as disableapic, for compatibility */ 2594 - static int __init setup_nolapic(char *arg) 2595 - { 2596 - return setup_disableapic(arg); 2597 2590 } 2598 2591 early_param("nolapic", setup_nolapic); 2599 2592
+1 -1
arch/x86/kernel/apic/io_apic.c
··· 1165 1165 (entry.ir_index_15 << 15) | entry.ir_index_0_14, entry.ir_zero); 1166 1166 } else { 1167 1167 apic_dbg("%s, %s, D(%02X%02X), M(%1d)\n", buf, 1168 - entry.dest_mode_logical ? "logical " : "physic al", 1168 + entry.dest_mode_logical ? "logical " : "physical", 1169 1169 entry.virt_destid_8_14, entry.destid_0_7, entry.delivery_mode); 1170 1170 } 1171 1171 }
+1 -1
arch/x86/kernel/cpu/match.c
··· 6 6 #include <linux/slab.h> 7 7 8 8 /** 9 - * x86_match_cpu - match current CPU again an array of x86_cpu_ids 9 + * x86_match_cpu - match current CPU against an array of x86_cpu_ids 10 10 * @match: Pointer to array of x86_cpu_ids. Last entry terminated with 11 11 * {}. 12 12 *
+1 -1
arch/x86/kernel/cpu/topology.c
··· 428 428 { 429 429 unsigned int possible = nr_cpu_ids; 430 430 431 - /* 'maxcpus=0' 'nosmp' 'nolapic' 'disableapic' */ 431 + /* 'maxcpus=0' 'nosmp' 'nolapic' */ 432 432 if (!setup_max_cpus || apic_is_disabled) 433 433 possible = 1; 434 434
-4
arch/x86/kernel/pci-dma.c
··· 108 108 swiotlb_init(x86_swiotlb_enable, x86_swiotlb_flags); 109 109 } 110 110 111 - /* 112 - * See <Documentation/arch/x86/x86_64/boot-options.rst> for the iommu kernel 113 - * parameter documentation. 114 - */ 115 111 static __init int iommu_setup(char *p) 116 112 { 117 113 iommu_merge = 1;
+40 -79
arch/x86/mm/ioremap.c
··· 593 593 * Examine the physical address to determine if it is EFI data. Check 594 594 * it against the boot params structure and EFI tables and memory types. 595 595 */ 596 - static bool memremap_is_efi_data(resource_size_t phys_addr, 597 - unsigned long size) 596 + static bool memremap_is_efi_data(resource_size_t phys_addr) 598 597 { 599 598 u64 paddr; 600 599 ··· 631 632 * Examine the physical address to determine if it is boot data by checking 632 633 * it against the boot params setup_data chain. 633 634 */ 634 - static bool memremap_is_setup_data(resource_size_t phys_addr, 635 - unsigned long size) 635 + static bool __ref __memremap_is_setup_data(resource_size_t phys_addr, bool early) 636 636 { 637 - struct setup_indirect *indirect; 638 - struct setup_data *data; 639 - u64 paddr, paddr_next; 640 - 641 - paddr = boot_params.hdr.setup_data; 642 - while (paddr) { 643 - unsigned int len; 644 - 645 - if (phys_addr == paddr) 646 - return true; 647 - 648 - data = memremap(paddr, sizeof(*data), 649 - MEMREMAP_WB | MEMREMAP_DEC); 650 - if (!data) { 651 - pr_warn("failed to memremap setup_data entry\n"); 652 - return false; 653 - } 654 - 655 - paddr_next = data->next; 656 - len = data->len; 657 - 658 - if ((phys_addr > paddr) && 659 - (phys_addr < (paddr + sizeof(struct setup_data) + len))) { 660 - memunmap(data); 661 - return true; 662 - } 663 - 664 - if (data->type == SETUP_INDIRECT) { 665 - memunmap(data); 666 - data = memremap(paddr, sizeof(*data) + len, 667 - MEMREMAP_WB | MEMREMAP_DEC); 668 - if (!data) { 669 - pr_warn("failed to memremap indirect setup_data\n"); 670 - return false; 671 - } 672 - 673 - indirect = (struct setup_indirect *)data->data; 674 - 675 - if (indirect->type != SETUP_INDIRECT) { 676 - paddr = indirect->addr; 677 - len = indirect->len; 678 - } 679 - } 680 - 681 - memunmap(data); 682 - 683 - if ((phys_addr > paddr) && (phys_addr < (paddr + len))) 684 - return true; 685 - 686 - paddr = paddr_next; 687 - } 688 - 689 - return false; 690 - } 691 - 692 - /* 693 - * Examine the physical address to determine if it is boot data by checking 694 - * it against the boot params setup_data chain (early boot version). 695 - */ 696 - static bool __init early_memremap_is_setup_data(resource_size_t phys_addr, 697 - unsigned long size) 698 - { 637 + unsigned int setup_data_sz = sizeof(struct setup_data); 699 638 struct setup_indirect *indirect; 700 639 struct setup_data *data; 701 640 u64 paddr, paddr_next; ··· 645 708 if (phys_addr == paddr) 646 709 return true; 647 710 648 - data = early_memremap_decrypted(paddr, sizeof(*data)); 711 + if (early) 712 + data = early_memremap_decrypted(paddr, setup_data_sz); 713 + else 714 + data = memremap(paddr, setup_data_sz, MEMREMAP_WB | MEMREMAP_DEC); 649 715 if (!data) { 650 - pr_warn("failed to early memremap setup_data entry\n"); 716 + pr_warn("failed to remap setup_data entry\n"); 651 717 return false; 652 718 } 653 719 654 - size = sizeof(*data); 720 + size = setup_data_sz; 655 721 656 722 paddr_next = data->next; 657 723 len = data->len; 658 724 659 725 if ((phys_addr > paddr) && 660 - (phys_addr < (paddr + sizeof(struct setup_data) + len))) { 661 - early_memunmap(data, sizeof(*data)); 726 + (phys_addr < (paddr + setup_data_sz + len))) { 727 + if (early) 728 + early_memunmap(data, setup_data_sz); 729 + else 730 + memunmap(data); 662 731 return true; 663 732 } 664 733 665 734 if (data->type == SETUP_INDIRECT) { 666 735 size += len; 667 - early_memunmap(data, sizeof(*data)); 668 - data = early_memremap_decrypted(paddr, size); 736 + if (early) { 737 + early_memunmap(data, setup_data_sz); 738 + data = early_memremap_decrypted(paddr, size); 739 + } else { 740 + memunmap(data); 741 + data = memremap(paddr, size, MEMREMAP_WB | MEMREMAP_DEC); 742 + } 669 743 if (!data) { 670 - pr_warn("failed to early memremap indirect setup_data\n"); 744 + pr_warn("failed to remap indirect setup_data\n"); 671 745 return false; 672 746 } 673 747 ··· 690 742 } 691 743 } 692 744 693 - early_memunmap(data, size); 745 + if (early) 746 + early_memunmap(data, size); 747 + else 748 + memunmap(data); 694 749 695 750 if ((phys_addr > paddr) && (phys_addr < (paddr + len))) 696 751 return true; ··· 702 751 } 703 752 704 753 return false; 754 + } 755 + 756 + static bool memremap_is_setup_data(resource_size_t phys_addr) 757 + { 758 + return __memremap_is_setup_data(phys_addr, false); 759 + } 760 + 761 + static bool __init early_memremap_is_setup_data(resource_size_t phys_addr) 762 + { 763 + return __memremap_is_setup_data(phys_addr, true); 705 764 } 706 765 707 766 /* ··· 732 771 return false; 733 772 734 773 if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) { 735 - if (memremap_is_setup_data(phys_addr, size) || 736 - memremap_is_efi_data(phys_addr, size)) 774 + if (memremap_is_setup_data(phys_addr) || 775 + memremap_is_efi_data(phys_addr)) 737 776 return false; 738 777 } 739 778 ··· 758 797 encrypted_prot = true; 759 798 760 799 if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) { 761 - if (early_memremap_is_setup_data(phys_addr, size) || 762 - memremap_is_efi_data(phys_addr, size)) 800 + if (early_memremap_is_setup_data(phys_addr) || 801 + memremap_is_efi_data(phys_addr)) 763 802 encrypted_prot = false; 764 803 } 765 804