tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'arm-fixes-6.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
"Most of the changes this time are for the Qualcomm Snapdragon
platforms.

There are bug fixes for error handling in Qualcomm icc-bwmon,
rpmh-rsc, ramp_controller and rmtfs driver as well as the AMD tee
firmware driver and a missing initialization in the Arm ff-a firmware
driver. The Qualcomm RPMh and EDAC drivers need some rework to work
correctly on all supported chips.

The DT fixes include:

- i.MX8 fixes for gpio, pinmux and clock settings

- ADS touchscreen gpio polarity settings in several machines

- Address dtb warnings for caches, panel and input-enable properties
on Qualcomm platforms

- Incorrect data on qualcomm platforms fir SA8155P power domains,
SM8550 LLCC, SC7180-lite SDRAM frequencies and SM8550 soundwire

- Remoteproc firmware paths are corrected for Sony Xperia 10 IV"

* tag 'arm-fixes-6.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (36 commits)
firmware: arm_ffa: Set handle field to zero in memory descriptor
ARM: dts: Fix erroneous ADS touchscreen polarities
arm64: dts: imx8mn-beacon: Fix SPI CS pinmux
arm64: dts: imx8-ss-dma: assign default clock rate for lpuarts
arm64: dts: imx8qm-mek: correct GPIOs for USDHC2 CD and WP signals
EDAC/qcom: Get rid of hardcoded register offsets
EDAC/qcom: Remove superfluous return variable assignment in qcom_llcc_core_setup()
arm64: dts: qcom: sm8550: Use the correct LLCC register scheme
dt-bindings: cache: qcom,llcc: Fix SM8550 description
arm64: dts: qcom: sc7180-lite: Fix SDRAM freq for misidentified sc7180-lite boards
arm64: dts: qcom: sm8550: use uint16 for Soundwire interval
soc: qcom: rpmhpd: Add SA8155P power domains
arm64: dts: qcom: Split out SA8155P and use correct RPMh power domains
dt-bindings: power: qcom,rpmpd: Add SA8155P
soc: qcom: Rename ice to qcom_ice to avoid module name conflict
soc: qcom: rmtfs: Fix error code in probe()
soc: qcom: ramp_controller: Fix an error handling path in qcom_ramp_controller_probe()
ARM: dts: at91: sama7g5ek: fix debounce delay property for shdwc
ARM: at91: pm: fix imbalanced reference counter for ethernet devices
arm64: dts: qcom: sm6375-pdx225: Fix remoteproc firmware paths
...

Linus Torvalds 859c7459 64569520

+478 -225
+1
Documentation/devicetree/bindings/cache/qcom,llcc.yaml
··· 129 129 - qcom,sm8250-llcc 130 130 - qcom,sm8350-llcc 131 131 - qcom,sm8450-llcc 132 + - qcom,sm8550-llcc 132 133 then: 133 134 properties: 134 135 reg:
+1
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
··· 29 29 - qcom,qcm2290-rpmpd 30 30 - qcom,qcs404-rpmpd 31 31 - qcom,qdu1000-rpmhpd 32 + - qcom,sa8155p-rpmhpd 32 33 - qcom,sa8540p-rpmhpd 33 34 - qcom,sa8775p-rpmhpd 34 35 - qcom,sdm660-rpmpd
+1 -1
arch/arm/boot/dts/am57xx-cl-som-am57x.dts
··· 527 527 528 528 interrupt-parent = <&gpio1>; 529 529 interrupts = <31 0>; 530 - pendown-gpio = <&gpio1 31 0>; 530 + pendown-gpio = <&gpio1 31 GPIO_ACTIVE_LOW>; 531 531 532 532 533 533 ti,x-min = /bits/ 16 <0x0>;
+1 -1
arch/arm/boot/dts/at91-sama7g5ek.dts
··· 792 792 }; 793 793 794 794 &shdwc { 795 - atmel,shdwc-debouncer = <976>; 795 + debounce-delay-us = <976>; 796 796 status = "okay"; 797 797 798 798 input@0 {
+1 -1
arch/arm/boot/dts/at91sam9261ek.dts
··· 156 156 compatible = "ti,ads7843"; 157 157 interrupts-extended = <&pioC 2 IRQ_TYPE_EDGE_BOTH>; 158 158 spi-max-frequency = <3000000>; 159 - pendown-gpio = <&pioC 2 GPIO_ACTIVE_HIGH>; 159 + pendown-gpio = <&pioC 2 GPIO_ACTIVE_LOW>; 160 160 161 161 ti,x-min = /bits/ 16 <150>; 162 162 ti,x-max = /bits/ 16 <3830>;
+1 -1
arch/arm/boot/dts/imx7d-pico-hobbit.dts
··· 64 64 interrupt-parent = <&gpio2>; 65 65 interrupts = <7 0>; 66 66 spi-max-frequency = <1000000>; 67 - pendown-gpio = <&gpio2 7 0>; 67 + pendown-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; 68 68 vcc-supply = <&reg_3p3v>; 69 69 ti,x-min = /bits/ 16 <0>; 70 70 ti,x-max = /bits/ 16 <4095>;
+1 -1
arch/arm/boot/dts/imx7d-sdb.dts
··· 205 205 pinctrl-0 = <&pinctrl_tsc2046_pendown>; 206 206 interrupt-parent = <&gpio2>; 207 207 interrupts = <29 0>; 208 - pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; 208 + pendown-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; 209 209 touchscreen-max-pressure = <255>; 210 210 wakeup-source; 211 211 };
+1 -1
arch/arm/boot/dts/omap3-cm-t3x.dtsi
··· 227 227 228 228 interrupt-parent = <&gpio2>; 229 229 interrupts = <25 0>; /* gpio_57 */ 230 - pendown-gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; 230 + pendown-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>; 231 231 232 232 ti,x-min = /bits/ 16 <0x0>; 233 233 ti,x-max = /bits/ 16 <0x0fff>;
+1 -1
arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi
··· 54 54 55 55 interrupt-parent = <&gpio1>; 56 56 interrupts = <27 0>; /* gpio_27 */ 57 - pendown-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; 57 + pendown-gpio = <&gpio1 27 GPIO_ACTIVE_LOW>; 58 58 59 59 ti,x-min = /bits/ 16 <0x0>; 60 60 ti,x-max = /bits/ 16 <0x0fff>;
+1 -1
arch/arm/boot/dts/omap3-lilly-a83x.dtsi
··· 311 311 interrupt-parent = <&gpio1>; 312 312 interrupts = <8 0>; /* boot6 / gpio_8 */ 313 313 spi-max-frequency = <1000000>; 314 - pendown-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; 314 + pendown-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; 315 315 vcc-supply = <&reg_vcc3>; 316 316 pinctrl-names = "default"; 317 317 pinctrl-0 = <&tsc2048_pins>;
+1 -1
arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi
··· 149 149 150 150 interrupt-parent = <&gpio4>; 151 151 interrupts = <18 0>; /* gpio_114 */ 152 - pendown-gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>; 152 + pendown-gpio = <&gpio4 18 GPIO_ACTIVE_LOW>; 153 153 154 154 ti,x-min = /bits/ 16 <0x0>; 155 155 ti,x-max = /bits/ 16 <0x0fff>;
+1 -1
arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi
··· 160 160 161 161 interrupt-parent = <&gpio4>; 162 162 interrupts = <18 0>; /* gpio_114 */ 163 - pendown-gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>; 163 + pendown-gpio = <&gpio4 18 GPIO_ACTIVE_LOW>; 164 164 165 165 ti,x-min = /bits/ 16 <0x0>; 166 166 ti,x-max = /bits/ 16 <0x0fff>;
+1 -1
arch/arm/boot/dts/omap3-pandora-common.dtsi
··· 651 651 pinctrl-0 = <&penirq_pins>; 652 652 interrupt-parent = <&gpio3>; 653 653 interrupts = <30 IRQ_TYPE_NONE>; /* GPIO_94 */ 654 - pendown-gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; 654 + pendown-gpio = <&gpio3 30 GPIO_ACTIVE_LOW>; 655 655 vcc-supply = <&vaux4>; 656 656 657 657 ti,x-min = /bits/ 16 <0>;
+1 -1
arch/arm/boot/dts/omap5-cm-t54.dts
··· 354 354 355 355 interrupt-parent = <&gpio1>; 356 356 interrupts = <15 0>; /* gpio1_wk15 */ 357 - pendown-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; 357 + pendown-gpio = <&gpio1 15 GPIO_ACTIVE_LOW>; 358 358 359 359 360 360 ti,x-min = /bits/ 16 <0x0>;
-2
arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts
··· 268 268 function = "gpio"; 269 269 drive-strength = <8>; 270 270 bias-disable; 271 - input-enable; 272 271 }; 273 272 274 273 wlan_hostwake_default_state: wlan-hostwake-default-state { ··· 275 276 function = "gpio"; 276 277 drive-strength = <2>; 277 278 bias-disable; 278 - input-enable; 279 279 }; 280 280 281 281 wlan_regulator_default_state: wlan-regulator-default-state {
-1
arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts
··· 352 352 function = "gpio"; 353 353 drive-strength = <2>; 354 354 bias-disable; 355 - input-enable; 356 355 }; 357 356 358 357 wlan_regulator_default_state: wlan-regulator-default-state {
-3
arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts
··· 307 307 function = "gpio"; 308 308 drive-strength = <2>; 309 309 bias-disable; 310 - input-enable; 311 310 }; 312 311 313 312 touch_pins: touch-state { ··· 316 317 317 318 drive-strength = <8>; 318 319 bias-pull-down; 319 - input-enable; 320 320 }; 321 321 322 322 reset-pins { ··· 333 335 function = "gpio"; 334 336 drive-strength = <2>; 335 337 bias-disable; 336 - input-enable; 337 338 }; 338 339 339 340 wlan_regulator_default_state: wlan-regulator-default-state {
+1
arch/arm/boot/dts/qcom-apq8064.dtsi
··· 83 83 L2: l2-cache { 84 84 compatible = "cache"; 85 85 cache-level = <2>; 86 + cache-unified; 86 87 }; 87 88 88 89 idle-states {
+1
arch/arm/boot/dts/qcom-apq8084.dtsi
··· 74 74 L2: l2-cache { 75 75 compatible = "cache"; 76 76 cache-level = <2>; 77 + cache-unified; 77 78 qcom,saw = <&saw_l2>; 78 79 }; 79 80
+1
arch/arm/boot/dts/qcom-ipq4019.dtsi
··· 102 102 L2: l2-cache { 103 103 compatible = "cache"; 104 104 cache-level = <2>; 105 + cache-unified; 105 106 qcom,saw = <&saw_l2>; 106 107 }; 107 108 };
+1
arch/arm/boot/dts/qcom-ipq8064.dtsi
··· 45 45 L2: l2-cache { 46 46 compatible = "cache"; 47 47 cache-level = <2>; 48 + cache-unified; 48 49 }; 49 50 }; 50 51
-1
arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts
··· 49 49 gpioext1-pins { 50 50 pins = "gpio2"; 51 51 function = "gpio"; 52 - input-enable; 53 52 bias-disable; 54 53 }; 55 54 };
+1
arch/arm/boot/dts/qcom-msm8660.dtsi
··· 36 36 L2: l2-cache { 37 37 compatible = "cache"; 38 38 cache-level = <2>; 39 + cache-unified; 39 40 }; 40 41 }; 41 42
+1
arch/arm/boot/dts/qcom-msm8960.dtsi
··· 42 42 L2: l2-cache { 43 43 compatible = "cache"; 44 44 cache-level = <2>; 45 + cache-unified; 45 46 }; 46 47 }; 47 48
-2
arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
··· 592 592 pins = "gpio73"; 593 593 function = "gpio"; 594 594 bias-disable; 595 - input-enable; 596 595 }; 597 596 598 597 touch_pin: touch-state { ··· 601 602 602 603 drive-strength = <2>; 603 604 bias-disable; 604 - input-enable; 605 605 }; 606 606 607 607 reset-pins {
-1
arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi
··· 433 433 function = "gpio"; 434 434 drive-strength = <2>; 435 435 bias-disable; 436 - input-enable; 437 436 }; 438 437 439 438 sdc1_on: sdc1-on-state {
+1
arch/arm/boot/dts/qcom-msm8974.dtsi
··· 80 80 L2: l2-cache { 81 81 compatible = "cache"; 82 82 cache-level = <2>; 83 + cache-unified; 83 84 qcom,saw = <&saw_l2>; 84 85 }; 85 86
-1
arch/arm/boot/dts/qcom-msm8974pro-oneplus-bacon.dts
··· 461 461 function = "gpio"; 462 462 drive-strength = <2>; 463 463 bias-disable; 464 - input-enable; 465 464 }; 466 465 467 466 reset-pins {
-4
arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts
··· 704 704 pins = "gpio75"; 705 705 function = "gpio"; 706 706 drive-strength = <16>; 707 - input-enable; 708 707 }; 709 708 710 709 devwake-pins { ··· 759 760 i2c_touchkey_pins: i2c-touchkey-state { 760 761 pins = "gpio95", "gpio96"; 761 762 function = "gpio"; 762 - input-enable; 763 763 bias-pull-up; 764 764 }; 765 765 766 766 i2c_led_gpioex_pins: i2c-led-gpioex-state { 767 767 pins = "gpio120", "gpio121"; 768 768 function = "gpio"; 769 - input-enable; 770 769 bias-pull-down; 771 770 }; 772 771 ··· 778 781 wifi_pin: wifi-state { 779 782 pins = "gpio92"; 780 783 function = "gpio"; 781 - input-enable; 782 784 bias-pull-down; 783 785 }; 784 786
-1
arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts
··· 631 631 function = "gpio"; 632 632 drive-strength = <2>; 633 633 bias-disable; 634 - input-enable; 635 634 }; 636 635 637 636 bt_host_wake_pin: bt-host-wake-state {
+9 -11
arch/arm/mach-at91/pm.c
··· 334 334 pdev = of_find_device_by_node(eth->np); 335 335 if (!pdev) 336 336 return false; 337 + /* put_device(eth->dev) is called at the end of suspend. */ 337 338 eth->dev = &pdev->dev; 338 339 } 339 340 340 341 /* No quirks if device isn't a wakeup source. */ 341 - if (!device_may_wakeup(eth->dev)) { 342 - put_device(eth->dev); 342 + if (!device_may_wakeup(eth->dev)) 343 343 return false; 344 - } 345 344 346 - /* put_device(eth->dev) is called at the end of suspend. */ 347 345 return true; 348 346 } 349 347 ··· 437 439 pr_err("AT91: PM: failed to enable %s clocks\n", 438 440 j == AT91_PM_G_ETH ? "geth" : "eth"); 439 441 } 440 - } else { 441 - /* 442 - * Release the reference to eth->dev taken in 443 - * at91_pm_eth_quirk_is_valid(). 444 - */ 445 - put_device(eth->dev); 446 - eth->dev = NULL; 447 442 } 443 + 444 + /* 445 + * Release the reference to eth->dev taken in 446 + * at91_pm_eth_quirk_is_valid(). 447 + */ 448 + put_device(eth->dev); 449 + eth->dev = NULL; 448 450 } 449 451 450 452 return ret;
+8
arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
··· 90 90 clocks = <&uart0_lpcg IMX_LPCG_CLK_4>, 91 91 <&uart0_lpcg IMX_LPCG_CLK_0>; 92 92 clock-names = "ipg", "baud"; 93 + assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; 94 + assigned-clock-rates = <80000000>; 93 95 power-domains = <&pd IMX_SC_R_UART_0>; 94 96 status = "disabled"; 95 97 }; ··· 102 100 clocks = <&uart1_lpcg IMX_LPCG_CLK_4>, 103 101 <&uart1_lpcg IMX_LPCG_CLK_0>; 104 102 clock-names = "ipg", "baud"; 103 + assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>; 104 + assigned-clock-rates = <80000000>; 105 105 power-domains = <&pd IMX_SC_R_UART_1>; 106 106 status = "disabled"; 107 107 }; ··· 114 110 clocks = <&uart2_lpcg IMX_LPCG_CLK_4>, 115 111 <&uart2_lpcg IMX_LPCG_CLK_0>; 116 112 clock-names = "ipg", "baud"; 113 + assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>; 114 + assigned-clock-rates = <80000000>; 117 115 power-domains = <&pd IMX_SC_R_UART_2>; 118 116 status = "disabled"; 119 117 }; ··· 126 120 clocks = <&uart3_lpcg IMX_LPCG_CLK_4>, 127 121 <&uart3_lpcg IMX_LPCG_CLK_0>; 128 122 clock-names = "ipg", "baud"; 123 + assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>; 124 + assigned-clock-rates = <80000000>; 129 125 power-domains = <&pd IMX_SC_R_UART_3>; 130 126 status = "disabled"; 131 127 };
+2 -2
arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi
··· 81 81 &ecspi2 { 82 82 pinctrl-names = "default"; 83 83 pinctrl-0 = <&pinctrl_espi2>; 84 - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 84 + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 85 85 status = "okay"; 86 86 87 87 eeprom@0 { ··· 202 202 MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 203 203 MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 204 204 MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 205 - MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41 205 + MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x41 206 206 >; 207 207 }; 208 208
+2 -2
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
··· 82 82 pinctrl-0 = <&pinctrl_usdhc2>; 83 83 bus-width = <4>; 84 84 vmmc-supply = <&reg_usdhc2_vmmc>; 85 - cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; 86 - wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; 85 + cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; 86 + wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; 87 87 status = "okay"; 88 88 }; 89 89
+1
arch/arm64/boot/dts/qcom/ipq5332.dtsi
··· 73 73 L2_0: l2-cache { 74 74 compatible = "cache"; 75 75 cache-level = <2>; 76 + cache-unified; 76 77 }; 77 78 }; 78 79
+2 -1
arch/arm64/boot/dts/qcom/ipq6018.dtsi
··· 83 83 84 84 L2_0: l2-cache { 85 85 compatible = "cache"; 86 - cache-level = <0x2>; 86 + cache-level = <2>; 87 + cache-unified; 87 88 }; 88 89 }; 89 90
+2 -1
arch/arm64/boot/dts/qcom/ipq8074.dtsi
··· 66 66 67 67 L2_0: l2-cache { 68 68 compatible = "cache"; 69 - cache-level = <0x2>; 69 + cache-level = <2>; 70 + cache-unified; 70 71 }; 71 72 }; 72 73
+1
arch/arm64/boot/dts/qcom/ipq9574.dtsi
··· 72 72 L2_0: l2-cache { 73 73 compatible = "cache"; 74 74 cache-level = <2>; 75 + cache-unified; 75 76 }; 76 77 }; 77 78
+1
arch/arm64/boot/dts/qcom/msm8916.dtsi
··· 180 180 L2_0: l2-cache { 181 181 compatible = "cache"; 182 182 cache-level = <2>; 183 + cache-unified; 183 184 }; 184 185 185 186 idle-states {
+2
arch/arm64/boot/dts/qcom/msm8953.dtsi
··· 153 153 L2_0: l2-cache-0 { 154 154 compatible = "cache"; 155 155 cache-level = <2>; 156 + cache-unified; 156 157 }; 157 158 158 159 L2_1: l2-cache-1 { 159 160 compatible = "cache"; 160 161 cache-level = <2>; 162 + cache-unified; 161 163 }; 162 164 }; 163 165
+2
arch/arm64/boot/dts/qcom/msm8976.dtsi
··· 193 193 l2_0: l2-cache0 { 194 194 compatible = "cache"; 195 195 cache-level = <2>; 196 + cache-unified; 196 197 }; 197 198 198 199 l2_1: l2-cache1 { 199 200 compatible = "cache"; 200 201 cache-level = <2>; 202 + cache-unified; 201 203 }; 202 204 }; 203 205
+2
arch/arm64/boot/dts/qcom/msm8994.dtsi
··· 52 52 L2_0: l2-cache { 53 53 compatible = "cache"; 54 54 cache-level = <2>; 55 + cache-unified; 55 56 }; 56 57 }; 57 58 ··· 89 88 L2_1: l2-cache { 90 89 compatible = "cache"; 91 90 cache-level = <2>; 91 + cache-unified; 92 92 }; 93 93 }; 94 94
+6 -4
arch/arm64/boot/dts/qcom/msm8996.dtsi
··· 53 53 #cooling-cells = <2>; 54 54 next-level-cache = <&L2_0>; 55 55 L2_0: l2-cache { 56 - compatible = "cache"; 57 - cache-level = <2>; 56 + compatible = "cache"; 57 + cache-level = <2>; 58 + cache-unified; 58 59 }; 59 60 }; 60 61 ··· 84 83 #cooling-cells = <2>; 85 84 next-level-cache = <&L2_1>; 86 85 L2_1: l2-cache { 87 - compatible = "cache"; 88 - cache-level = <2>; 86 + compatible = "cache"; 87 + cache-level = <2>; 88 + cache-unified; 89 89 }; 90 90 }; 91 91
+2
arch/arm64/boot/dts/qcom/msm8998.dtsi
··· 146 146 L2_0: l2-cache { 147 147 compatible = "cache"; 148 148 cache-level = <2>; 149 + cache-unified; 149 150 }; 150 151 }; 151 152 ··· 191 190 L2_1: l2-cache { 192 191 compatible = "cache"; 193 192 cache-level = <2>; 193 + cache-unified; 194 194 }; 195 195 }; 196 196
+1
arch/arm64/boot/dts/qcom/qcm2290.dtsi
··· 51 51 L2_0: l2-cache { 52 52 compatible = "cache"; 53 53 cache-level = <2>; 54 + cache-unified; 54 55 }; 55 56 }; 56 57
+1
arch/arm64/boot/dts/qcom/qcs404.dtsi
··· 95 95 L2_0: l2-cache { 96 96 compatible = "cache"; 97 97 cache-level = <2>; 98 + cache-unified; 98 99 }; 99 100 100 101 idle-states {
+10
arch/arm64/boot/dts/qcom/qdu1000.dtsi
··· 35 35 next-level-cache = <&L2_0>; 36 36 L2_0: l2-cache { 37 37 compatible = "cache"; 38 + cache-level = <2>; 39 + cache-unified; 38 40 next-level-cache = <&L3_0>; 39 41 L3_0: l3-cache { 40 42 compatible = "cache"; 43 + cache-level = <3>; 44 + cache-unified; 41 45 }; 42 46 }; 43 47 }; ··· 58 54 next-level-cache = <&L2_100>; 59 55 L2_100: l2-cache { 60 56 compatible = "cache"; 57 + cache-level = <2>; 58 + cache-unified; 61 59 next-level-cache = <&L3_0>; 62 60 }; 63 61 }; ··· 76 70 next-level-cache = <&L2_200>; 77 71 L2_200: l2-cache { 78 72 compatible = "cache"; 73 + cache-level = <2>; 74 + cache-unified; 79 75 next-level-cache = <&L3_0>; 80 76 }; 81 77 }; ··· 94 86 next-level-cache = <&L2_300>; 95 87 L2_300: l2-cache { 96 88 compatible = "cache"; 89 + cache-level = <2>; 90 + cache-unified; 97 91 next-level-cache = <&L3_0>; 98 92 }; 99 93 };
+1 -1
arch/arm64/boot/dts/qcom/sa8155p-adp.dts
··· 7 7 8 8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 9 9 #include <dt-bindings/gpio/gpio.h> 10 - #include "sm8150.dtsi" 10 + #include "sa8155p.dtsi" 11 11 #include "pmm8155au_1.dtsi" 12 12 #include "pmm8155au_2.dtsi" 13 13
+40
arch/arm64/boot/dts/qcom/sa8155p.dtsi
··· 1 + // SPDX-License-Identifier: BSD-3-Clause 2 + /* 3 + * Copyright (c) 2023, Linaro Limited 4 + * 5 + * SA8155P is an automotive variant of SM8150, with some minor changes. 6 + * Most notably, the RPMhPD setup differs: MMCX and LCX/LMX rails are gone, 7 + * though the cmd-db doesn't reflect that and access attemps result in a bite. 8 + */ 9 + 10 + #include "sm8150.dtsi" 11 + 12 + &dispcc { 13 + power-domains = <&rpmhpd SA8155P_CX>; 14 + }; 15 + 16 + &mdss_dsi0 { 17 + power-domains = <&rpmhpd SA8155P_CX>; 18 + }; 19 + 20 + &mdss_dsi1 { 21 + power-domains = <&rpmhpd SA8155P_CX>; 22 + }; 23 + 24 + &mdss_mdp { 25 + power-domains = <&rpmhpd SA8155P_CX>; 26 + }; 27 + 28 + &remoteproc_slpi { 29 + power-domains = <&rpmhpd SA8155P_CX>, 30 + <&rpmhpd SA8155P_MX>; 31 + }; 32 + 33 + &rpmhpd { 34 + /* 35 + * The bindings were crafted such that SA8155P PDs match their 36 + * SM8150 counterparts to make it more maintainable and only 37 + * necessitate adjusting entries that actually differ 38 + */ 39 + compatible = "qcom,sa8155p-rpmhpd"; 40 + };
+20
arch/arm64/boot/dts/qcom/sa8775p.dtsi
··· 42 42 next-level-cache = <&L2_0>; 43 43 L2_0: l2-cache { 44 44 compatible = "cache"; 45 + cache-level = <2>; 46 + cache-unified; 45 47 next-level-cache = <&L3_0>; 46 48 L3_0: l3-cache { 47 49 compatible = "cache"; 50 + cache-level = <3>; 51 + cache-unified; 48 52 }; 49 53 }; 50 54 }; ··· 62 58 next-level-cache = <&L2_1>; 63 59 L2_1: l2-cache { 64 60 compatible = "cache"; 61 + cache-level = <2>; 62 + cache-unified; 65 63 next-level-cache = <&L3_0>; 66 64 }; 67 65 }; ··· 77 71 next-level-cache = <&L2_2>; 78 72 L2_2: l2-cache { 79 73 compatible = "cache"; 74 + cache-level = <2>; 75 + cache-unified; 80 76 next-level-cache = <&L3_0>; 81 77 }; 82 78 }; ··· 92 84 next-level-cache = <&L2_3>; 93 85 L2_3: l2-cache { 94 86 compatible = "cache"; 87 + cache-level = <2>; 88 + cache-unified; 95 89 next-level-cache = <&L3_0>; 96 90 }; 97 91 }; ··· 107 97 next-level-cache = <&L2_4>; 108 98 L2_4: l2-cache { 109 99 compatible = "cache"; 100 + cache-level = <2>; 101 + cache-unified; 110 102 next-level-cache = <&L3_1>; 111 103 L3_1: l3-cache { 112 104 compatible = "cache"; 105 + cache-level = <3>; 106 + cache-unified; 113 107 }; 114 108 115 109 }; ··· 128 114 next-level-cache = <&L2_5>; 129 115 L2_5: l2-cache { 130 116 compatible = "cache"; 117 + cache-level = <2>; 118 + cache-unified; 131 119 next-level-cache = <&L3_1>; 132 120 }; 133 121 }; ··· 143 127 next-level-cache = <&L2_6>; 144 128 L2_6: l2-cache { 145 129 compatible = "cache"; 130 + cache-level = <2>; 131 + cache-unified; 146 132 next-level-cache = <&L3_1>; 147 133 }; 148 134 }; ··· 158 140 next-level-cache = <&L2_7>; 159 141 L2_7: l2-cache { 160 142 compatible = "cache"; 143 + cache-level = <2>; 144 + cache-unified; 161 145 next-level-cache = <&L3_1>; 162 146 }; 163 147 };
+8
arch/arm64/boot/dts/qcom/sc7180-lite.dtsi
··· 16 16 &cpu6_opp12 { 17 17 opp-peak-kBps = <8532000 23347200>; 18 18 }; 19 + 20 + &cpu6_opp13 { 21 + opp-peak-kBps = <8532000 23347200>; 22 + }; 23 + 24 + &cpu6_opp14 { 25 + opp-peak-kBps = <8532000 23347200>; 26 + };
+9
arch/arm64/boot/dts/qcom/sc7180.dtsi
··· 92 92 L2_0: l2-cache { 93 93 compatible = "cache"; 94 94 cache-level = <2>; 95 + cache-unified; 95 96 next-level-cache = <&L3_0>; 96 97 L3_0: l3-cache { 97 98 compatible = "cache"; 98 99 cache-level = <3>; 100 + cache-unified; 99 101 }; 100 102 }; 101 103 }; ··· 122 120 L2_100: l2-cache { 123 121 compatible = "cache"; 124 122 cache-level = <2>; 123 + cache-unified; 125 124 next-level-cache = <&L3_0>; 126 125 }; 127 126 }; ··· 147 144 L2_200: l2-cache { 148 145 compatible = "cache"; 149 146 cache-level = <2>; 147 + cache-unified; 150 148 next-level-cache = <&L3_0>; 151 149 }; 152 150 }; ··· 172 168 L2_300: l2-cache { 173 169 compatible = "cache"; 174 170 cache-level = <2>; 171 + cache-unified; 175 172 next-level-cache = <&L3_0>; 176 173 }; 177 174 }; ··· 197 192 L2_400: l2-cache { 198 193 compatible = "cache"; 199 194 cache-level = <2>; 195 + cache-unified; 200 196 next-level-cache = <&L3_0>; 201 197 }; 202 198 }; ··· 222 216 L2_500: l2-cache { 223 217 compatible = "cache"; 224 218 cache-level = <2>; 219 + cache-unified; 225 220 next-level-cache = <&L3_0>; 226 221 }; 227 222 }; ··· 247 240 L2_600: l2-cache { 248 241 compatible = "cache"; 249 242 cache-level = <2>; 243 + cache-unified; 250 244 next-level-cache = <&L3_0>; 251 245 }; 252 246 }; ··· 272 264 L2_700: l2-cache { 273 265 compatible = "cache"; 274 266 cache-level = <2>; 267 + cache-unified; 275 268 next-level-cache = <&L3_0>; 276 269 }; 277 270 };
-2
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
··· 480 480 wcd_rx: codec@0,4 { 481 481 compatible = "sdw20217010d00"; 482 482 reg = <0 4>; 483 - #sound-dai-cells = <1>; 484 483 qcom,rx-port-mapping = <1 2 3 4 5>; 485 484 }; 486 485 }; ··· 490 491 wcd_tx: codec@0,3 { 491 492 compatible = "sdw20217010d00"; 492 493 reg = <0 3>; 493 - #sound-dai-cells = <1>; 494 494 qcom,tx-port-mapping = <1 2 3 4>; 495 495 }; 496 496 };
-2
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
··· 414 414 wcd_rx: codec@0,4 { 415 415 compatible = "sdw20217010d00"; 416 416 reg = <0 4>; 417 - #sound-dai-cells = <1>; 418 417 qcom,rx-port-mapping = <1 2 3 4 5>; 419 418 }; 420 419 }; ··· 422 423 wcd_tx: codec@0,3 { 423 424 compatible = "sdw20217010d00"; 424 425 reg = <0 3>; 425 - #sound-dai-cells = <1>; 426 426 qcom,tx-port-mapping = <1 2 3 4>; 427 427 }; 428 428 };
+9
arch/arm64/boot/dts/qcom/sc7280.dtsi
··· 182 182 L2_0: l2-cache { 183 183 compatible = "cache"; 184 184 cache-level = <2>; 185 + cache-unified; 185 186 next-level-cache = <&L3_0>; 186 187 L3_0: l3-cache { 187 188 compatible = "cache"; 188 189 cache-level = <3>; 190 + cache-unified; 189 191 }; 190 192 }; 191 193 }; ··· 210 208 L2_100: l2-cache { 211 209 compatible = "cache"; 212 210 cache-level = <2>; 211 + cache-unified; 213 212 next-level-cache = <&L3_0>; 214 213 }; 215 214 }; ··· 233 230 L2_200: l2-cache { 234 231 compatible = "cache"; 235 232 cache-level = <2>; 233 + cache-unified; 236 234 next-level-cache = <&L3_0>; 237 235 }; 238 236 }; ··· 256 252 L2_300: l2-cache { 257 253 compatible = "cache"; 258 254 cache-level = <2>; 255 + cache-unified; 259 256 next-level-cache = <&L3_0>; 260 257 }; 261 258 }; ··· 279 274 L2_400: l2-cache { 280 275 compatible = "cache"; 281 276 cache-level = <2>; 277 + cache-unified; 282 278 next-level-cache = <&L3_0>; 283 279 }; 284 280 }; ··· 302 296 L2_500: l2-cache { 303 297 compatible = "cache"; 304 298 cache-level = <2>; 299 + cache-unified; 305 300 next-level-cache = <&L3_0>; 306 301 }; 307 302 }; ··· 325 318 L2_600: l2-cache { 326 319 compatible = "cache"; 327 320 cache-level = <2>; 321 + cache-unified; 328 322 next-level-cache = <&L3_0>; 329 323 }; 330 324 }; ··· 348 340 L2_700: l2-cache { 349 341 compatible = "cache"; 350 342 cache-level = <2>; 343 + cache-unified; 351 344 next-level-cache = <&L3_0>; 352 345 }; 353 346 };
+16 -2
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
··· 58 58 L2_0: l2-cache { 59 59 compatible = "cache"; 60 60 cache-level = <2>; 61 + cache-unified; 61 62 next-level-cache = <&L3_0>; 62 63 L3_0: l3-cache { 63 - compatible = "cache"; 64 - cache-level = <3>; 64 + compatible = "cache"; 65 + cache-level = <3>; 66 + cache-unified; 65 67 }; 66 68 }; 67 69 }; ··· 85 83 L2_100: l2-cache { 86 84 compatible = "cache"; 87 85 cache-level = <2>; 86 + cache-unified; 88 87 next-level-cache = <&L3_0>; 89 88 }; 90 89 }; ··· 107 104 L2_200: l2-cache { 108 105 compatible = "cache"; 109 106 cache-level = <2>; 107 + cache-unified; 110 108 next-level-cache = <&L3_0>; 111 109 }; 112 110 }; ··· 129 125 L2_300: l2-cache { 130 126 compatible = "cache"; 131 127 cache-level = <2>; 128 + cache-unified; 132 129 next-level-cache = <&L3_0>; 133 130 }; 134 131 }; ··· 151 146 L2_400: l2-cache { 152 147 compatible = "cache"; 153 148 cache-level = <2>; 149 + cache-unified; 154 150 next-level-cache = <&L3_0>; 155 151 }; 156 152 }; ··· 173 167 L2_500: l2-cache { 174 168 compatible = "cache"; 175 169 cache-level = <2>; 170 + cache-unified; 176 171 next-level-cache = <&L3_0>; 177 172 }; 178 173 }; ··· 195 188 L2_600: l2-cache { 196 189 compatible = "cache"; 197 190 cache-level = <2>; 191 + cache-unified; 198 192 next-level-cache = <&L3_0>; 199 193 }; 200 194 }; ··· 217 209 L2_700: l2-cache { 218 210 compatible = "cache"; 219 211 cache-level = <2>; 212 + cache-unified; 220 213 next-level-cache = <&L3_0>; 221 214 }; 222 215 }; ··· 2735 2726 pins = "gpio7"; 2736 2727 function = "dmic1_data"; 2737 2728 drive-strength = <8>; 2729 + input-enable; 2738 2730 }; 2739 2731 }; 2740 2732 ··· 2753 2743 function = "dmic1_data"; 2754 2744 drive-strength = <2>; 2755 2745 bias-pull-down; 2746 + input-enable; 2756 2747 }; 2757 2748 }; 2758 2749 ··· 2769 2758 pins = "gpio9"; 2770 2759 function = "dmic2_data"; 2771 2760 drive-strength = <8>; 2761 + input-enable; 2772 2762 }; 2773 2763 }; 2774 2764 ··· 2787 2775 function = "dmic2_data"; 2788 2776 drive-strength = <2>; 2789 2777 bias-pull-down; 2778 + input-enable; 2790 2779 }; 2791 2780 }; 2792 2781 ··· 3995 3982 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3996 3983 <WAKE_TCS 3>, <CONTROL_TCS 1>; 3997 3984 label = "apps_rsc"; 3985 + power-domains = <&CLUSTER_PD>; 3998 3986 3999 3987 apps_bcm_voter: bcm-voter { 4000 3988 compatible = "qcom,bcm-voter";
+2
arch/arm64/boot/dts/qcom/sdm630.dtsi
··· 63 63 L2_1: l2-cache { 64 64 compatible = "cache"; 65 65 cache-level = <2>; 66 + cache-unified; 66 67 }; 67 68 }; 68 69 ··· 128 127 L2_0: l2-cache { 129 128 compatible = "cache"; 130 129 cache-level = <2>; 130 + cache-unified; 131 131 }; 132 132 }; 133 133
+19 -1
arch/arm64/boot/dts/qcom/sdm670.dtsi
··· 41 41 L2_0: l2-cache { 42 42 compatible = "cache"; 43 43 next-level-cache = <&L3_0>; 44 + cache-level = <2>; 45 + cache-unified; 44 46 L3_0: l3-cache { 45 - compatible = "cache"; 47 + compatible = "cache"; 48 + cache-level = <3>; 49 + cache-unified; 46 50 }; 47 51 }; 48 52 }; ··· 61 57 next-level-cache = <&L2_100>; 62 58 L2_100: l2-cache { 63 59 compatible = "cache"; 60 + cache-level = <2>; 61 + cache-unified; 64 62 next-level-cache = <&L3_0>; 65 63 }; 66 64 }; ··· 77 71 next-level-cache = <&L2_200>; 78 72 L2_200: l2-cache { 79 73 compatible = "cache"; 74 + cache-level = <2>; 75 + cache-unified; 80 76 next-level-cache = <&L3_0>; 81 77 }; 82 78 }; ··· 93 85 next-level-cache = <&L2_300>; 94 86 L2_300: l2-cache { 95 87 compatible = "cache"; 88 + cache-level = <2>; 89 + cache-unified; 96 90 next-level-cache = <&L3_0>; 97 91 }; 98 92 }; ··· 109 99 next-level-cache = <&L2_400>; 110 100 L2_400: l2-cache { 111 101 compatible = "cache"; 102 + cache-level = <2>; 103 + cache-unified; 112 104 next-level-cache = <&L3_0>; 113 105 }; 114 106 }; ··· 125 113 next-level-cache = <&L2_500>; 126 114 L2_500: l2-cache { 127 115 compatible = "cache"; 116 + cache-level = <2>; 117 + cache-unified; 128 118 next-level-cache = <&L3_0>; 129 119 }; 130 120 }; ··· 141 127 next-level-cache = <&L2_600>; 142 128 L2_600: l2-cache { 143 129 compatible = "cache"; 130 + cache-level = <2>; 131 + cache-unified; 144 132 next-level-cache = <&L3_0>; 145 133 }; 146 134 }; ··· 157 141 next-level-cache = <&L2_700>; 158 142 L2_700: l2-cache { 159 143 compatible = "cache"; 144 + cache-level = <2>; 145 + cache-unified; 160 146 next-level-cache = <&L3_0>; 161 147 }; 162 148 };
+11 -2
arch/arm64/boot/dts/qcom/sdm845.dtsi
··· 108 108 L2_0: l2-cache { 109 109 compatible = "cache"; 110 110 cache-level = <2>; 111 + cache-unified; 111 112 next-level-cache = <&L3_0>; 112 113 L3_0: l3-cache { 113 - compatible = "cache"; 114 - cache-level = <3>; 114 + compatible = "cache"; 115 + cache-level = <3>; 116 + cache-unified; 115 117 }; 116 118 }; 117 119 }; ··· 137 135 L2_100: l2-cache { 138 136 compatible = "cache"; 139 137 cache-level = <2>; 138 + cache-unified; 140 139 next-level-cache = <&L3_0>; 141 140 }; 142 141 }; ··· 161 158 L2_200: l2-cache { 162 159 compatible = "cache"; 163 160 cache-level = <2>; 161 + cache-unified; 164 162 next-level-cache = <&L3_0>; 165 163 }; 166 164 }; ··· 185 181 L2_300: l2-cache { 186 182 compatible = "cache"; 187 183 cache-level = <2>; 184 + cache-unified; 188 185 next-level-cache = <&L3_0>; 189 186 }; 190 187 }; ··· 209 204 L2_400: l2-cache { 210 205 compatible = "cache"; 211 206 cache-level = <2>; 207 + cache-unified; 212 208 next-level-cache = <&L3_0>; 213 209 }; 214 210 }; ··· 233 227 L2_500: l2-cache { 234 228 compatible = "cache"; 235 229 cache-level = <2>; 230 + cache-unified; 236 231 next-level-cache = <&L3_0>; 237 232 }; 238 233 }; ··· 257 250 L2_600: l2-cache { 258 251 compatible = "cache"; 259 252 cache-level = <2>; 253 + cache-unified; 260 254 next-level-cache = <&L3_0>; 261 255 }; 262 256 }; ··· 281 273 L2_700: l2-cache { 282 274 compatible = "cache"; 283 275 cache-level = <2>; 276 + cache-unified; 284 277 next-level-cache = <&L3_0>; 285 278 }; 286 279 };
+2
arch/arm64/boot/dts/qcom/sm6115.dtsi
··· 50 50 L2_0: l2-cache { 51 51 compatible = "cache"; 52 52 cache-level = <2>; 53 + cache-unified; 53 54 }; 54 55 }; 55 56 ··· 103 102 L2_1: l2-cache { 104 103 compatible = "cache"; 105 104 cache-level = <2>; 105 + cache-unified; 106 106 }; 107 107 }; 108 108
+2
arch/arm64/boot/dts/qcom/sm6125.dtsi
··· 47 47 L2_0: l2-cache { 48 48 compatible = "cache"; 49 49 cache-level = <2>; 50 + cache-unified; 50 51 }; 51 52 }; 52 53 ··· 88 87 L2_1: l2-cache { 89 88 compatible = "cache"; 90 89 cache-level = <2>; 90 + cache-unified; 91 91 }; 92 92 }; 93 93
+9
arch/arm64/boot/dts/qcom/sm6350.dtsi
··· 60 60 L2_0: l2-cache { 61 61 compatible = "cache"; 62 62 cache-level = <2>; 63 + cache-unified; 63 64 next-level-cache = <&L3_0>; 64 65 L3_0: l3-cache { 65 66 compatible = "cache"; 66 67 cache-level = <3>; 68 + cache-unified; 67 69 }; 68 70 }; 69 71 }; ··· 88 86 L2_100: l2-cache { 89 87 compatible = "cache"; 90 88 cache-level = <2>; 89 + cache-unified; 91 90 next-level-cache = <&L3_0>; 92 91 }; 93 92 }; ··· 111 108 L2_200: l2-cache { 112 109 compatible = "cache"; 113 110 cache-level = <2>; 111 + cache-unified; 114 112 next-level-cache = <&L3_0>; 115 113 }; 116 114 }; ··· 134 130 L2_300: l2-cache { 135 131 compatible = "cache"; 136 132 cache-level = <2>; 133 + cache-unified; 137 134 next-level-cache = <&L3_0>; 138 135 }; 139 136 }; ··· 157 152 L2_400: l2-cache { 158 153 compatible = "cache"; 159 154 cache-level = <2>; 155 + cache-unified; 160 156 next-level-cache = <&L3_0>; 161 157 }; 162 158 }; ··· 180 174 L2_500: l2-cache { 181 175 compatible = "cache"; 182 176 cache-level = <2>; 177 + cache-unified; 183 178 next-level-cache = <&L3_0>; 184 179 }; 185 180 }; ··· 203 196 L2_600: l2-cache { 204 197 compatible = "cache"; 205 198 cache-level = <2>; 199 + cache-unified; 206 200 next-level-cache = <&L3_0>; 207 201 }; 208 202 }; ··· 226 218 L2_700: l2-cache { 227 219 compatible = "cache"; 228 220 cache-level = <2>; 221 + cache-unified; 229 222 next-level-cache = <&L3_0>; 230 223 }; 231 224 };
+2 -2
arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts
··· 178 178 }; 179 179 180 180 &remoteproc_adsp { 181 - firmware-name = "qcom/Sony/murray/adsp.mbn"; 181 + firmware-name = "qcom/sm6375/Sony/murray/adsp.mbn"; 182 182 status = "okay"; 183 183 }; 184 184 185 185 &remoteproc_cdsp { 186 - firmware-name = "qcom/Sony/murray/cdsp.mbn"; 186 + firmware-name = "qcom/sm6375/Sony/murray/cdsp.mbn"; 187 187 status = "okay"; 188 188 }; 189 189
+35 -17
arch/arm64/boot/dts/qcom/sm6375.dtsi
··· 48 48 power-domain-names = "psci"; 49 49 #cooling-cells = <2>; 50 50 L2_0: l2-cache { 51 - compatible = "cache"; 52 - next-level-cache = <&L3_0>; 51 + compatible = "cache"; 52 + cache-level = <2>; 53 + cache-unified; 54 + next-level-cache = <&L3_0>; 53 55 L3_0: l3-cache { 54 - compatible = "cache"; 56 + compatible = "cache"; 57 + cache-level = <3>; 58 + cache-unified; 55 59 }; 56 60 }; 57 61 }; ··· 72 68 power-domain-names = "psci"; 73 69 #cooling-cells = <2>; 74 70 L2_100: l2-cache { 75 - compatible = "cache"; 76 - next-level-cache = <&L3_0>; 71 + compatible = "cache"; 72 + cache-level = <2>; 73 + cache-unified; 74 + next-level-cache = <&L3_0>; 77 75 }; 78 76 }; 79 77 ··· 91 85 power-domain-names = "psci"; 92 86 #cooling-cells = <2>; 93 87 L2_200: l2-cache { 94 - compatible = "cache"; 95 - next-level-cache = <&L3_0>; 88 + compatible = "cache"; 89 + cache-level = <2>; 90 + cache-unified; 91 + next-level-cache = <&L3_0>; 96 92 }; 97 93 }; 98 94 ··· 110 102 power-domain-names = "psci"; 111 103 #cooling-cells = <2>; 112 104 L2_300: l2-cache { 113 - compatible = "cache"; 114 - next-level-cache = <&L3_0>; 105 + compatible = "cache"; 106 + cache-level = <2>; 107 + cache-unified; 108 + next-level-cache = <&L3_0>; 115 109 }; 116 110 }; 117 111 ··· 129 119 power-domain-names = "psci"; 130 120 #cooling-cells = <2>; 131 121 L2_400: l2-cache { 132 - compatible = "cache"; 133 - next-level-cache = <&L3_0>; 122 + compatible = "cache"; 123 + cache-level = <2>; 124 + cache-unified; 125 + next-level-cache = <&L3_0>; 134 126 }; 135 127 }; 136 128 ··· 148 136 power-domain-names = "psci"; 149 137 #cooling-cells = <2>; 150 138 L2_500: l2-cache { 151 - compatible = "cache"; 152 - next-level-cache = <&L3_0>; 139 + compatible = "cache"; 140 + cache-level = <2>; 141 + cache-unified; 142 + next-level-cache = <&L3_0>; 153 143 }; 154 144 }; 155 145 ··· 167 153 power-domain-names = "psci"; 168 154 #cooling-cells = <2>; 169 155 L2_600: l2-cache { 170 - compatible = "cache"; 171 - next-level-cache = <&L3_0>; 156 + compatible = "cache"; 157 + cache-level = <2>; 158 + cache-unified; 159 + next-level-cache = <&L3_0>; 172 160 }; 173 161 }; 174 162 ··· 186 170 power-domain-names = "psci"; 187 171 #cooling-cells = <2>; 188 172 L2_700: l2-cache { 189 - compatible = "cache"; 190 - next-level-cache = <&L3_0>; 173 + compatible = "cache"; 174 + cache-level = <2>; 175 + cache-unified; 176 + next-level-cache = <&L3_0>; 191 177 }; 192 178 }; 193 179
+11 -2
arch/arm64/boot/dts/qcom/sm8150.dtsi
··· 63 63 L2_0: l2-cache { 64 64 compatible = "cache"; 65 65 cache-level = <2>; 66 + cache-unified; 66 67 next-level-cache = <&L3_0>; 67 68 L3_0: l3-cache { 68 - compatible = "cache"; 69 - cache-level = <3>; 69 + compatible = "cache"; 70 + cache-level = <3>; 71 + cache-unified; 70 72 }; 71 73 }; 72 74 }; ··· 92 90 L2_100: l2-cache { 93 91 compatible = "cache"; 94 92 cache-level = <2>; 93 + cache-unified; 95 94 next-level-cache = <&L3_0>; 96 95 }; 97 96 }; ··· 116 113 L2_200: l2-cache { 117 114 compatible = "cache"; 118 115 cache-level = <2>; 116 + cache-unified; 119 117 next-level-cache = <&L3_0>; 120 118 }; 121 119 }; ··· 140 136 L2_300: l2-cache { 141 137 compatible = "cache"; 142 138 cache-level = <2>; 139 + cache-unified; 143 140 next-level-cache = <&L3_0>; 144 141 }; 145 142 }; ··· 164 159 L2_400: l2-cache { 165 160 compatible = "cache"; 166 161 cache-level = <2>; 162 + cache-unified; 167 163 next-level-cache = <&L3_0>; 168 164 }; 169 165 }; ··· 188 182 L2_500: l2-cache { 189 183 compatible = "cache"; 190 184 cache-level = <2>; 185 + cache-unified; 191 186 next-level-cache = <&L3_0>; 192 187 }; 193 188 }; ··· 212 205 L2_600: l2-cache { 213 206 compatible = "cache"; 214 207 cache-level = <2>; 208 + cache-unified; 215 209 next-level-cache = <&L3_0>; 216 210 }; 217 211 }; ··· 236 228 L2_700: l2-cache { 237 229 compatible = "cache"; 238 230 cache-level = <2>; 231 + cache-unified; 239 232 next-level-cache = <&L3_0>; 240 233 }; 241 234 };
+1 -1
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-boe.dts
··· 13 13 }; 14 14 15 15 &display_panel { 16 - compatible = "xiaomi,elish-boe-nt36523"; 16 + compatible = "xiaomi,elish-boe-nt36523", "novatek,nt36523"; 17 17 status = "okay"; 18 18 };
+1 -1
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-csot.dts
··· 13 13 }; 14 14 15 15 &display_panel { 16 - compatible = "xiaomi,elish-csot-nt36523"; 16 + compatible = "xiaomi,elish-csot-nt36523", "novatek,nt36523"; 17 17 status = "okay"; 18 18 };
+35 -26
arch/arm64/boot/dts/qcom/sm8350.dtsi
··· 58 58 power-domain-names = "psci"; 59 59 #cooling-cells = <2>; 60 60 L2_0: l2-cache { 61 - compatible = "cache"; 62 - cache-level = <2>; 63 - next-level-cache = <&L3_0>; 61 + compatible = "cache"; 62 + cache-level = <2>; 63 + cache-unified; 64 + next-level-cache = <&L3_0>; 64 65 L3_0: l3-cache { 65 - compatible = "cache"; 66 - cache-level = <3>; 66 + compatible = "cache"; 67 + cache-level = <3>; 68 + cache-unified; 67 69 }; 68 70 }; 69 71 }; ··· 82 80 power-domain-names = "psci"; 83 81 #cooling-cells = <2>; 84 82 L2_100: l2-cache { 85 - compatible = "cache"; 86 - cache-level = <2>; 87 - next-level-cache = <&L3_0>; 83 + compatible = "cache"; 84 + cache-level = <2>; 85 + cache-unified; 86 + next-level-cache = <&L3_0>; 88 87 }; 89 88 }; 90 89 ··· 101 98 power-domain-names = "psci"; 102 99 #cooling-cells = <2>; 103 100 L2_200: l2-cache { 104 - compatible = "cache"; 105 - cache-level = <2>; 106 - next-level-cache = <&L3_0>; 101 + compatible = "cache"; 102 + cache-level = <2>; 103 + cache-unified; 104 + next-level-cache = <&L3_0>; 107 105 }; 108 106 }; 109 107 ··· 120 116 power-domain-names = "psci"; 121 117 #cooling-cells = <2>; 122 118 L2_300: l2-cache { 123 - compatible = "cache"; 124 - cache-level = <2>; 125 - next-level-cache = <&L3_0>; 119 + compatible = "cache"; 120 + cache-level = <2>; 121 + cache-unified; 122 + next-level-cache = <&L3_0>; 126 123 }; 127 124 }; 128 125 ··· 139 134 power-domain-names = "psci"; 140 135 #cooling-cells = <2>; 141 136 L2_400: l2-cache { 142 - compatible = "cache"; 143 - cache-level = <2>; 144 - next-level-cache = <&L3_0>; 137 + compatible = "cache"; 138 + cache-level = <2>; 139 + cache-unified; 140 + next-level-cache = <&L3_0>; 145 141 }; 146 142 }; 147 143 ··· 158 152 power-domain-names = "psci"; 159 153 #cooling-cells = <2>; 160 154 L2_500: l2-cache { 161 - compatible = "cache"; 162 - cache-level = <2>; 163 - next-level-cache = <&L3_0>; 155 + compatible = "cache"; 156 + cache-level = <2>; 157 + cache-unified; 158 + next-level-cache = <&L3_0>; 164 159 }; 165 160 }; 166 161 ··· 177 170 power-domain-names = "psci"; 178 171 #cooling-cells = <2>; 179 172 L2_600: l2-cache { 180 - compatible = "cache"; 181 - cache-level = <2>; 182 - next-level-cache = <&L3_0>; 173 + compatible = "cache"; 174 + cache-level = <2>; 175 + cache-unified; 176 + next-level-cache = <&L3_0>; 183 177 }; 184 178 }; 185 179 ··· 196 188 power-domain-names = "psci"; 197 189 #cooling-cells = <2>; 198 190 L2_700: l2-cache { 199 - compatible = "cache"; 200 - cache-level = <2>; 201 - next-level-cache = <&L3_0>; 191 + compatible = "cache"; 192 + cache-level = <2>; 193 + cache-unified; 194 + next-level-cache = <&L3_0>; 202 195 }; 203 196 }; 204 197
+35 -26
arch/arm64/boot/dts/qcom/sm8450.dtsi
··· 57 57 #cooling-cells = <2>; 58 58 clocks = <&cpufreq_hw 0>; 59 59 L2_0: l2-cache { 60 - compatible = "cache"; 61 - cache-level = <2>; 62 - next-level-cache = <&L3_0>; 60 + compatible = "cache"; 61 + cache-level = <2>; 62 + cache-unified; 63 + next-level-cache = <&L3_0>; 63 64 L3_0: l3-cache { 64 - compatible = "cache"; 65 - cache-level = <3>; 65 + compatible = "cache"; 66 + cache-level = <3>; 67 + cache-unified; 66 68 }; 67 69 }; 68 70 }; ··· 81 79 #cooling-cells = <2>; 82 80 clocks = <&cpufreq_hw 0>; 83 81 L2_100: l2-cache { 84 - compatible = "cache"; 85 - cache-level = <2>; 86 - next-level-cache = <&L3_0>; 82 + compatible = "cache"; 83 + cache-level = <2>; 84 + cache-unified; 85 + next-level-cache = <&L3_0>; 87 86 }; 88 87 }; 89 88 ··· 100 97 #cooling-cells = <2>; 101 98 clocks = <&cpufreq_hw 0>; 102 99 L2_200: l2-cache { 103 - compatible = "cache"; 104 - cache-level = <2>; 105 - next-level-cache = <&L3_0>; 100 + compatible = "cache"; 101 + cache-level = <2>; 102 + cache-unified; 103 + next-level-cache = <&L3_0>; 106 104 }; 107 105 }; 108 106 ··· 119 115 #cooling-cells = <2>; 120 116 clocks = <&cpufreq_hw 0>; 121 117 L2_300: l2-cache { 122 - compatible = "cache"; 123 - cache-level = <2>; 124 - next-level-cache = <&L3_0>; 118 + compatible = "cache"; 119 + cache-level = <2>; 120 + cache-unified; 121 + next-level-cache = <&L3_0>; 125 122 }; 126 123 }; 127 124 ··· 138 133 #cooling-cells = <2>; 139 134 clocks = <&cpufreq_hw 1>; 140 135 L2_400: l2-cache { 141 - compatible = "cache"; 142 - cache-level = <2>; 143 - next-level-cache = <&L3_0>; 136 + compatible = "cache"; 137 + cache-level = <2>; 138 + cache-unified; 139 + next-level-cache = <&L3_0>; 144 140 }; 145 141 }; 146 142 ··· 157 151 #cooling-cells = <2>; 158 152 clocks = <&cpufreq_hw 1>; 159 153 L2_500: l2-cache { 160 - compatible = "cache"; 161 - cache-level = <2>; 162 - next-level-cache = <&L3_0>; 154 + compatible = "cache"; 155 + cache-level = <2>; 156 + cache-unified; 157 + next-level-cache = <&L3_0>; 163 158 }; 164 159 }; 165 160 ··· 176 169 #cooling-cells = <2>; 177 170 clocks = <&cpufreq_hw 1>; 178 171 L2_600: l2-cache { 179 - compatible = "cache"; 180 - cache-level = <2>; 181 - next-level-cache = <&L3_0>; 172 + compatible = "cache"; 173 + cache-level = <2>; 174 + cache-unified; 175 + next-level-cache = <&L3_0>; 182 176 }; 183 177 }; 184 178 ··· 195 187 #cooling-cells = <2>; 196 188 clocks = <&cpufreq_hw 2>; 197 189 L2_700: l2-cache { 198 - compatible = "cache"; 199 - cache-level = <2>; 200 - next-level-cache = <&L3_0>; 190 + compatible = "cache"; 191 + cache-level = <2>; 192 + cache-unified; 193 + next-level-cache = <&L3_0>; 201 194 }; 202 195 }; 203 196
+21 -5
arch/arm64/boot/dts/qcom/sm8550.dtsi
··· 80 80 L2_0: l2-cache { 81 81 compatible = "cache"; 82 82 cache-level = <2>; 83 + cache-unified; 83 84 next-level-cache = <&L3_0>; 84 85 L3_0: l3-cache { 85 86 compatible = "cache"; 86 87 cache-level = <3>; 88 + cache-unified; 87 89 }; 88 90 }; 89 91 }; ··· 106 104 L2_100: l2-cache { 107 105 compatible = "cache"; 108 106 cache-level = <2>; 107 + cache-unified; 109 108 next-level-cache = <&L3_0>; 110 109 }; 111 110 }; ··· 127 124 L2_200: l2-cache { 128 125 compatible = "cache"; 129 126 cache-level = <2>; 127 + cache-unified; 130 128 next-level-cache = <&L3_0>; 131 129 }; 132 130 }; ··· 148 144 L2_300: l2-cache { 149 145 compatible = "cache"; 150 146 cache-level = <2>; 147 + cache-unified; 151 148 next-level-cache = <&L3_0>; 152 149 }; 153 150 }; ··· 169 164 L2_400: l2-cache { 170 165 compatible = "cache"; 171 166 cache-level = <2>; 167 + cache-unified; 172 168 next-level-cache = <&L3_0>; 173 169 }; 174 170 }; ··· 190 184 L2_500: l2-cache { 191 185 compatible = "cache"; 192 186 cache-level = <2>; 187 + cache-unified; 193 188 next-level-cache = <&L3_0>; 194 189 }; 195 190 }; ··· 211 204 L2_600: l2-cache { 212 205 compatible = "cache"; 213 206 cache-level = <2>; 207 + cache-unified; 214 208 next-level-cache = <&L3_0>; 215 209 }; 216 210 }; ··· 232 224 L2_700: l2-cache { 233 225 compatible = "cache"; 234 226 cache-level = <2>; 227 + cache-unified; 235 228 next-level-cache = <&L3_0>; 236 229 }; 237 230 }; ··· 2031 2022 qcom,din-ports = <4>; 2032 2023 qcom,dout-ports = <9>; 2033 2024 2034 - qcom,ports-sinterval = <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2025 + qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2035 2026 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2036 2027 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2037 2028 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; ··· 2077 2068 qcom,din-ports = <0>; 2078 2069 qcom,dout-ports = <10>; 2079 2070 2080 - qcom,ports-sinterval = <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>; 2071 + qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>; 2081 2072 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>; 2082 2073 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>; 2083 2074 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>; ··· 2142 2133 qcom,din-ports = <4>; 2143 2134 qcom,dout-ports = <9>; 2144 2135 2145 - qcom,ports-sinterval = <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2136 + qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2146 2137 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2147 2138 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2148 2139 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; ··· 3771 3762 3772 3763 system-cache-controller@25000000 { 3773 3764 compatible = "qcom,sm8550-llcc"; 3774 - reg = <0 0x25000000 0 0x800000>, 3765 + reg = <0 0x25000000 0 0x200000>, 3766 + <0 0x25200000 0 0x200000>, 3767 + <0 0x25400000 0 0x200000>, 3768 + <0 0x25600000 0 0x200000>, 3775 3769 <0 0x25800000 0 0x200000>; 3776 - reg-names = "llcc_base", "llcc_broadcast_base"; 3770 + reg-names = "llcc0_base", 3771 + "llcc1_base", 3772 + "llcc2_base", 3773 + "llcc3_base", 3774 + "llcc_broadcast_base"; 3777 3775 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3778 3776 }; 3779 3777
+59 -59
drivers/edac/qcom_edac.c
··· 21 21 #define TRP_SYN_REG_CNT 6 22 22 #define DRP_SYN_REG_CNT 8 23 23 24 - #define LLCC_COMMON_STATUS0 0x0003000c 25 24 #define LLCC_LB_CNT_MASK GENMASK(31, 28) 26 25 #define LLCC_LB_CNT_SHIFT 28 27 - 28 - /* Single & double bit syndrome register offsets */ 29 - #define TRP_ECC_SB_ERR_SYN0 0x0002304c 30 - #define TRP_ECC_DB_ERR_SYN0 0x00020370 31 - #define DRP_ECC_SB_ERR_SYN0 0x0004204c 32 - #define DRP_ECC_DB_ERR_SYN0 0x00042070 33 - 34 - /* Error register offsets */ 35 - #define TRP_ECC_ERROR_STATUS1 0x00020348 36 - #define TRP_ECC_ERROR_STATUS0 0x00020344 37 - #define DRP_ECC_ERROR_STATUS1 0x00042048 38 - #define DRP_ECC_ERROR_STATUS0 0x00042044 39 - 40 - /* TRP, DRP interrupt register offsets */ 41 - #define DRP_INTERRUPT_STATUS 0x00041000 42 - #define TRP_INTERRUPT_0_STATUS 0x00020480 43 - #define DRP_INTERRUPT_CLEAR 0x00041008 44 - #define DRP_ECC_ERROR_CNTR_CLEAR 0x00040004 45 - #define TRP_INTERRUPT_0_CLEAR 0x00020484 46 - #define TRP_ECC_ERROR_CNTR_CLEAR 0x00020440 47 26 48 27 /* Mask and shift macros */ 49 28 #define ECC_DB_ERR_COUNT_MASK GENMASK(4, 0) ··· 38 59 39 60 #define DRP_TRP_INT_CLEAR GENMASK(1, 0) 40 61 #define DRP_TRP_CNT_CLEAR GENMASK(1, 0) 41 - 42 - /* Config registers offsets*/ 43 - #define DRP_ECC_ERROR_CFG 0x00040000 44 - 45 - /* Tag RAM, Data RAM interrupt register offsets */ 46 - #define CMN_INTERRUPT_0_ENABLE 0x0003001c 47 - #define CMN_INTERRUPT_2_ENABLE 0x0003003c 48 - #define TRP_INTERRUPT_0_ENABLE 0x00020488 49 - #define DRP_INTERRUPT_ENABLE 0x0004100c 50 62 51 63 #define SB_ERROR_THRESHOLD 0x1 52 64 #define SB_ERROR_THRESHOLD_SHIFT 24 ··· 58 88 static const struct llcc_edac_reg_data edac_reg_data[] = { 59 89 [LLCC_DRAM_CE] = { 60 90 .name = "DRAM Single-bit", 61 - .synd_reg = DRP_ECC_SB_ERR_SYN0, 62 - .count_status_reg = DRP_ECC_ERROR_STATUS1, 63 - .ways_status_reg = DRP_ECC_ERROR_STATUS0, 64 91 .reg_cnt = DRP_SYN_REG_CNT, 65 92 .count_mask = ECC_SB_ERR_COUNT_MASK, 66 93 .ways_mask = ECC_SB_ERR_WAYS_MASK, ··· 65 98 }, 66 99 [LLCC_DRAM_UE] = { 67 100 .name = "DRAM Double-bit", 68 - .synd_reg = DRP_ECC_DB_ERR_SYN0, 69 - .count_status_reg = DRP_ECC_ERROR_STATUS1, 70 - .ways_status_reg = DRP_ECC_ERROR_STATUS0, 71 101 .reg_cnt = DRP_SYN_REG_CNT, 72 102 .count_mask = ECC_DB_ERR_COUNT_MASK, 73 103 .ways_mask = ECC_DB_ERR_WAYS_MASK, ··· 72 108 }, 73 109 [LLCC_TRAM_CE] = { 74 110 .name = "TRAM Single-bit", 75 - .synd_reg = TRP_ECC_SB_ERR_SYN0, 76 - .count_status_reg = TRP_ECC_ERROR_STATUS1, 77 - .ways_status_reg = TRP_ECC_ERROR_STATUS0, 78 111 .reg_cnt = TRP_SYN_REG_CNT, 79 112 .count_mask = ECC_SB_ERR_COUNT_MASK, 80 113 .ways_mask = ECC_SB_ERR_WAYS_MASK, ··· 79 118 }, 80 119 [LLCC_TRAM_UE] = { 81 120 .name = "TRAM Double-bit", 82 - .synd_reg = TRP_ECC_DB_ERR_SYN0, 83 - .count_status_reg = TRP_ECC_ERROR_STATUS1, 84 - .ways_status_reg = TRP_ECC_ERROR_STATUS0, 85 121 .reg_cnt = TRP_SYN_REG_CNT, 86 122 .count_mask = ECC_DB_ERR_COUNT_MASK, 87 123 .ways_mask = ECC_DB_ERR_WAYS_MASK, ··· 86 128 }, 87 129 }; 88 130 89 - static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap) 131 + static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *llcc_bcast_regmap) 90 132 { 91 133 u32 sb_err_threshold; 92 134 int ret; ··· 95 137 * Configure interrupt enable registers such that Tag, Data RAM related 96 138 * interrupts are propagated to interrupt controller for servicing 97 139 */ 98 - ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE, 140 + ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable, 99 141 TRP0_INTERRUPT_ENABLE, 100 142 TRP0_INTERRUPT_ENABLE); 101 143 if (ret) 102 144 return ret; 103 145 104 - ret = regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE, 146 + ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->trp_interrupt_0_enable, 105 147 SB_DB_TRP_INTERRUPT_ENABLE, 106 148 SB_DB_TRP_INTERRUPT_ENABLE); 107 149 if (ret) 108 150 return ret; 109 151 110 152 sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT); 111 - ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG, 153 + ret = regmap_write(llcc_bcast_regmap, drv->edac_reg_offset->drp_ecc_error_cfg, 112 154 sb_err_threshold); 113 155 if (ret) 114 156 return ret; 115 157 116 - ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE, 158 + ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable, 117 159 DRP0_INTERRUPT_ENABLE, 118 160 DRP0_INTERRUPT_ENABLE); 119 161 if (ret) 120 162 return ret; 121 163 122 - ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE, 164 + ret = regmap_write(llcc_bcast_regmap, drv->edac_reg_offset->drp_interrupt_enable, 123 165 SB_DB_DRP_INTERRUPT_ENABLE); 124 166 return ret; 125 167 } ··· 128 170 static int 129 171 qcom_llcc_clear_error_status(int err_type, struct llcc_drv_data *drv) 130 172 { 131 - int ret = 0; 173 + int ret; 132 174 133 175 switch (err_type) { 134 176 case LLCC_DRAM_CE: 135 177 case LLCC_DRAM_UE: 136 - ret = regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR, 178 + ret = regmap_write(drv->bcast_regmap, 179 + drv->edac_reg_offset->drp_interrupt_clear, 137 180 DRP_TRP_INT_CLEAR); 138 181 if (ret) 139 182 return ret; 140 183 141 - ret = regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR, 184 + ret = regmap_write(drv->bcast_regmap, 185 + drv->edac_reg_offset->drp_ecc_error_cntr_clear, 142 186 DRP_TRP_CNT_CLEAR); 143 187 if (ret) 144 188 return ret; 145 189 break; 146 190 case LLCC_TRAM_CE: 147 191 case LLCC_TRAM_UE: 148 - ret = regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR, 192 + ret = regmap_write(drv->bcast_regmap, 193 + drv->edac_reg_offset->trp_interrupt_0_clear, 149 194 DRP_TRP_INT_CLEAR); 150 195 if (ret) 151 196 return ret; 152 197 153 - ret = regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR, 198 + ret = regmap_write(drv->bcast_regmap, 199 + drv->edac_reg_offset->trp_ecc_error_cntr_clear, 154 200 DRP_TRP_CNT_CLEAR); 155 201 if (ret) 156 202 return ret; ··· 167 205 return ret; 168 206 } 169 207 208 + struct qcom_llcc_syn_regs { 209 + u32 synd_reg; 210 + u32 count_status_reg; 211 + u32 ways_status_reg; 212 + }; 213 + 214 + static void get_reg_offsets(struct llcc_drv_data *drv, int err_type, 215 + struct qcom_llcc_syn_regs *syn_regs) 216 + { 217 + const struct llcc_edac_reg_offset *edac_reg_offset = drv->edac_reg_offset; 218 + 219 + switch (err_type) { 220 + case LLCC_DRAM_CE: 221 + syn_regs->synd_reg = edac_reg_offset->drp_ecc_sb_err_syn0; 222 + syn_regs->count_status_reg = edac_reg_offset->drp_ecc_error_status1; 223 + syn_regs->ways_status_reg = edac_reg_offset->drp_ecc_error_status0; 224 + break; 225 + case LLCC_DRAM_UE: 226 + syn_regs->synd_reg = edac_reg_offset->drp_ecc_db_err_syn0; 227 + syn_regs->count_status_reg = edac_reg_offset->drp_ecc_error_status1; 228 + syn_regs->ways_status_reg = edac_reg_offset->drp_ecc_error_status0; 229 + break; 230 + case LLCC_TRAM_CE: 231 + syn_regs->synd_reg = edac_reg_offset->trp_ecc_sb_err_syn0; 232 + syn_regs->count_status_reg = edac_reg_offset->trp_ecc_error_status1; 233 + syn_regs->ways_status_reg = edac_reg_offset->trp_ecc_error_status0; 234 + break; 235 + case LLCC_TRAM_UE: 236 + syn_regs->synd_reg = edac_reg_offset->trp_ecc_db_err_syn0; 237 + syn_regs->count_status_reg = edac_reg_offset->trp_ecc_error_status1; 238 + syn_regs->ways_status_reg = edac_reg_offset->trp_ecc_error_status0; 239 + break; 240 + } 241 + } 242 + 170 243 /* Dump Syndrome registers data for Tag RAM, Data RAM bit errors*/ 171 244 static int 172 245 dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) 173 246 { 174 247 struct llcc_edac_reg_data reg_data = edac_reg_data[err_type]; 248 + struct qcom_llcc_syn_regs regs = { }; 175 249 int err_cnt, err_ways, ret, i; 176 250 u32 synd_reg, synd_val; 177 251 252 + get_reg_offsets(drv, err_type, &regs); 253 + 178 254 for (i = 0; i < reg_data.reg_cnt; i++) { 179 - synd_reg = reg_data.synd_reg + (i * 4); 255 + synd_reg = regs.synd_reg + (i * 4); 180 256 ret = regmap_read(drv->regmaps[bank], synd_reg, 181 257 &synd_val); 182 258 if (ret) ··· 224 224 reg_data.name, i, synd_val); 225 225 } 226 226 227 - ret = regmap_read(drv->regmaps[bank], reg_data.count_status_reg, 227 + ret = regmap_read(drv->regmaps[bank], regs.count_status_reg, 228 228 &err_cnt); 229 229 if (ret) 230 230 goto clear; ··· 234 234 edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error count: 0x%4x\n", 235 235 reg_data.name, err_cnt); 236 236 237 - ret = regmap_read(drv->regmaps[bank], reg_data.ways_status_reg, 237 + ret = regmap_read(drv->regmaps[bank], regs.ways_status_reg, 238 238 &err_ways); 239 239 if (ret) 240 240 goto clear; ··· 295 295 296 296 /* Iterate over the banks and look for Tag RAM or Data RAM errors */ 297 297 for (i = 0; i < drv->num_banks; i++) { 298 - ret = regmap_read(drv->regmaps[i], DRP_INTERRUPT_STATUS, 298 + ret = regmap_read(drv->regmaps[i], drv->edac_reg_offset->drp_interrupt_status, 299 299 &drp_error); 300 300 301 301 if (!ret && (drp_error & SB_ECC_ERROR)) { ··· 310 310 if (!ret) 311 311 irq_rc = IRQ_HANDLED; 312 312 313 - ret = regmap_read(drv->regmaps[i], TRP_INTERRUPT_0_STATUS, 313 + ret = regmap_read(drv->regmaps[i], drv->edac_reg_offset->trp_interrupt_0_status, 314 314 &trp_error); 315 315 316 316 if (!ret && (trp_error & SB_ECC_ERROR)) { ··· 342 342 int ecc_irq; 343 343 int rc; 344 344 345 - rc = qcom_llcc_core_setup(llcc_driv_data->bcast_regmap); 345 + rc = qcom_llcc_core_setup(llcc_driv_data, llcc_driv_data->bcast_regmap); 346 346 if (rc) 347 347 return rc; 348 348
+1
drivers/firmware/arm_ffa/driver.c
··· 424 424 ep_mem_access->flag = 0; 425 425 ep_mem_access->reserved = 0; 426 426 } 427 + mem_region->handle = 0; 427 428 mem_region->reserved_0 = 0; 428 429 mem_region->reserved_1 = 0; 429 430 mem_region->ep_count = args->nattrs;
+2 -1
drivers/soc/qcom/Makefile
··· 32 32 obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o 33 33 obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o 34 34 obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmon.o 35 - obj-$(CONFIG_QCOM_INLINE_CRYPTO_ENGINE) += ice.o 35 + qcom_ice-objs += ice.o 36 + obj-$(CONFIG_QCOM_INLINE_CRYPTO_ENGINE) += qcom_ice.o
+2 -2
drivers/soc/qcom/icc-bwmon.c
··· 773 773 bwmon->max_bw_kbps = UINT_MAX; 774 774 opp = dev_pm_opp_find_bw_floor(dev, &bwmon->max_bw_kbps, 0); 775 775 if (IS_ERR(opp)) 776 - return dev_err_probe(dev, ret, "failed to find max peak bandwidth\n"); 776 + return dev_err_probe(dev, PTR_ERR(opp), "failed to find max peak bandwidth\n"); 777 777 778 778 bwmon->min_bw_kbps = 0; 779 779 opp = dev_pm_opp_find_bw_ceil(dev, &bwmon->min_bw_kbps, 0); 780 780 if (IS_ERR(opp)) 781 - return dev_err_probe(dev, ret, "failed to find min peak bandwidth\n"); 781 + return dev_err_probe(dev, PTR_ERR(opp), "failed to find min peak bandwidth\n"); 782 782 783 783 bwmon->dev = dev; 784 784
+1 -1
drivers/soc/qcom/ramp_controller.c
··· 296 296 return -ENOMEM; 297 297 298 298 qrc->desc = device_get_match_data(&pdev->dev); 299 - if (!qrc) 299 + if (!qrc->desc) 300 300 return -EINVAL; 301 301 302 302 qrc->regmap = devm_regmap_init_mmio(&pdev->dev, base, &qrc_regmap_config);
+1
drivers/soc/qcom/rmtfs_mem.c
··· 233 233 num_vmids = 0; 234 234 } else if (num_vmids < 0) { 235 235 dev_err(&pdev->dev, "failed to count qcom,vmid elements: %d\n", num_vmids); 236 + ret = num_vmids; 236 237 goto remove_cdev; 237 238 } else if (num_vmids > NUM_MAX_VMIDS) { 238 239 dev_warn(&pdev->dev,
+1 -1
drivers/soc/qcom/rpmh-rsc.c
··· 1073 1073 drv->ver.minor = rsc_id & (MINOR_VER_MASK << MINOR_VER_SHIFT); 1074 1074 drv->ver.minor >>= MINOR_VER_SHIFT; 1075 1075 1076 - if (drv->ver.major == 3 && drv->ver.minor >= 0) 1076 + if (drv->ver.major == 3) 1077 1077 drv->regs = rpmh_rsc_reg_offset_ver_3_0; 1078 1078 else 1079 1079 drv->regs = rpmh_rsc_reg_offset_ver_2_7;
+16
drivers/soc/qcom/rpmhpd.c
··· 342 342 .num_pds = ARRAY_SIZE(sm8150_rpmhpds), 343 343 }; 344 344 345 + static struct rpmhpd *sa8155p_rpmhpds[] = { 346 + [SA8155P_CX] = &cx_w_mx_parent, 347 + [SA8155P_CX_AO] = &cx_ao_w_mx_parent, 348 + [SA8155P_EBI] = &ebi, 349 + [SA8155P_GFX] = &gfx, 350 + [SA8155P_MSS] = &mss, 351 + [SA8155P_MX] = &mx, 352 + [SA8155P_MX_AO] = &mx_ao, 353 + }; 354 + 355 + static const struct rpmhpd_desc sa8155p_desc = { 356 + .rpmhpds = sa8155p_rpmhpds, 357 + .num_pds = ARRAY_SIZE(sa8155p_rpmhpds), 358 + }; 359 + 345 360 /* SM8250 RPMH powerdomains */ 346 361 static struct rpmhpd *sm8250_rpmhpds[] = { 347 362 [SM8250_CX] = &cx_w_mx_parent, ··· 534 519 535 520 static const struct of_device_id rpmhpd_match_table[] = { 536 521 { .compatible = "qcom,qdu1000-rpmhpd", .data = &qdu1000_desc }, 522 + { .compatible = "qcom,sa8155p-rpmhpd", .data = &sa8155p_desc }, 537 523 { .compatible = "qcom,sa8540p-rpmhpd", .data = &sa8540p_desc }, 538 524 { .compatible = "qcom,sa8775p-rpmhpd", .data = &sa8775p_desc }, 539 525 { .compatible = "qcom,sc7180-rpmhpd", .data = &sc7180_desc },
+6 -4
drivers/tee/amdtee/amdtee_if.h
··· 118 118 119 119 /** 120 120 * struct tee_cmd_load_ta - load Trusted Application (TA) binary into TEE 121 - * @low_addr: [in] bits [31:0] of the physical address of the TA binary 122 - * @hi_addr: [in] bits [63:32] of the physical address of the TA binary 123 - * @size: [in] size of TA binary in bytes 124 - * @ta_handle: [out] return handle of the loaded TA 121 + * @low_addr: [in] bits [31:0] of the physical address of the TA binary 122 + * @hi_addr: [in] bits [63:32] of the physical address of the TA binary 123 + * @size: [in] size of TA binary in bytes 124 + * @ta_handle: [out] return handle of the loaded TA 125 + * @return_origin: [out] origin of return code after TEE processing 125 126 */ 126 127 struct tee_cmd_load_ta { 127 128 u32 low_addr; 128 129 u32 hi_addr; 129 130 u32 size; 130 131 u32 ta_handle; 132 + u32 return_origin; 131 133 }; 132 134 133 135 /**
+16 -12
drivers/tee/amdtee/call.c
··· 423 423 if (ret) { 424 424 arg->ret_origin = TEEC_ORIGIN_COMMS; 425 425 arg->ret = TEEC_ERROR_COMMUNICATION; 426 - } else if (arg->ret == TEEC_SUCCESS) { 427 - ret = get_ta_refcount(load_cmd.ta_handle); 428 - if (!ret) { 429 - arg->ret_origin = TEEC_ORIGIN_COMMS; 430 - arg->ret = TEEC_ERROR_OUT_OF_MEMORY; 426 + } else { 427 + arg->ret_origin = load_cmd.return_origin; 431 428 432 - /* Unload the TA on error */ 433 - unload_cmd.ta_handle = load_cmd.ta_handle; 434 - psp_tee_process_cmd(TEE_CMD_ID_UNLOAD_TA, 435 - (void *)&unload_cmd, 436 - sizeof(unload_cmd), &ret); 437 - } else { 438 - set_session_id(load_cmd.ta_handle, 0, &arg->session); 429 + if (arg->ret == TEEC_SUCCESS) { 430 + ret = get_ta_refcount(load_cmd.ta_handle); 431 + if (!ret) { 432 + arg->ret_origin = TEEC_ORIGIN_COMMS; 433 + arg->ret = TEEC_ERROR_OUT_OF_MEMORY; 434 + 435 + /* Unload the TA on error */ 436 + unload_cmd.ta_handle = load_cmd.ta_handle; 437 + psp_tee_process_cmd(TEE_CMD_ID_UNLOAD_TA, 438 + (void *)&unload_cmd, 439 + sizeof(unload_cmd), &ret); 440 + } else { 441 + set_session_id(load_cmd.ta_handle, 0, &arg->session); 442 + } 439 443 } 440 444 } 441 445 mutex_unlock(&ta_refcount_mutex);
+9
include/dt-bindings/power/qcom-rpmpd.h
··· 90 90 #define SM8150_MMCX 9 91 91 #define SM8150_MMCX_AO 10 92 92 93 + /* SA8155P is a special case, kept for backwards compatibility */ 94 + #define SA8155P_CX SM8150_CX 95 + #define SA8155P_CX_AO SM8150_CX_AO 96 + #define SA8155P_EBI SM8150_EBI 97 + #define SA8155P_GFX SM8150_GFX 98 + #define SA8155P_MSS SM8150_MSS 99 + #define SA8155P_MX SM8150_MX 100 + #define SA8155P_MX_AO SM8150_MX_AO 101 + 93 102 /* SM8250 Power Domain Indexes */ 94 103 #define SM8250_CX 0 95 104 #define SM8250_CX_AO 1
-6
include/linux/soc/qcom/llcc-qcom.h
··· 69 69 /** 70 70 * struct llcc_edac_reg_data - llcc edac registers data for each error type 71 71 * @name: Name of the error 72 - * @synd_reg: Syndrome register address 73 - * @count_status_reg: Status register address to read the error count 74 - * @ways_status_reg: Status register address to read the error ways 75 72 * @reg_cnt: Number of registers 76 73 * @count_mask: Mask value to get the error count 77 74 * @ways_mask: Mask value to get the error ways ··· 77 80 */ 78 81 struct llcc_edac_reg_data { 79 82 char *name; 80 - u64 synd_reg; 81 - u64 count_status_reg; 82 - u64 ways_status_reg; 83 83 u32 reg_cnt; 84 84 u32 count_mask; 85 85 u32 ways_mask;