tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/etnaviv: Add PPU flop reset

The PPU flop reset is required on some hardware to clear the
temporary registers. This code follows the implementation
of the PPU flop reset as found in the public galcore kernel
module. Compared to that code some superfluous parts were
removed and only the code path for SoC chip_model = 0x8000
and revision = 0x6205 is implemented and tested.

v2: - Move flop reset data to etnaviv_drm_private and initialize it
from etnaviv_gpu_bind (Lucas)
- Prepare code for more chip IDs and other flop reset types
- Do some cleanups and rename some functions

v3: - Move initialization of flop reset data to etnaviv_gpu_init (Lucas)
- Free PPU data suballocation (Lucas)

v4: As suggested by
- replace "asm-generic/int-ll64.h" with "linux/types.h"
- drop flop reset type enum since we only support one type here
- move function return parameters on same line with function name
- replace open coded for loop with memset32
- add cnost to local static values
- add a return value to etnaviv_flop_reset_ppu_init; handle and
pass errors on to the caller
- handle etnaviv_flop_reset_ppu_init return value
- use dev_err for flop reset error message
- fix include guard to be consistent with the other driver code
- fix license header and formatting

v5: As suggested by Christian Gmeiner:
- add required header that is no longer pulled in by etnaviv_buffer.h
- fix include style of linux headers
- free flop_reset_data_ppu when command buffer initialization fails
- fix typo in error message

[cgmeiner: fix SPDX comment style, fix line end with a '(' and fix typo]

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Tested-by: Marek Vasut <marek.vasut@mailbox.org> # STM32MP255C DHCOS DHSBC
Link: https://patch.msgid.link/20251119164624.9297-5-gert.wollny@collabora.com
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>

authored by

Gert Wollny and committed by
Christian Gmeiner 85ba57ad 9fcdece1

+260
+1
drivers/gpu/drm/etnaviv/Makefile
··· 14 14 etnaviv_iommu.o \ 15 15 etnaviv_mmu.o \ 16 16 etnaviv_perfmon.o \ 17 + etnaviv_flop_reset.o \ 17 18 etnaviv_sched.o 18 19 19 20 obj-$(CONFIG_DRM_ETNAVIV) += etnaviv.o
+6
drivers/gpu/drm/etnaviv/etnaviv_buffer.c
··· 19 19 #include "state_3d.xml.h" 20 20 #include "cmdstream.xml.h" 21 21 22 + #include "etnaviv_flop_reset.h" 23 + 22 24 static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu, 23 25 struct etnaviv_cmdbuf *buffer, u8 pipe) 24 26 { ··· 102 100 103 101 /* initialize buffer */ 104 102 buffer->user_size = 0; 103 + 104 + /* Queue in PPU flop reset */ 105 + if (etnaviv_flop_reset_ppu_require(&gpu->identity)) 106 + etnaviv_flop_reset_ppu_run(gpu); 105 107 106 108 CMD_WAIT(buffer, gpu->fe_waitcycles); 107 109 CMD_LINK(buffer, 2,
+7
drivers/gpu/drm/etnaviv/etnaviv_buffer.h
··· 7 7 #define __ETNAVIV_BUFFER_H__ 8 8 9 9 #include "etnaviv_cmdbuf.h" 10 + #include "etnaviv_gpu.h" 11 + #include "etnaviv_gem.h" 12 + #include "etnaviv_mmu.h" 10 13 11 14 #include "common.xml.h" 15 + #include "linux/printk.h" 12 16 #include "state.xml.h" 17 + #include "state_blt.xml.h" 18 + #include "state_hi.xml.h" 19 + #include "state_3d.xml.h" 13 20 #include "cmdstream.xml.h" 14 21 15 22 static inline void OUT(struct etnaviv_cmdbuf *buffer, u32 data)
+3
drivers/gpu/drm/etnaviv/etnaviv_drv.c
··· 601 601 602 602 component_unbind_all(dev, drm); 603 603 604 + etnaviv_cmdbuf_free(priv->flop_reset_data_ppu); 605 + kfree(priv->flop_reset_data_ppu); 606 + 604 607 etnaviv_cmdbuf_suballoc_destroy(priv->cmdbuf_suballoc); 605 608 606 609 xa_destroy(&priv->active_contexts);
+3
drivers/gpu/drm/etnaviv/etnaviv_drv.h
··· 48 48 /* list of GEM objects: */ 49 49 struct mutex gem_lock; 50 50 struct list_head gem_list; 51 + 52 + /* ppu flop reset data */ 53 + struct etnaviv_cmdbuf *flop_reset_data_ppu; 51 54 }; 52 55 53 56 int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data,
+208
drivers/gpu/drm/etnaviv/etnaviv_flop_reset.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Copyright (C) 2025 Etnaviv Project 4 + */ 5 + 6 + #include <linux/errno.h> 7 + #include <linux/dev_printk.h> 8 + #include <linux/string.h> 9 + #include <linux/types.h> 10 + 11 + #include "etnaviv_buffer.h" 12 + #include "etnaviv_cmdbuf.h" 13 + #include "etnaviv_gpu.h" 14 + #include "state_3d.xml.h" 15 + 16 + #include "etnaviv_flop_reset.h" 17 + 18 + #define PPU_IMAGE_STRIDE 64 19 + #define PPU_IMAGE_XSIZE 64 20 + #define PPU_IMAGE_YSIZE 6 21 + 22 + #define PPU_FLOP_RESET_INSTR_DWORD_COUNT 16 23 + 24 + static void etnaviv_emit_flop_reset_state_ppu(struct etnaviv_cmdbuf *cmdbuf, 25 + u32 buffer_base, u32 input_offset, 26 + u32 output_offset, 27 + u32 shader_offset, 28 + u32 shader_size, 29 + u32 shader_register_count) 30 + { 31 + CMD_LOAD_STATE(cmdbuf, VIVS_GL_API_MODE, VIVS_GL_API_MODE_OPENCL); 32 + CMD_SEM(cmdbuf, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); 33 + CMD_STALL(cmdbuf, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); 34 + 35 + CMD_LOAD_STATES_START(cmdbuf, VIVS_SH_HALTI5_UNIFORMS(0), 4); 36 + 37 + OUT(cmdbuf, buffer_base + input_offset); 38 + OUT(cmdbuf, PPU_IMAGE_STRIDE); 39 + OUT(cmdbuf, PPU_IMAGE_XSIZE | (PPU_IMAGE_YSIZE << 16)); 40 + OUT(cmdbuf, 0x444051f0); 41 + OUT(cmdbuf, 0xffffffff); 42 + 43 + CMD_LOAD_STATES_START(cmdbuf, VIVS_SH_HALTI5_UNIFORMS(4), 4); 44 + OUT(cmdbuf, buffer_base + output_offset); 45 + OUT(cmdbuf, PPU_IMAGE_STRIDE); 46 + OUT(cmdbuf, PPU_IMAGE_XSIZE | (PPU_IMAGE_YSIZE << 16)); 47 + OUT(cmdbuf, 0x444051f0); 48 + OUT(cmdbuf, 0xffffffff); 49 + 50 + CMD_LOAD_STATE(cmdbuf, VIVS_CL_CONFIG, 51 + VIVS_CL_CONFIG_DIMENSIONS(2) | 52 + VIVS_CL_CONFIG_VALUE_ORDER(3)); 53 + CMD_LOAD_STATE(cmdbuf, VIVS_VS_ICACHE_INVALIDATE, 0x1f); 54 + CMD_LOAD_STATE(cmdbuf, VIVS_PS_VARYING_NUM_COMPONENTS(0), 0); 55 + CMD_LOAD_STATE(cmdbuf, VIVS_PS_TEMP_REGISTER_CONTROL, 56 + shader_register_count); 57 + CMD_LOAD_STATE(cmdbuf, VIVS_PS_SAMPLER_BASE, 0x0); 58 + CMD_LOAD_STATE(cmdbuf, VIVS_PS_UNIFORM_BASE, 0x0); 59 + CMD_LOAD_STATE(cmdbuf, VIVS_PS_NEWRANGE_LOW, 0x0); 60 + CMD_LOAD_STATE(cmdbuf, VIVS_PS_NEWRANGE_HIGH, shader_size / 16); 61 + CMD_LOAD_STATE(cmdbuf, VIVS_PS_INST_ADDR, buffer_base + shader_offset); 62 + CMD_LOAD_STATE(cmdbuf, VIVS_SH_CONFIG, VIVS_SH_CONFIG_RTNE_ROUNDING); 63 + CMD_LOAD_STATE(cmdbuf, VIVS_VS_ICACHE_CONTROL, 64 + VIVS_VS_ICACHE_CONTROL_ENABLE); 65 + CMD_LOAD_STATE(cmdbuf, VIVS_PS_ICACHE_COUNT, shader_size / 16 - 1); 66 + CMD_LOAD_STATE(cmdbuf, VIVS_PS_INPUT_COUNT, 0x1f01); 67 + CMD_LOAD_STATE(cmdbuf, VIVS_VS_HALTI5_UNK008A0, 0x0); 68 + CMD_LOAD_STATE(cmdbuf, VIVS_PA_VS_OUTPUT_COUNT, 0x0); 69 + CMD_LOAD_STATE(cmdbuf, VIVS_GL_VARYING_TOTAL_COMPONENTS, 0x0); 70 + CMD_LOAD_STATE(cmdbuf, VIVS_PS_CONTROL_EXT, 0x0); 71 + CMD_LOAD_STATE(cmdbuf, VIVS_VS_OUTPUT_COUNT, 0x1); 72 + CMD_LOAD_STATE(cmdbuf, VIVS_GL_HALTI5_SH_SPECIALS, 0x0); 73 + CMD_LOAD_STATE(cmdbuf, VIVS_PS_ICACHE_PREFETCH, 0x0); 74 + CMD_LOAD_STATE(cmdbuf, VIVS_CL_UNK00924, 0x0); 75 + CMD_LOAD_STATE(cmdbuf, VIVS_CL_THREAD_ALLOCATION, 0x1); 76 + 77 + CMD_LOAD_STATE(cmdbuf, VIVS_CL_GLOBAL_WORK_OFFSET_X, 0x0); 78 + CMD_LOAD_STATE(cmdbuf, VIVS_CL_GLOBAL_WORK_OFFSET_Y, 0x0); 79 + CMD_LOAD_STATE(cmdbuf, VIVS_CL_GLOBAL_WORK_OFFSET_Z, 0x0); 80 + 81 + CMD_LOAD_STATES_START(cmdbuf, VIVS_CL_WORKGROUP_COUNT_X, 9); 82 + OUT(cmdbuf, 0xf); 83 + OUT(cmdbuf, 0x5); 84 + OUT(cmdbuf, 0xffffffff); 85 + OUT(cmdbuf, 0x0); 86 + OUT(cmdbuf, 0x0); 87 + OUT(cmdbuf, 0x3ff); 88 + OUT(cmdbuf, 0x0); 89 + OUT(cmdbuf, 0x4); 90 + OUT(cmdbuf, 0x1); 91 + OUT(cmdbuf, 0x0); 92 + 93 + CMD_LOAD_STATE(cmdbuf, VIVS_CL_KICKER, 0xbadabeeb); 94 + CMD_LOAD_STATE(cmdbuf, VIVS_GL_FLUSH_CACHE, 95 + VIVS_GL_FLUSH_CACHE_SHADER_L1 | 96 + VIVS_GL_FLUSH_CACHE_UNK10 | 97 + VIVS_GL_FLUSH_CACHE_UNK11); 98 + } 99 + 100 + static void etnaviv_flop_reset_ppu_fill_input(u32 *buffer, u32 size) 101 + { 102 + memset32(buffer, 0x01010101, size / 4); 103 + } 104 + 105 + static void etnaviv_flop_reset_ppu_set_shader(u8 *dest) 106 + { 107 + static const u32 inst[PPU_FLOP_RESET_INSTR_DWORD_COUNT] = { 108 + /* img_load.u8 r1, c0, r0.xy */ 109 + 0x78011779, 110 + 0x39000804, 111 + 0x00A90050, 112 + 0x00000000, 113 + /* img_load.u8 r2, c0, r0.xy */ 114 + 0x78021779, 115 + 0x39000804, 116 + 0x00A90050, 117 + 0x00000000, 118 + /* dp2x8 r1, r1, r2, c3_512 */ 119 + 0xB8017145, 120 + 0x390018FC, 121 + 0x01C90140, 122 + 0x40390028, 123 + /* img_store.u8 r1, c2, r0.xy, r1 */ 124 + 0x380007BA, 125 + 0x39001804, 126 + 0x00A90050, 127 + 0x00390018, 128 + }; 129 + memcpy(dest, inst, sizeof(inst)); 130 + } 131 + 132 + static const struct etnaviv_flop_reset_entry { 133 + u16 chip_model; 134 + u16 revision; 135 + u32 flags; 136 + } etnaviv_flop_reset_db[] = { 137 + { 138 + .chip_model = 0x8000, 139 + .revision = 0x6205, 140 + }, 141 + }; 142 + 143 + bool etnaviv_flop_reset_ppu_require(const struct etnaviv_chip_identity *chip_id) 144 + { 145 + const struct etnaviv_flop_reset_entry *e = etnaviv_flop_reset_db; 146 + 147 + for (int i = 0; i < ARRAY_SIZE(etnaviv_flop_reset_db); ++i, ++e) { 148 + if (chip_id->model == e->chip_model && 149 + chip_id->revision == e->revision) 150 + return true; 151 + } 152 + 153 + return false; 154 + } 155 + 156 + static const u32 image_data_size = PPU_IMAGE_STRIDE * PPU_IMAGE_YSIZE; 157 + static const u32 output_offset = ALIGN(image_data_size, 64); 158 + static const u32 shader_offset = ALIGN(output_offset + image_data_size, 64); 159 + static const u32 shader_size = PPU_FLOP_RESET_INSTR_DWORD_COUNT * sizeof(u32); 160 + static const u32 shader_register_count = 3; 161 + static const u32 buffer_size = shader_offset + shader_size; 162 + 163 + int etnaviv_flop_reset_ppu_init(struct etnaviv_drm_private *priv) 164 + { 165 + /* Get some space from the ring buffer to put the payload 166 + * (input and output image, and shader), we keep this buffer 167 + * for the whole life time the driver is bound 168 + */ 169 + priv->flop_reset_data_ppu = 170 + kzalloc(sizeof(*priv->flop_reset_data_ppu), GFP_KERNEL); 171 + 172 + if (!priv->flop_reset_data_ppu) 173 + return -ENOMEM; 174 + 175 + int ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, 176 + priv->flop_reset_data_ppu, buffer_size); 177 + if (ret) { 178 + kfree(priv->flop_reset_data_ppu); 179 + return ret; 180 + } 181 + 182 + void *buffer_base = priv->flop_reset_data_ppu->vaddr; 183 + u32 *input_data = (u32 *)buffer_base; 184 + u8 *shader_data = (u8 *)buffer_base + shader_offset; 185 + 186 + etnaviv_flop_reset_ppu_fill_input(input_data, image_data_size); 187 + etnaviv_flop_reset_ppu_set_shader(shader_data); 188 + 189 + return 0; 190 + } 191 + 192 + void etnaviv_flop_reset_ppu_run(struct etnaviv_gpu *gpu) 193 + { 194 + struct etnaviv_drm_private *priv = gpu->drm->dev_private; 195 + 196 + if (!priv->flop_reset_data_ppu) { 197 + dev_err(gpu->dev, 198 + "Oops: Flop reset data was not initialized, skipping\n"); 199 + return; 200 + } 201 + 202 + u32 buffer_base = etnaviv_cmdbuf_get_va(priv->flop_reset_data_ppu, 203 + &gpu->mmu_context->cmdbuf_mapping); 204 + 205 + etnaviv_emit_flop_reset_state_ppu(&gpu->buffer, buffer_base, 0, 206 + output_offset, shader_offset, 207 + shader_size, shader_register_count); 208 + }
+21
drivers/gpu/drm/etnaviv/etnaviv_flop_reset.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 2 + * 3 + * Copyright (C) 2025 Etnaviv Project 4 + */ 5 + 6 + #ifndef _ETNAVIV_FLOP_RESET_H_ 7 + #define _ETNAVIV_FLOP_RESET_H_ 8 + 9 + #include <linux/types.h> 10 + 11 + struct etnaviv_chip_identity; 12 + struct etnaviv_drm_private; 13 + struct etnaviv_gpu; 14 + 15 + bool etnaviv_flop_reset_ppu_require(const struct etnaviv_chip_identity *chip_id); 16 + 17 + int etnaviv_flop_reset_ppu_init(struct etnaviv_drm_private *priv); 18 + 19 + void etnaviv_flop_reset_ppu_run(struct etnaviv_gpu *gpu); 20 + 21 + #endif
+11
drivers/gpu/drm/etnaviv/etnaviv_gpu.c
··· 20 20 21 21 #include "etnaviv_cmdbuf.h" 22 22 #include "etnaviv_dump.h" 23 + #include "etnaviv_flop_reset.h" 23 24 #include "etnaviv_gpu.h" 24 25 #include "etnaviv_gem.h" 25 26 #include "etnaviv_mmu.h" ··· 838 837 dev_err(gpu->dev, "Unknown GPU model\n"); 839 838 ret = -ENXIO; 840 839 goto fail; 840 + } 841 + 842 + if (etnaviv_flop_reset_ppu_require(&gpu->identity) && 843 + !priv->flop_reset_data_ppu) { 844 + ret = etnaviv_flop_reset_ppu_init(priv); 845 + if (ret) { 846 + dev_err(gpu->dev, 847 + "Unable to initialize PPU flop reset data\n"); 848 + goto fail; 849 + } 841 850 } 842 851 843 852 if (gpu->identity.nn_core_count > 0)