Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Nothing too scary, we have one outstanding i915 regression but Daniel
has promised the fix as soon as he's finished testing it a bit.
Fixes for the main x86 drivers:
- radeon: dpm fixes, displayport regression fix
- i915: quirks for backlight regression, edp reboot fix, valleyview
black screen fixes
- nouveau: display port regression fixes, fix for memory reclocking"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/radeon/dpm: Reenabling SS on Cayman
drm/radeon: fix typo in ci_stop_dpm()
drm/radeon: fix typo in golden register setup on evergreen
drm/radeon: only print meaningful VM faults
drm/radeon/dp: return -EIO for flags not zero case
drm/i915/vlv: T12 eDP panel timing enforcement during reboot
drm/i915: Only unbind vgacon, not other console drivers
drm/i915: Don't clobber the GTT when it's within stolen memory
drm/i915/vlv: Update the DSI ULPS entry/exit sequence
drm/i915/vlv: DPI FIFO empty check is not needed
drm/i915: Toshiba CB35 has a controllable backlight
drm/i915: Acer C720 and C720P have controllable backlights
drm/i915: quirk asserts controllable backlight presence, overriding VBT
drm/nouveau/ram: fix test for gpio presence
drm/nouveau/dp: workaround broken display
drm/nouveau/dp: fix required link bandwidth calculations
drm/nouveau/kms: restore fbcon after display has been resumed
drm/nv50-/kms: pass a non-zero value for head to sor dpms methods
drm/nouveau/fb: Prevent inlining of ramfuc_reg
drm/gk104/ram: bash mpll bit 31 on
+177
-73
+3
-2
drivers/gpu/drm/i915/i915_dma.c
+3
-2
drivers/gpu/drm/i915/i915_dma.c
···
1464
1464
#else
1465
1465
static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1466
1466
{
1467
-
int ret;
1467
+
int ret = 0;
1468
1468
1469
1469
DRM_INFO("Replacing VGA console driver\n");
1470
1470
1471
1471
console_lock();
1472
-
ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
1472
+
if (con_is_bound(&vga_con))
1473
+
ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
1473
1474
if (ret == 0) {
1474
1475
ret = do_unregister_con_driver(&vga_con);
1475
1476
+1
drivers/gpu/drm/i915/i915_drv.h
+1
drivers/gpu/drm/i915/i915_drv.h
+44
drivers/gpu/drm/i915/i915_gem_stolen.c
+44
drivers/gpu/drm/i915/i915_gem_stolen.c
···
74
74
if (base == 0)
75
75
return 0;
76
76
77
+
/* make sure we don't clobber the GTT if it's within stolen memory */
78
+
if (INTEL_INFO(dev)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) {
79
+
struct {
80
+
u32 start, end;
81
+
} stolen[2] = {
82
+
{ .start = base, .end = base + dev_priv->gtt.stolen_size, },
83
+
{ .start = base, .end = base + dev_priv->gtt.stolen_size, },
84
+
};
85
+
u64 gtt_start, gtt_end;
86
+
87
+
gtt_start = I915_READ(PGTBL_CTL);
88
+
if (IS_GEN4(dev))
89
+
gtt_start = (gtt_start & PGTBL_ADDRESS_LO_MASK) |
90
+
(gtt_start & PGTBL_ADDRESS_HI_MASK) << 28;
91
+
else
92
+
gtt_start &= PGTBL_ADDRESS_LO_MASK;
93
+
gtt_end = gtt_start + gtt_total_entries(dev_priv->gtt) * 4;
94
+
95
+
if (gtt_start >= stolen[0].start && gtt_start < stolen[0].end)
96
+
stolen[0].end = gtt_start;
97
+
if (gtt_end > stolen[1].start && gtt_end <= stolen[1].end)
98
+
stolen[1].start = gtt_end;
99
+
100
+
/* pick the larger of the two chunks */
101
+
if (stolen[0].end - stolen[0].start >
102
+
stolen[1].end - stolen[1].start) {
103
+
base = stolen[0].start;
104
+
dev_priv->gtt.stolen_size = stolen[0].end - stolen[0].start;
105
+
} else {
106
+
base = stolen[1].start;
107
+
dev_priv->gtt.stolen_size = stolen[1].end - stolen[1].start;
108
+
}
109
+
110
+
if (stolen[0].start != stolen[1].start ||
111
+
stolen[0].end != stolen[1].end) {
112
+
DRM_DEBUG_KMS("GTT within stolen memory at 0x%llx-0x%llx\n",
113
+
(unsigned long long) gtt_start,
114
+
(unsigned long long) gtt_end - 1);
115
+
DRM_DEBUG_KMS("Stolen memory adjusted to 0x%x-0x%x\n",
116
+
base, base + (u32) dev_priv->gtt.stolen_size - 1);
117
+
}
118
+
}
119
+
120
+
77
121
/* Verify that nothing else uses this physical address. Stolen
78
122
* memory should be reserved by the BIOS and hidden from the
79
123
* kernel. So if the region is already marked as busy, something
+3
drivers/gpu/drm/i915/i915_reg.h
+3
drivers/gpu/drm/i915/i915_reg.h
···
942
942
/*
943
943
* Instruction and interrupt control regs
944
944
*/
945
+
#define PGTBL_CTL 0x02020
946
+
#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
947
+
#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
945
948
#define PGTBL_ER 0x02024
946
949
#define RENDER_RING_BASE 0x02000
947
950
#define BSD_RING_BASE 0x04000
+14
drivers/gpu/drm/i915/intel_display.c
+14
drivers/gpu/drm/i915/intel_display.c
···
11591
11591
DRM_INFO("applying inverted panel brightness quirk\n");
11592
11592
}
11593
11593
11594
+
/* Some VBT's incorrectly indicate no backlight is present */
11595
+
static void quirk_backlight_present(struct drm_device *dev)
11596
+
{
11597
+
struct drm_i915_private *dev_priv = dev->dev_private;
11598
+
dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
11599
+
DRM_INFO("applying backlight present quirk\n");
11600
+
}
11601
+
11594
11602
struct intel_quirk {
11595
11603
int device;
11596
11604
int subsystem_vendor;
···
11667
11659
11668
11660
/* Acer Aspire 5336 */
11669
11661
{ 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11662
+
11663
+
/* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
11664
+
{ 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
11665
+
11666
+
/* Toshiba CB35 Chromebook (Celeron 2955U) */
11667
+
{ 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
11670
11668
};
11671
11669
11672
11670
static void intel_init_quirks(struct drm_device *dev)
+42
drivers/gpu/drm/i915/intel_dp.c
+42
drivers/gpu/drm/i915/intel_dp.c
···
28
28
#include <linux/i2c.h>
29
29
#include <linux/slab.h>
30
30
#include <linux/export.h>
31
+
#include <linux/notifier.h>
32
+
#include <linux/reboot.h>
31
33
#include <drm/drmP.h>
32
34
#include <drm/drm_crtc.h>
33
35
#include <drm/drm_crtc_helper.h>
···
336
334
return PCH_PP_STATUS;
337
335
else
338
336
return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
337
+
}
338
+
339
+
/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
340
+
This function only applicable when panel PM state is not to be tracked */
341
+
static int edp_notify_handler(struct notifier_block *this, unsigned long code,
342
+
void *unused)
343
+
{
344
+
struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
345
+
edp_notifier);
346
+
struct drm_device *dev = intel_dp_to_dev(intel_dp);
347
+
struct drm_i915_private *dev_priv = dev->dev_private;
348
+
u32 pp_div;
349
+
u32 pp_ctrl_reg, pp_div_reg;
350
+
enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
351
+
352
+
if (!is_edp(intel_dp) || code != SYS_RESTART)
353
+
return 0;
354
+
355
+
if (IS_VALLEYVIEW(dev)) {
356
+
pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
357
+
pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
358
+
pp_div = I915_READ(pp_div_reg);
359
+
pp_div &= PP_REFERENCE_DIVIDER_MASK;
360
+
361
+
/* 0x1F write to PP_DIV_REG sets max cycle delay */
362
+
I915_WRITE(pp_div_reg, pp_div | 0x1F);
363
+
I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
364
+
msleep(intel_dp->panel_power_cycle_delay);
365
+
}
366
+
367
+
return 0;
339
368
}
340
369
341
370
static bool edp_have_panel_power(struct intel_dp *intel_dp)
···
3740
3707
drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
3741
3708
edp_panel_vdd_off_sync(intel_dp);
3742
3709
drm_modeset_unlock(&dev->mode_config.connection_mutex);
3710
+
if (intel_dp->edp_notifier.notifier_call) {
3711
+
unregister_reboot_notifier(&intel_dp->edp_notifier);
3712
+
intel_dp->edp_notifier.notifier_call = NULL;
3713
+
}
3743
3714
}
3744
3715
kfree(intel_dig_port);
3745
3716
}
···
4220
4183
fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4221
4184
}
4222
4185
mutex_unlock(&dev->mode_config.mutex);
4186
+
4187
+
if (IS_VALLEYVIEW(dev)) {
4188
+
intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4189
+
register_reboot_notifier(&intel_dp->edp_notifier);
4190
+
}
4223
4191
4224
4192
intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4225
4193
intel_panel_setup_backlight(connector);
+2
drivers/gpu/drm/i915/intel_drv.h
+2
drivers/gpu/drm/i915/intel_drv.h
+15
-14
drivers/gpu/drm/i915/intel_dsi.c
+15
-14
drivers/gpu/drm/i915/intel_dsi.c
···
117
117
/* bandgap reset is needed after everytime we do power gate */
118
118
band_gap_reset(dev_priv);
119
119
120
+
I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
121
+
usleep_range(2500, 3000);
122
+
120
123
val = I915_READ(MIPI_PORT_CTRL(pipe));
121
124
I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD);
122
125
usleep_range(1000, 1500);
123
-
I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
124
-
usleep_range(2000, 2500);
126
+
127
+
I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
128
+
usleep_range(2500, 3000);
129
+
125
130
I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
126
-
usleep_range(2000, 2500);
127
-
I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
128
-
usleep_range(2000, 2500);
129
-
I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
130
-
usleep_range(2000, 2500);
131
+
usleep_range(2500, 3000);
131
132
}
132
133
133
134
static void intel_dsi_enable(struct intel_encoder *encoder)
···
272
271
273
272
DRM_DEBUG_KMS("\n");
274
273
275
-
I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
274
+
I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER);
276
275
usleep_range(2000, 2500);
277
276
278
-
I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
277
+
I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
279
278
usleep_range(2000, 2500);
280
279
281
-
I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
280
+
I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER);
282
281
usleep_range(2000, 2500);
283
-
284
-
val = I915_READ(MIPI_PORT_CTRL(pipe));
285
-
I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
286
-
usleep_range(1000, 1500);
287
282
288
283
if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT)
289
284
== 0x00000), 30))
290
285
DRM_ERROR("DSI LP not going Low\n");
286
+
287
+
val = I915_READ(MIPI_PORT_CTRL(pipe));
288
+
I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
289
+
usleep_range(1000, 1500);
291
290
292
291
I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
293
292
usleep_range(2000, 2500);
-6
drivers/gpu/drm/i915/intel_dsi_cmd.c
-6
drivers/gpu/drm/i915/intel_dsi_cmd.c
···
404
404
else
405
405
cmd |= DPI_LP_MODE;
406
406
407
-
/* DPI virtual channel?! */
408
-
409
-
mask = DPI_FIFO_EMPTY;
410
-
if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50))
411
-
DRM_ERROR("Timeout waiting for DPI FIFO empty.\n");
412
-
413
407
/* clear bit */
414
408
I915_WRITE(MIPI_INTR_STAT(pipe), SPL_PKT_SENT_INTERRUPT);
415
409
+6
-2
drivers/gpu/drm/i915/intel_panel.c
+6
-2
drivers/gpu/drm/i915/intel_panel.c
···
1118
1118
int ret;
1119
1119
1120
1120
if (!dev_priv->vbt.backlight.present) {
1121
-
DRM_DEBUG_KMS("native backlight control not available per VBT\n");
1122
-
return 0;
1121
+
if (dev_priv->quirks & QUIRK_BACKLIGHT_PRESENT) {
1122
+
DRM_DEBUG_KMS("no backlight present per VBT, but present per quirk\n");
1123
+
} else {
1124
+
DRM_DEBUG_KMS("no backlight present per VBT\n");
1125
+
return 0;
1126
+
}
1123
1127
}
1124
1128
1125
1129
/* set level and max in panel struct */
+3
-3
drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+3
-3
drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
···
1516
1516
}
1517
1517
1518
1518
switch ((ctrl & 0x000f0000) >> 16) {
1519
-
case 6: datarate = pclk * 30 / 8; break;
1520
-
case 5: datarate = pclk * 24 / 8; break;
1519
+
case 6: datarate = pclk * 30; break;
1520
+
case 5: datarate = pclk * 24; break;
1521
1521
case 2:
1522
1522
default:
1523
-
datarate = pclk * 18 / 8;
1523
+
datarate = pclk * 18;
1524
1524
break;
1525
1525
}
1526
1526
+3
-3
drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
+3
-3
drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
···
1159
1159
if (outp->info.type == DCB_OUTPUT_DP) {
1160
1160
u32 sync = nv_rd32(priv, 0x660404 + (head * 0x300));
1161
1161
switch ((sync & 0x000003c0) >> 6) {
1162
-
case 6: pclk = pclk * 30 / 8; break;
1163
-
case 5: pclk = pclk * 24 / 8; break;
1162
+
case 6: pclk = pclk * 30; break;
1163
+
case 5: pclk = pclk * 24; break;
1164
1164
case 2:
1165
1165
default:
1166
-
pclk = pclk * 18 / 8;
1166
+
pclk = pclk * 18;
1167
1167
break;
1168
1168
}
1169
1169
+5
-3
drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c
+5
-3
drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c
···
34
34
struct nvkm_output_dp *outp = (void *)base;
35
35
bool retrain = true;
36
36
u8 link[2], stat[3];
37
-
u32 rate;
37
+
u32 linkrate;
38
38
int ret, i;
39
39
40
40
/* check that the link is trained at a high enough rate */
···
44
44
goto done;
45
45
}
46
46
47
-
rate = link[0] * 27000 * (link[1] & DPCD_LC01_LANE_COUNT_SET);
48
-
if (rate < ((datarate / 8) * 10)) {
47
+
linkrate = link[0] * 27000 * (link[1] & DPCD_LC01_LANE_COUNT_SET);
48
+
linkrate = (linkrate * 8) / 10; /* 8B/10B coding overhead */
49
+
datarate = (datarate + 9) / 10; /* -> decakilobits */
50
+
if (linkrate < datarate) {
49
51
DBG("link not trained at sufficient rate\n");
50
52
goto done;
51
53
}
+1
drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
+1
drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
+2
-2
drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h
+2
-2
drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h
···
26
26
};
27
27
}
28
28
29
-
static inline struct ramfuc_reg
29
+
static noinline struct ramfuc_reg
30
30
ramfuc_reg(u32 addr)
31
31
{
32
32
return ramfuc_reg2(addr, addr);
···
107
107
108
108
#define ram_init(s,p) ramfuc_init(&(s)->base, (p))
109
109
#define ram_exec(s,e) ramfuc_exec(&(s)->base, (e))
110
-
#define ram_have(s,r) ((s)->r_##r.addr != 0x000000)
110
+
#define ram_have(s,r) ((s)->r_##r.addr[0] != 0x000000)
111
111
#define ram_rd32(s,r) ramfuc_rd32(&(s)->base, &(s)->r_##r)
112
112
#define ram_wr32(s,r,d) ramfuc_wr32(&(s)->base, &(s)->r_##r, (d))
113
113
#define ram_nuke(s,r) ramfuc_nuke(&(s)->base, &(s)->r_##r)
+1
drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
+1
drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
···
200
200
/* (re)program mempll, if required */
201
201
if (ram->mode == 2) {
202
202
ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
203
+
ram_mask(fuc, 0x132000, 0x80000000, 0x80000000);
203
204
ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
204
205
ram_mask(fuc, 0x132004, 0x103fffff, mcoef);
205
206
ram_mask(fuc, 0x132000, 0x00000001, 0x00000001);
+9
-8
drivers/gpu/drm/nouveau/nouveau_drm.c
+9
-8
drivers/gpu/drm/nouveau/nouveau_drm.c
···
652
652
ret = nouveau_do_resume(drm_dev);
653
653
if (ret)
654
654
return ret;
655
-
if (drm_dev->mode_config.num_crtc)
656
-
nouveau_fbcon_set_suspend(drm_dev, 0);
657
655
658
-
nouveau_fbcon_zfill_all(drm_dev);
659
-
if (drm_dev->mode_config.num_crtc)
656
+
if (drm_dev->mode_config.num_crtc) {
660
657
nouveau_display_resume(drm_dev);
658
+
nouveau_fbcon_set_suspend(drm_dev, 0);
659
+
}
660
+
661
661
return 0;
662
662
}
663
663
···
683
683
ret = nouveau_do_resume(drm_dev);
684
684
if (ret)
685
685
return ret;
686
-
if (drm_dev->mode_config.num_crtc)
687
-
nouveau_fbcon_set_suspend(drm_dev, 0);
688
-
nouveau_fbcon_zfill_all(drm_dev);
689
-
if (drm_dev->mode_config.num_crtc)
686
+
687
+
if (drm_dev->mode_config.num_crtc) {
690
688
nouveau_display_resume(drm_dev);
689
+
nouveau_fbcon_set_suspend(drm_dev, 0);
690
+
}
691
+
691
692
return 0;
692
693
}
693
694
+3
-10
drivers/gpu/drm/nouveau/nouveau_fbcon.c
+3
-10
drivers/gpu/drm/nouveau/nouveau_fbcon.c
···
531
531
if (state == 1)
532
532
nouveau_fbcon_save_disable_accel(dev);
533
533
fb_set_suspend(drm->fbcon->helper.fbdev, state);
534
-
if (state == 0)
534
+
if (state == 0) {
535
535
nouveau_fbcon_restore_accel(dev);
536
+
nouveau_fbcon_zfill(dev, drm->fbcon);
537
+
}
536
538
console_unlock();
537
-
}
538
-
}
539
-
540
-
void
541
-
nouveau_fbcon_zfill_all(struct drm_device *dev)
542
-
{
543
-
struct nouveau_drm *drm = nouveau_drm(dev);
544
-
if (drm->fbcon) {
545
-
nouveau_fbcon_zfill(dev, drm->fbcon);
546
539
}
547
540
}
-1
drivers/gpu/drm/nouveau/nouveau_fbcon.h
-1
drivers/gpu/drm/nouveau/nouveau_fbcon.h
···
61
61
int nouveau_fbcon_init(struct drm_device *dev);
62
62
void nouveau_fbcon_fini(struct drm_device *dev);
63
63
void nouveau_fbcon_set_suspend(struct drm_device *dev, int state);
64
-
void nouveau_fbcon_zfill_all(struct drm_device *dev);
65
64
void nouveau_fbcon_save_disable_accel(struct drm_device *dev);
66
65
void nouveau_fbcon_restore_accel(struct drm_device *dev);
67
66
+2
-1
drivers/gpu/drm/nouveau/nv50_display.c
+2
-1
drivers/gpu/drm/nouveau/nv50_display.c
···
1741
1741
}
1742
1742
}
1743
1743
1744
-
mthd = (ffs(nv_encoder->dcb->sorconf.link) - 1) << 2;
1744
+
mthd = (ffs(nv_encoder->dcb->heads) - 1) << 3;
1745
+
mthd |= (ffs(nv_encoder->dcb->sorconf.link) - 1) << 2;
1745
1746
mthd |= nv_encoder->or;
1746
1747
1747
1748
if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
+1
-1
drivers/gpu/drm/radeon/atombios_dp.c
+1
-1
drivers/gpu/drm/radeon/atombios_dp.c
+1
-1
drivers/gpu/drm/radeon/ci_dpm.c
+1
-1
drivers/gpu/drm/radeon/ci_dpm.c
+4
-2
drivers/gpu/drm/radeon/cik.c
+4
-2
drivers/gpu/drm/radeon/cik.c
···
7676
7676
addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
7677
7677
status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
7678
7678
mc_client = RREG32(VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
7679
+
/* reset addr and status */
7680
+
WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
7681
+
if (addr == 0x0 && status == 0x0)
7682
+
break;
7679
7683
dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
7680
7684
dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
7681
7685
addr);
7682
7686
dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
7683
7687
status);
7684
7688
cik_vm_decode_fault(rdev, status, addr, mc_client);
7685
-
/* reset addr and status */
7686
-
WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
7687
7689
break;
7688
7690
case 167: /* VCE */
7689
7691
DRM_DEBUG("IH: VCE int: 0x%08x\n", src_data);
+8
-6
drivers/gpu/drm/radeon/evergreen.c
+8
-6
drivers/gpu/drm/radeon/evergreen.c
···
189
189
0x8c1c, 0xffffffff, 0x00001010,
190
190
0x28350, 0xffffffff, 0x00000000,
191
191
0xa008, 0xffffffff, 0x00010000,
192
-
0x5cc, 0xffffffff, 0x00000001,
192
+
0x5c4, 0xffffffff, 0x00000001,
193
193
0x9508, 0xffffffff, 0x00000002,
194
194
0x913c, 0x0000000f, 0x0000000a
195
195
};
···
476
476
0x8c1c, 0xffffffff, 0x00001010,
477
477
0x28350, 0xffffffff, 0x00000000,
478
478
0xa008, 0xffffffff, 0x00010000,
479
-
0x5cc, 0xffffffff, 0x00000001,
479
+
0x5c4, 0xffffffff, 0x00000001,
480
480
0x9508, 0xffffffff, 0x00000002
481
481
};
482
482
···
635
635
static const u32 supersumo_golden_registers[] =
636
636
{
637
637
0x5eb4, 0xffffffff, 0x00000002,
638
-
0x5cc, 0xffffffff, 0x00000001,
638
+
0x5c4, 0xffffffff, 0x00000001,
639
639
0x7030, 0xffffffff, 0x00000011,
640
640
0x7c30, 0xffffffff, 0x00000011,
641
641
0x6104, 0x01000300, 0x00000000,
···
719
719
static const u32 wrestler_golden_registers[] =
720
720
{
721
721
0x5eb4, 0xffffffff, 0x00000002,
722
-
0x5cc, 0xffffffff, 0x00000001,
722
+
0x5c4, 0xffffffff, 0x00000001,
723
723
0x7030, 0xffffffff, 0x00000011,
724
724
0x7c30, 0xffffffff, 0x00000011,
725
725
0x6104, 0x01000300, 0x00000000,
···
5066
5066
case 147:
5067
5067
addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
5068
5068
status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
5069
+
/* reset addr and status */
5070
+
WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
5071
+
if (addr == 0x0 && status == 0x0)
5072
+
break;
5069
5073
dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
5070
5074
dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
5071
5075
addr);
5072
5076
dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
5073
5077
status);
5074
5078
cayman_vm_decode_fault(rdev, status, addr);
5075
-
/* reset addr and status */
5076
-
WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
5077
5079
break;
5078
5080
case 176: /* CP_INT in ring buffer */
5079
5081
case 177: /* CP_INT in IB1 */
-6
drivers/gpu/drm/radeon/rv770_dpm.c
-6
drivers/gpu/drm/radeon/rv770_dpm.c
···
2329
2329
pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
2330
2330
ASIC_INTERNAL_MEMORY_SS, 0);
2331
2331
2332
-
/* disable ss, causes hangs on some cayman boards */
2333
-
if (rdev->family == CHIP_CAYMAN) {
2334
-
pi->sclk_ss = false;
2335
-
pi->mclk_ss = false;
2336
-
}
2337
-
2338
2332
if (pi->sclk_ss || pi->mclk_ss)
2339
2333
pi->dynamic_ss = true;
2340
2334
else
+4
-2
drivers/gpu/drm/radeon/si.c
+4
-2
drivers/gpu/drm/radeon/si.c
···
6376
6376
case 147:
6377
6377
addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
6378
6378
status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
6379
+
/* reset addr and status */
6380
+
WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
6381
+
if (addr == 0x0 && status == 0x0)
6382
+
break;
6379
6383
dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
6380
6384
dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
6381
6385
addr);
6382
6386
dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
6383
6387
status);
6384
6388
si_vm_decode_fault(rdev, status, addr);
6385
-
/* reset addr and status */
6386
-
WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
6387
6389
break;
6388
6390
case 176: /* RINGID0 CP_INT */
6389
6391
radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);