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RISC-V: KVM: Move copy_sbi_ext_reg_indices() to SBI implementation

The ONE_REG handling of SBI extension enable/disable registers and
SBI extension state registers is already under SBI implementation.
On similar lines, let's move copy_sbi_ext_reg_indices() under SBI
implementation.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20250823155947.1354229-5-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>

authored by

Anup Patel and committed by
Anup Patel 85e7850e 699a53ae

+29 -29
+1 -1
arch/riscv/include/asm/kvm_vcpu_sbi.h
··· 77 77 unsigned long pc, unsigned long a1); 78 78 void kvm_riscv_vcpu_sbi_load_reset_state(struct kvm_vcpu *vcpu); 79 79 int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run); 80 + int kvm_riscv_vcpu_reg_indices_sbi_ext(struct kvm_vcpu *vcpu, u64 __user *uindices); 80 81 int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu, 81 82 const struct kvm_one_reg *reg); 82 83 int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu, ··· 87 86 int kvm_riscv_vcpu_get_reg_sbi(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 88 87 const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext( 89 88 struct kvm_vcpu *vcpu, unsigned long extid); 90 - bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, int idx); 91 89 int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run); 92 90 void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu); 93 91 void kvm_riscv_vcpu_sbi_deinit(struct kvm_vcpu *vcpu);
+2 -27
arch/riscv/kvm/vcpu_onereg.c
··· 1082 1082 return copy_isa_ext_reg_indices(vcpu, NULL); 1083 1083 } 1084 1084 1085 - static int copy_sbi_ext_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 1086 - { 1087 - unsigned int n = 0; 1088 - 1089 - for (int i = 0; i < KVM_RISCV_SBI_EXT_MAX; i++) { 1090 - u64 size = IS_ENABLED(CONFIG_32BIT) ? 1091 - KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64; 1092 - u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_SBI_EXT | 1093 - KVM_REG_RISCV_SBI_SINGLE | i; 1094 - 1095 - if (!riscv_vcpu_supports_sbi_ext(vcpu, i)) 1096 - continue; 1097 - 1098 - if (uindices) { 1099 - if (put_user(reg, uindices)) 1100 - return -EFAULT; 1101 - uindices++; 1102 - } 1103 - 1104 - n++; 1105 - } 1106 - 1107 - return n; 1108 - } 1109 - 1110 1085 static unsigned long num_sbi_ext_regs(struct kvm_vcpu *vcpu) 1111 1086 { 1112 - return copy_sbi_ext_reg_indices(vcpu, NULL); 1087 + return kvm_riscv_vcpu_reg_indices_sbi_ext(vcpu, NULL); 1113 1088 } 1114 1089 1115 1090 static inline unsigned long num_sbi_regs(struct kvm_vcpu *vcpu) ··· 1212 1237 return ret; 1213 1238 uindices += ret; 1214 1239 1215 - ret = copy_sbi_ext_reg_indices(vcpu, uindices); 1240 + ret = kvm_riscv_vcpu_reg_indices_sbi_ext(vcpu, uindices); 1216 1241 if (ret < 0) 1217 1242 return ret; 1218 1243 uindices += ret;
+26 -1
arch/riscv/kvm/vcpu_sbi.c
··· 110 110 return sext; 111 111 } 112 112 113 - bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, int idx) 113 + static bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, int idx) 114 114 { 115 115 struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context; 116 116 const struct kvm_riscv_sbi_extension_entry *sext; ··· 286 286 } 287 287 288 288 return 0; 289 + } 290 + 291 + int kvm_riscv_vcpu_reg_indices_sbi_ext(struct kvm_vcpu *vcpu, u64 __user *uindices) 292 + { 293 + unsigned int n = 0; 294 + 295 + for (int i = 0; i < KVM_RISCV_SBI_EXT_MAX; i++) { 296 + u64 size = IS_ENABLED(CONFIG_32BIT) ? 297 + KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64; 298 + u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_SBI_EXT | 299 + KVM_REG_RISCV_SBI_SINGLE | i; 300 + 301 + if (!riscv_vcpu_supports_sbi_ext(vcpu, i)) 302 + continue; 303 + 304 + if (uindices) { 305 + if (put_user(reg, uindices)) 306 + return -EFAULT; 307 + uindices++; 308 + } 309 + 310 + n++; 311 + } 312 + 313 + return n; 289 314 } 290 315 291 316 int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu,