Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'riscv-for-linus-5.16-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V Fixes for 5.16-rc4
- .rodata is no longer linkd into PT_DYNAMIC.
It was not supposed to be there in the first place and resulted in
invalid (but unused) entries. This manifests as at least warnings in
llvm-readelf
- A fix for runtime constants with all-0 upper 32-bits. This should
only manifest on MMU=n kernels
- A fix for context save/restore on systems using the T-Head vector
extensions
- A fix for a conflicting "+r"/"r" register constraint in the VDSO
getrandom syscall wrapper, which is undefined behavior in clang
- A fix for a missing register clobber in the RVV raid6 implementation.
This manifests as a NULL pointer reference on some compilers, but
could trigger in other ways
- Misaligned accesses from userspace at faulting addresses are now
handled correctly
- A fix for an incorrect optimization that allowed access_ok() to mark
invalid addresses as accessible, which can result in userspace
triggering BUG()s
- A few fixes for build warnings, and an update to Drew's email address
* tag 'riscv-for-linus-5.16-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: export boot_cpu_hartid
Revert "riscv: Define TASK_SIZE_MAX for __access_ok()"
riscv: Fix sparse warning in vendor_extensions/sifive.c
Revert "riscv: misaligned: fix sleeping function called during misaligned access handling"
MAINTAINERS: Update Drew Fustini's email address
RISC-V: uaccess: Wrap the get_user_8 uaccess macro
raid6: riscv: Fix NULL pointer dereference caused by a missing clobber
RISC-V: vDSO: Correct inline assembly constraints in the getrandom syscall wrapper
riscv: vector: Fix context save/restore with xtheadvector
riscv: fix runtime constant support for nommu kernels
riscv: vdso: Exclude .rodata from the PT_DYNAMIC segment
+45
-35
+1
.mailmap
+1
.mailmap
···
223
223
Dmitry Safonov <0x7f454c46@gmail.com> <dsafonov@virtuozzo.com>
224
224
Domen Puncer <domen@coderock.org>
225
225
Douglas Gilbert <dougg@torque.net>
226
+
Drew Fustini <fustini@kernel.org> <drew@pdp7.com>
226
227
Ed L. Cashin <ecashin@coraid.com>
227
228
Elliot Berman <quic_eberman@quicinc.com> <eberman@codeaurora.org>
228
229
Enric Balletbo i Serra <eballetbo@kernel.org> <enric.balletbo@collabora.com>
+1
-1
MAINTAINERS
+1
-1
MAINTAINERS
-1
arch/riscv/include/asm/pgtable.h
-1
arch/riscv/include/asm/pgtable.h
+1
-1
arch/riscv/include/asm/runtime-const.h
+1
-1
arch/riscv/include/asm/runtime-const.h
···
206
206
addi_insn_mask &= 0x07fff;
207
207
}
208
208
209
-
if (lower_immediate & 0x00000fff) {
209
+
if (lower_immediate & 0x00000fff || lui_insn == RISCV_INSN_NOP4) {
210
210
/* replace upper 12 bits of addi with lower 12 bits of val */
211
211
addi_insn &= addi_insn_mask;
212
212
addi_insn |= (lower_immediate & 0x00000fff) << 20;
+2
-1
arch/riscv/include/asm/uaccess.h
+2
-1
arch/riscv/include/asm/uaccess.h
···
127
127
128
128
#ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT
129
129
#define __get_user_8(x, ptr, label) \
130
+
do { \
130
131
u32 __user *__ptr = (u32 __user *)(ptr); \
131
132
u32 __lo, __hi; \
132
133
asm_goto_output( \
···
142
141
: : label); \
143
142
(x) = (__typeof__(x))((__typeof__((x) - (x)))( \
144
143
(((u64)__hi << 32) | __lo))); \
145
-
144
+
} while (0)
146
145
#else /* !CONFIG_CC_HAS_ASM_GOTO_OUTPUT */
147
146
#define __get_user_8(x, ptr, label) \
148
147
do { \
+1
-1
arch/riscv/include/asm/vdso/getrandom.h
+1
-1
arch/riscv/include/asm/vdso/getrandom.h
+6
-6
arch/riscv/include/asm/vector.h
+6
-6
arch/riscv/include/asm/vector.h
···
205
205
THEAD_VSETVLI_T4X0E8M8D1
206
206
THEAD_VSB_V_V0T0
207
207
"add t0, t0, t4\n\t"
208
-
THEAD_VSB_V_V0T0
208
+
THEAD_VSB_V_V8T0
209
209
"add t0, t0, t4\n\t"
210
-
THEAD_VSB_V_V0T0
210
+
THEAD_VSB_V_V16T0
211
211
"add t0, t0, t4\n\t"
212
-
THEAD_VSB_V_V0T0
212
+
THEAD_VSB_V_V24T0
213
213
: : "r" (datap) : "memory", "t0", "t4");
214
214
} else {
215
215
asm volatile (
···
241
241
THEAD_VSETVLI_T4X0E8M8D1
242
242
THEAD_VLB_V_V0T0
243
243
"add t0, t0, t4\n\t"
244
-
THEAD_VLB_V_V0T0
244
+
THEAD_VLB_V_V8T0
245
245
"add t0, t0, t4\n\t"
246
-
THEAD_VLB_V_V0T0
246
+
THEAD_VLB_V_V16T0
247
247
"add t0, t0, t4\n\t"
248
-
THEAD_VLB_V_V0T0
248
+
THEAD_VLB_V_V24T0
249
249
: : "r" (datap) : "memory", "t0", "t4");
250
250
} else {
251
251
asm volatile (
+1
arch/riscv/kernel/setup.c
+1
arch/riscv/kernel/setup.c
+2
-2
arch/riscv/kernel/traps_misaligned.c
+2
-2
arch/riscv/kernel/traps_misaligned.c
···
454
454
455
455
val.data_u64 = 0;
456
456
if (user_mode(regs)) {
457
-
if (copy_from_user_nofault(&val, (u8 __user *)addr, len))
457
+
if (copy_from_user(&val, (u8 __user *)addr, len))
458
458
return -1;
459
459
} else {
460
460
memcpy(&val, (u8 *)addr, len);
···
555
555
return -EOPNOTSUPP;
556
556
557
557
if (user_mode(regs)) {
558
-
if (copy_to_user_nofault((u8 __user *)addr, &val, len))
558
+
if (copy_to_user((u8 __user *)addr, &val, len))
559
559
return -1;
560
560
} else {
561
561
memcpy((u8 *)addr, &val, len);
+1
-1
arch/riscv/kernel/vdso/vdso.lds.S
+1
-1
arch/riscv/kernel/vdso/vdso.lds.S
+1
-1
arch/riscv/kernel/vendor_extensions/sifive.c
+1
-1
arch/riscv/kernel/vendor_extensions/sifive.c
···
8
8
#include <linux/types.h>
9
9
10
10
/* All SiFive vendor extensions supported in Linux */
11
-
const struct riscv_isa_ext_data riscv_isa_vendor_ext_sifive[] = {
11
+
static const struct riscv_isa_ext_data riscv_isa_vendor_ext_sifive[] = {
12
12
__RISCV_ISA_EXT_DATA(xsfvfnrclipxfqf, RISCV_ISA_VENDOR_EXT_XSFVFNRCLIPXFQF),
13
13
__RISCV_ISA_EXT_DATA(xsfvfwmaccqqq, RISCV_ISA_VENDOR_EXT_XSFVFWMACCQQQ),
14
14
__RISCV_ISA_EXT_DATA(xsfvqmaccdod, RISCV_ISA_VENDOR_EXT_XSFVQMACCDOD),
+28
-20
lib/raid6/rvv.c
+28
-20
lib/raid6/rvv.c
···
26
26
static void raid6_rvv1_gen_syndrome_real(int disks, unsigned long bytes, void **ptrs)
27
27
{
28
28
u8 **dptr = (u8 **)ptrs;
29
-
unsigned long d;
30
-
int z, z0;
31
29
u8 *p, *q;
30
+
unsigned long vl, d;
31
+
int z, z0;
32
32
33
33
z0 = disks - 3; /* Highest data disk */
34
34
p = dptr[z0 + 1]; /* XOR parity */
···
36
36
37
37
asm volatile (".option push\n"
38
38
".option arch,+v\n"
39
-
"vsetvli t0, x0, e8, m1, ta, ma\n"
39
+
"vsetvli %0, x0, e8, m1, ta, ma\n"
40
40
".option pop\n"
41
+
: "=&r" (vl)
41
42
);
42
43
43
44
/* v0:wp0, v1:wq0, v2:wd0/w20, v3:w10 */
···
100
99
{
101
100
u8 **dptr = (u8 **)ptrs;
102
101
u8 *p, *q;
103
-
unsigned long d;
102
+
unsigned long vl, d;
104
103
int z, z0;
105
104
106
105
z0 = stop; /* P/Q right side optimization */
···
109
108
110
109
asm volatile (".option push\n"
111
110
".option arch,+v\n"
112
-
"vsetvli t0, x0, e8, m1, ta, ma\n"
111
+
"vsetvli %0, x0, e8, m1, ta, ma\n"
113
112
".option pop\n"
113
+
: "=&r" (vl)
114
114
);
115
115
116
116
/* v0:wp0, v1:wq0, v2:wd0/w20, v3:w10 */
···
197
195
static void raid6_rvv2_gen_syndrome_real(int disks, unsigned long bytes, void **ptrs)
198
196
{
199
197
u8 **dptr = (u8 **)ptrs;
200
-
unsigned long d;
201
-
int z, z0;
202
198
u8 *p, *q;
199
+
unsigned long vl, d;
200
+
int z, z0;
203
201
204
202
z0 = disks - 3; /* Highest data disk */
205
203
p = dptr[z0 + 1]; /* XOR parity */
···
207
205
208
206
asm volatile (".option push\n"
209
207
".option arch,+v\n"
210
-
"vsetvli t0, x0, e8, m1, ta, ma\n"
208
+
"vsetvli %0, x0, e8, m1, ta, ma\n"
211
209
".option pop\n"
210
+
: "=&r" (vl)
212
211
);
213
212
214
213
/*
···
290
287
{
291
288
u8 **dptr = (u8 **)ptrs;
292
289
u8 *p, *q;
293
-
unsigned long d;
290
+
unsigned long vl, d;
294
291
int z, z0;
295
292
296
293
z0 = stop; /* P/Q right side optimization */
···
299
296
300
297
asm volatile (".option push\n"
301
298
".option arch,+v\n"
302
-
"vsetvli t0, x0, e8, m1, ta, ma\n"
299
+
"vsetvli %0, x0, e8, m1, ta, ma\n"
303
300
".option pop\n"
301
+
: "=&r" (vl)
304
302
);
305
303
306
304
/*
···
417
413
static void raid6_rvv4_gen_syndrome_real(int disks, unsigned long bytes, void **ptrs)
418
414
{
419
415
u8 **dptr = (u8 **)ptrs;
420
-
unsigned long d;
421
-
int z, z0;
422
416
u8 *p, *q;
417
+
unsigned long vl, d;
418
+
int z, z0;
423
419
424
420
z0 = disks - 3; /* Highest data disk */
425
421
p = dptr[z0 + 1]; /* XOR parity */
···
427
423
428
424
asm volatile (".option push\n"
429
425
".option arch,+v\n"
430
-
"vsetvli t0, x0, e8, m1, ta, ma\n"
426
+
"vsetvli %0, x0, e8, m1, ta, ma\n"
431
427
".option pop\n"
428
+
: "=&r" (vl)
432
429
);
433
430
434
431
/*
···
544
539
{
545
540
u8 **dptr = (u8 **)ptrs;
546
541
u8 *p, *q;
547
-
unsigned long d;
542
+
unsigned long vl, d;
548
543
int z, z0;
549
544
550
545
z0 = stop; /* P/Q right side optimization */
···
553
548
554
549
asm volatile (".option push\n"
555
550
".option arch,+v\n"
556
-
"vsetvli t0, x0, e8, m1, ta, ma\n"
551
+
"vsetvli %0, x0, e8, m1, ta, ma\n"
557
552
".option pop\n"
553
+
: "=&r" (vl)
558
554
);
559
555
560
556
/*
···
727
721
static void raid6_rvv8_gen_syndrome_real(int disks, unsigned long bytes, void **ptrs)
728
722
{
729
723
u8 **dptr = (u8 **)ptrs;
730
-
unsigned long d;
731
-
int z, z0;
732
724
u8 *p, *q;
725
+
unsigned long vl, d;
726
+
int z, z0;
733
727
734
728
z0 = disks - 3; /* Highest data disk */
735
729
p = dptr[z0 + 1]; /* XOR parity */
···
737
731
738
732
asm volatile (".option push\n"
739
733
".option arch,+v\n"
740
-
"vsetvli t0, x0, e8, m1, ta, ma\n"
734
+
"vsetvli %0, x0, e8, m1, ta, ma\n"
741
735
".option pop\n"
736
+
: "=&r" (vl)
742
737
);
743
738
744
739
/*
···
922
915
{
923
916
u8 **dptr = (u8 **)ptrs;
924
917
u8 *p, *q;
925
-
unsigned long d;
918
+
unsigned long vl, d;
926
919
int z, z0;
927
920
928
921
z0 = stop; /* P/Q right side optimization */
···
931
924
932
925
asm volatile (".option push\n"
933
926
".option arch,+v\n"
934
-
"vsetvli t0, x0, e8, m1, ta, ma\n"
927
+
"vsetvli %0, x0, e8, m1, ta, ma\n"
935
928
".option pop\n"
929
+
: "=&r" (vl)
936
930
);
937
931
938
932
/*