tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

Merge tag 'armsoc-fixes-v5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
"This time there is one fix for the error path in the mediatek cmdq
driver (used by their video driver) and a couple of devicetree fixes,
mostly for 32-bit ARM, and fairly harmless:

- On OMAP2 there were a few regressions in the ethernet drivers, one
of them leading to an external abort trap

- One Raspberry Pi version had a misconfigured LED

- Interrupts on Broadcom NSP were slightly misconfigured

- One i.MX6q board had issues with graphics mode setting

- On mmp3 there are some minor fixes that were submitted for v5.8
with a cc:stable tag, so I ended up picking them up here as well

- The Mediatek Video Codec needs to run at a higher frequency than
configured originally"

* tag 'armsoc-fixes-v5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
ARM: dts: mmp3: Drop usb-nop-xceiv from HSIC phy
ARM: dts: mmp3-dell-ariel: Fix the SPI devices
ARM: dts: mmp3: Use the MMP3 compatible string for /clocks
ARM: dts: bcm: HR2: Fix PPI interrupt types
ARM: dts: bcm2835-rpi-zero-w: Fix led polarity
ARM: dts/imx6q-bx50v3: Set display interface clock parents
soc: mediatek: cmdq: return send msg error code
arm64: dts: mt8173: fix vcodec-enc clock
ARM: dts: Fix wrong mdio clock for dm814x
ARM: dts: am437x: fix networking on boards with ksz9031 phy
ARM: dts: am57xx: fix networking on boards with ksz9031 phy

Linus Torvalds 86852175 e2fce151

+44 -54
+1 -1
arch/arm/boot/dts/am437x-gp-evm.dts
··· 943 943 944 944 &cpsw_emac0 { 945 945 phy-handle = <&ethphy0>; 946 - phy-mode = "rgmii"; 946 + phy-mode = "rgmii-rxid"; 947 947 }; 948 948 949 949 &elm {
+1 -1
arch/arm/boot/dts/am437x-idk-evm.dts
··· 504 504 505 505 &cpsw_emac0 { 506 506 phy-handle = <&ethphy0>; 507 - phy-mode = "rgmii"; 507 + phy-mode = "rgmii-rxid"; 508 508 }; 509 509 510 510 &rtc {
+2 -2
arch/arm/boot/dts/am437x-sk-evm.dts
··· 833 833 834 834 &cpsw_emac0 { 835 835 phy-handle = <&ethphy0>; 836 - phy-mode = "rgmii"; 836 + phy-mode = "rgmii-rxid"; 837 837 dual_emac_res_vlan = <1>; 838 838 }; 839 839 840 840 &cpsw_emac1 { 841 841 phy-handle = <&ethphy1>; 842 - phy-mode = "rgmii"; 842 + phy-mode = "rgmii-rxid"; 843 843 dual_emac_res_vlan = <2>; 844 844 }; 845 845
+2 -2
arch/arm/boot/dts/am571x-idk.dts
··· 190 190 191 191 &cpsw_port1 { 192 192 phy-handle = <&ethphy0_sw>; 193 - phy-mode = "rgmii"; 193 + phy-mode = "rgmii-rxid"; 194 194 ti,dual-emac-pvid = <1>; 195 195 }; 196 196 197 197 &cpsw_port2 { 198 198 phy-handle = <&ethphy1_sw>; 199 - phy-mode = "rgmii"; 199 + phy-mode = "rgmii-rxid"; 200 200 ti,dual-emac-pvid = <2>; 201 201 }; 202 202
+2 -2
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
··· 433 433 434 434 &cpsw_emac0 { 435 435 phy-handle = <&phy0>; 436 - phy-mode = "rgmii"; 436 + phy-mode = "rgmii-rxid"; 437 437 dual_emac_res_vlan = <1>; 438 438 }; 439 439 440 440 &cpsw_emac1 { 441 441 phy-handle = <&phy1>; 442 - phy-mode = "rgmii"; 442 + phy-mode = "rgmii-rxid"; 443 443 dual_emac_res_vlan = <2>; 444 444 }; 445 445
+2 -2
arch/arm/boot/dts/am57xx-idk-common.dtsi
··· 408 408 409 409 &cpsw_emac0 { 410 410 phy-handle = <&ethphy0>; 411 - phy-mode = "rgmii"; 411 + phy-mode = "rgmii-rxid"; 412 412 dual_emac_res_vlan = <1>; 413 413 }; 414 414 415 415 &cpsw_emac1 { 416 416 phy-handle = <&ethphy1>; 417 - phy-mode = "rgmii"; 417 + phy-mode = "rgmii-rxid"; 418 418 dual_emac_res_vlan = <2>; 419 419 }; 420 420
+3 -3
arch/arm/boot/dts/bcm-hr2.dtsi
··· 75 75 timer@20200 { 76 76 compatible = "arm,cortex-a9-global-timer"; 77 77 reg = <0x20200 0x100>; 78 - interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; 78 + interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; 79 79 clocks = <&periph_clk>; 80 80 }; 81 81 ··· 83 83 compatible = "arm,cortex-a9-twd-timer"; 84 84 reg = <0x20600 0x20>; 85 85 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | 86 - IRQ_TYPE_LEVEL_HIGH)>; 86 + IRQ_TYPE_EDGE_RISING)>; 87 87 clocks = <&periph_clk>; 88 88 }; 89 89 ··· 91 91 compatible = "arm,cortex-a9-twd-wdt"; 92 92 reg = <0x20620 0x20>; 93 93 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | 94 - IRQ_TYPE_LEVEL_HIGH)>; 94 + IRQ_TYPE_EDGE_RISING)>; 95 95 clocks = <&periph_clk>; 96 96 }; 97 97
+1 -1
arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
··· 24 24 25 25 leds { 26 26 act { 27 - gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; 27 + gpios = <&gpio 47 GPIO_ACTIVE_LOW>; 28 28 }; 29 29 }; 30 30
+1 -1
arch/arm/boot/dts/dm814x.dtsi
··· 693 693 694 694 davinci_mdio: mdio@800 { 695 695 compatible = "ti,cpsw-mdio", "ti,davinci_mdio"; 696 - clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>; 696 + clocks = <&cpsw_125mhz_gclk>; 697 697 clock-names = "fck"; 698 698 #address-cells = <1>; 699 699 #size-cells = <0>;
-7
arch/arm/boot/dts/imx6q-b450v3.dts
··· 65 65 }; 66 66 }; 67 67 68 - &clks { 69 - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 70 - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 71 - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 72 - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 73 - }; 74 - 75 68 &ldb { 76 69 status = "okay"; 77 70
-7
arch/arm/boot/dts/imx6q-b650v3.dts
··· 65 65 }; 66 66 }; 67 67 68 - &clks { 69 - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 70 - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 71 - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 72 - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 73 - }; 74 - 75 68 &ldb { 76 69 status = "okay"; 77 70
-11
arch/arm/boot/dts/imx6q-b850v3.dts
··· 53 53 }; 54 54 }; 55 55 56 - &clks { 57 - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 58 - <&clks IMX6QDL_CLK_LDB_DI1_SEL>, 59 - <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, 60 - <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; 61 - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, 62 - <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, 63 - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, 64 - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; 65 - }; 66 - 67 56 &ldb { 68 57 fsl,dual-channel; 69 58 status = "okay";
+15
arch/arm/boot/dts/imx6q-bx50v3.dtsi
··· 377 377 #interrupt-cells = <1>; 378 378 }; 379 379 }; 380 + 381 + &clks { 382 + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 383 + <&clks IMX6QDL_CLK_LDB_DI1_SEL>, 384 + <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, 385 + <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>, 386 + <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>, 387 + <&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>; 388 + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, 389 + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, 390 + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, 391 + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, 392 + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, 393 + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; 394 + };
+6 -6
arch/arm/boot/dts/mmp3-dell-ariel.dts
··· 98 98 status = "okay"; 99 99 }; 100 100 101 - &ssp3 { 101 + &ssp1 { 102 102 status = "okay"; 103 - cs-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; 103 + cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; 104 104 105 105 firmware-flash@0 { 106 - compatible = "st,m25p80", "jedec,spi-nor"; 106 + compatible = "winbond,w25q32", "jedec,spi-nor"; 107 107 reg = <0>; 108 - spi-max-frequency = <40000000>; 108 + spi-max-frequency = <104000000>; 109 109 m25p,fast-read; 110 110 }; 111 111 }; 112 112 113 - &ssp4 { 114 - cs-gpios = <&gpio 56 GPIO_ACTIVE_HIGH>; 113 + &ssp2 { 114 + cs-gpios = <&gpio 56 GPIO_ACTIVE_LOW>; 115 115 status = "okay"; 116 116 };
+3 -5
arch/arm/boot/dts/mmp3.dtsi
··· 202 202 }; 203 203 204 204 hsic_phy0: hsic-phy@f0001800 { 205 - compatible = "marvell,mmp3-hsic-phy", 206 - "usb-nop-xceiv"; 205 + compatible = "marvell,mmp3-hsic-phy"; 207 206 reg = <0xf0001800 0x40>; 208 207 #phy-cells = <0>; 209 208 status = "disabled"; ··· 223 224 }; 224 225 225 226 hsic_phy1: hsic-phy@f0002800 { 226 - compatible = "marvell,mmp3-hsic-phy", 227 - "usb-nop-xceiv"; 227 + compatible = "marvell,mmp3-hsic-phy"; 228 228 reg = <0xf0002800 0x40>; 229 229 #phy-cells = <0>; 230 230 status = "disabled"; ··· 529 531 }; 530 532 531 533 soc_clocks: clocks@d4050000 { 532 - compatible = "marvell,mmp2-clock"; 534 + compatible = "marvell,mmp3-clock"; 533 535 reg = <0xd4050000 0x1000>, 534 536 <0xd4282800 0x400>, 535 537 <0xd4015000 0x1000>;
+2 -2
arch/arm64/boot/dts/mediatek/mt8173.dtsi
··· 1402 1402 "venc_lt_sel"; 1403 1403 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, 1404 1404 <&topckgen CLK_TOP_VENC_LT_SEL>; 1405 - assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>, 1406 - <&topckgen CLK_TOP_UNIVPLL1_D2>; 1405 + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>, 1406 + <&topckgen CLK_TOP_VCODECPLL_370P5>; 1407 1407 }; 1408 1408 1409 1409 jpegdec: jpegdec@18004000 {
+3 -1
drivers/soc/mediatek/mtk-cmdq-helper.c
··· 351 351 spin_unlock_irqrestore(&client->lock, flags); 352 352 } 353 353 354 - mbox_send_message(client->chan, pkt); 354 + err = mbox_send_message(client->chan, pkt); 355 + if (err < 0) 356 + return err; 355 357 /* We can send next packet immediately, so just call txdone. */ 356 358 mbox_client_txdone(client->chan, 0); 357 359