Merge tag 'tty-6.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty

+8 -2

arch/mips/alchemy/common/platform.c

··· 51 51 #define PORT(_base, _irq) \ 52 52 { \ 53 53 .mapbase = _base, \ 54 + .mapsize = 0x1000, \ 54 55 .irq = _irq, \ 55 56 .regshift = 2, \ 56 - .iotype = UPIO_AU, \ 57 57 .flags = UPF_SKIP_TEST | UPF_IOREMAP | \ 58 58 UPF_FIXED_TYPE, \ 59 59 .type = PORT_16550A, \ ··· 124 124 au1xx0_uart_device.dev.platform_data = ports; 125 125 126 126 /* Fill up uartclk. */ 127 - for (s = 0; s < c; s++) 127 + for (s = 0; s < c; s++) { 128 128 ports[s].uartclk = uartclk; 129 + if (au_platform_setup(&ports[s]) < 0) { 130 + kfree(ports); 131 + printk(KERN_INFO "Alchemy: missing support for UARTs\n"); 132 + return; 133 + } 134 + } 129 135 if (platform_device_register(&au1xx0_uart_device)) 130 136 printk(KERN_INFO "Alchemy: failed to register UARTs\n"); 131 137 }

+9 -5

arch/powerpc/kernel/legacy_serial.c

··· 508 508 509 509 port->irq = virq; 510 510 511 - #ifdef CONFIG_SERIAL_8250_FSL 512 - if (of_device_is_compatible(np, "fsl,ns16550")) { 513 - port->handle_irq = fsl8250_handle_irq; 514 - port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 511 + if (IS_ENABLED(CONFIG_SERIAL_8250) && 512 + of_device_is_compatible(np, "fsl,ns16550")) { 513 + if (IS_REACHABLE(CONFIG_SERIAL_8250_FSL)) { 514 + port->handle_irq = fsl8250_handle_irq; 515 + port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 516 + } else { 517 + pr_warn_once("Not activating Freescale specific workaround for device %pOFP\n", 518 + np); 519 + } 515 520 } 516 - #endif 517 521 } 518 522 519 523 static void __init fixup_port_pio(int index,

+21 -4

drivers/tty/n_tty.c

··· 203 203 struct n_tty_data *ldata = tty->disc_data; 204 204 205 205 /* Did the input worker stop? Restart it */ 206 - if (unlikely(ldata->no_room)) { 207 - ldata->no_room = 0; 206 + if (unlikely(READ_ONCE(ldata->no_room))) { 207 + WRITE_ONCE(ldata->no_room, 0); 208 208 209 209 WARN_RATELIMIT(tty->port->itty == NULL, 210 210 "scheduling with invalid itty\n"); ··· 1697 1697 if (overflow && room < 0) 1698 1698 ldata->read_head--; 1699 1699 room = overflow; 1700 - ldata->no_room = flow && !room; 1700 + WRITE_ONCE(ldata->no_room, flow && !room); 1701 1701 } else 1702 1702 overflow = 0; 1703 1703 ··· 1727 1727 } 1728 1728 } else 1729 1729 n_tty_check_throttle(tty); 1730 + 1731 + if (unlikely(ldata->no_room)) { 1732 + /* 1733 + * Barrier here is to ensure to read the latest read_tail in 1734 + * chars_in_buffer() and to make sure that read_tail is not loaded 1735 + * before ldata->no_room is set. 1736 + */ 1737 + smp_mb(); 1738 + if (!chars_in_buffer(tty)) 1739 + n_tty_kick_worker(tty); 1740 + } 1730 1741 1731 1742 up_read(&tty->termios_rwsem); 1732 1743 ··· 2292 2281 if (time) 2293 2282 timeout = time; 2294 2283 } 2295 - if (old_tail != ldata->read_tail) 2284 + if (old_tail != ldata->read_tail) { 2285 + /* 2286 + * Make sure no_room is not read in n_tty_kick_worker() 2287 + * before setting ldata->read_tail in copy_from_read_buf(). 2288 + */ 2289 + smp_mb(); 2296 2290 n_tty_kick_worker(tty); 2291 + } 2297 2292 up_read(&tty->termios_rwsem); 2298 2293 2299 2294 remove_wait_queue(&tty->read_wait, &wait);

+8 -3

drivers/tty/serial/8250/8250.h

··· 91 91 #define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */ 92 92 #define UART_BUG_NOMSR BIT(2) /* UART has buggy MSR status bits (Au1x00) */ 93 93 #define UART_BUG_THRE BIT(3) /* UART has buggy THRE reassertion */ 94 - #define UART_BUG_PARITY BIT(4) /* UART mishandles parity if FIFO enabled */ 95 94 #define UART_BUG_TXRACE BIT(5) /* UART Tx fails to set remote DR */ 96 95 97 96 ··· 166 167 167 168 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p); 168 169 169 - static inline int serial_dl_read(struct uart_8250_port *up) 170 + static inline u32 serial_dl_read(struct uart_8250_port *up) 170 171 { 171 172 return up->dl_read(up); 172 173 } 173 174 174 - static inline void serial_dl_write(struct uart_8250_port *up, int value) 175 + static inline void serial_dl_write(struct uart_8250_port *up, u32 value) 175 176 { 176 177 up->dl_write(up, value); 177 178 } 178 179 179 180 static inline bool serial8250_set_THRI(struct uart_8250_port *up) 180 181 { 182 + /* Port locked to synchronize UART_IER access against the console. */ 183 + lockdep_assert_held_once(&up->port.lock); 184 + 181 185 if (up->ier & UART_IER_THRI) 182 186 return false; 183 187 up->ier |= UART_IER_THRI; ··· 190 188 191 189 static inline bool serial8250_clear_THRI(struct uart_8250_port *up) 192 190 { 191 + /* Port locked to synchronize UART_IER access against the console. */ 192 + lockdep_assert_held_once(&up->port.lock); 193 + 193 194 if (!(up->ier & UART_IER_THRI)) 194 195 return false; 195 196 up->ier &= ~UART_IER_THRI;

+3

drivers/tty/serial/8250/8250_aspeed_vuart.c

··· 275 275 { 276 276 unsigned char irqs = UART_IER_RLSI | UART_IER_RDI; 277 277 278 + /* Port locked to synchronize UART_IER access against the console. */ 279 + lockdep_assert_held_once(&up->port.lock); 280 + 278 281 up->ier &= ~irqs; 279 282 if (!throttle) 280 283 up->ier |= irqs;

+4

drivers/tty/serial/8250/8250_bcm7271.c

··· 605 605 /* 606 606 * Disable the Receive Data Interrupt because the DMA engine 607 607 * will handle this. 608 + * 609 + * Synchronize UART_IER access against the console. 608 610 */ 611 + spin_lock_irq(&port->lock); 609 612 up->ier &= ~UART_IER_RDI; 610 613 serial_port_out(port, UART_IER, up->ier); 614 + spin_unlock_irq(&port->lock); 611 615 612 616 priv->tx_running = false; 613 617 priv->dma.rx_dma = NULL;

+68 -23

drivers/tty/serial/8250/8250_core.c

··· 488 488 up->port.quirks |= skip_txen_test ? UPQ_NO_TXEN_TEST : 0; 489 489 } 490 490 491 + static struct uart_8250_port *serial8250_setup_port(int index) 492 + { 493 + struct uart_8250_port *up; 494 + 495 + if (index >= UART_NR) 496 + return NULL; 497 + 498 + up = &serial8250_ports[index]; 499 + up->port.line = index; 500 + 501 + serial8250_init_port(up); 502 + if (!base_ops) 503 + base_ops = up->port.ops; 504 + up->port.ops = &univ8250_port_ops; 505 + 506 + timer_setup(&up->timer, serial8250_timeout, 0); 507 + 508 + up->ops = &univ8250_driver_ops; 509 + 510 + if (IS_ENABLED(CONFIG_ALPHA_JENSEN) || 511 + (IS_ENABLED(CONFIG_ALPHA_GENERIC) && alpha_jensen())) 512 + up->port.set_mctrl = alpha_jensen_set_mctrl; 513 + 514 + serial8250_set_defaults(up); 515 + 516 + return up; 517 + } 518 + 491 519 static void __init serial8250_isa_init_ports(void) 492 520 { 493 521 struct uart_8250_port *up; ··· 529 501 if (nr_uarts > UART_NR) 530 502 nr_uarts = UART_NR; 531 503 532 - for (i = 0; i < nr_uarts; i++) { 533 - struct uart_8250_port *up = &serial8250_ports[i]; 534 - struct uart_port *port = &up->port; 535 - 536 - port->line = i; 537 - serial8250_init_port(up); 538 - if (!base_ops) 539 - base_ops = port->ops; 540 - port->ops = &univ8250_port_ops; 541 - 542 - timer_setup(&up->timer, serial8250_timeout, 0); 543 - 544 - up->ops = &univ8250_driver_ops; 545 - 546 - if (IS_ENABLED(CONFIG_ALPHA_JENSEN) || 547 - (IS_ENABLED(CONFIG_ALPHA_GENERIC) && alpha_jensen())) 548 - port->set_mctrl = alpha_jensen_set_mctrl; 549 - 550 - serial8250_set_defaults(up); 551 - } 504 + /* 505 + * Set up initial isa ports based on nr_uart module param, or else 506 + * default to CONFIG_SERIAL_8250_RUNTIME_UARTS. Note that we do not 507 + * need to increase nr_uarts when setting up the initial isa ports. 508 + */ 509 + for (i = 0; i < nr_uarts; i++) 510 + serial8250_setup_port(i); 552 511 553 512 /* chain base port ops to support Remote Supervisor Adapter */ 554 513 univ8250_port_ops = *base_ops; ··· 601 586 602 587 static int univ8250_console_setup(struct console *co, char *options) 603 588 { 589 + struct uart_8250_port *up; 604 590 struct uart_port *port; 605 - int retval; 591 + int retval, i; 606 592 607 593 /* 608 594 * Check whether an invalid uart number has been specified, and 609 595 * if so, search for the first available port that does have 610 596 * console support. 611 597 */ 612 - if (co->index >= nr_uarts) 598 + if (co->index >= UART_NR) 613 599 co->index = 0; 600 + 601 + /* 602 + * If the console is past the initial isa ports, init more ports up to 603 + * co->index as needed and increment nr_uarts accordingly. 604 + */ 605 + for (i = nr_uarts; i <= co->index; i++) { 606 + up = serial8250_setup_port(i); 607 + if (!up) 608 + return -ENODEV; 609 + nr_uarts++; 610 + } 611 + 614 612 port = &serial8250_ports[co->index].port; 615 613 /* link port to console */ 616 614 port->cons = co; ··· 850 822 uart.port.iotype = p->iotype; 851 823 uart.port.flags = p->flags; 852 824 uart.port.mapbase = p->mapbase; 825 + uart.port.mapsize = p->mapsize; 853 826 uart.port.hub6 = p->hub6; 854 827 uart.port.has_sysrq = p->has_sysrq; 855 828 uart.port.private_data = p->private_data; 856 829 uart.port.type = p->type; 830 + uart.bugs = p->bugs; 857 831 uart.port.serial_in = p->serial_in; 858 832 uart.port.serial_out = p->serial_out; 833 + uart.dl_read = p->dl_read; 834 + uart.dl_write = p->dl_write; 859 835 uart.port.handle_irq = p->handle_irq; 860 836 uart.port.handle_break = p->handle_break; 861 837 uart.port.set_termios = p->set_termios; ··· 1022 990 mutex_lock(&serial_mutex); 1023 991 1024 992 uart = serial8250_find_match_or_unused(&up->port); 1025 - if (uart && uart->port.type != PORT_8250_CIR) { 993 + if (!uart) { 994 + /* 995 + * If the port is past the initial isa ports, initialize a new 996 + * port and increment nr_uarts accordingly. 997 + */ 998 + uart = serial8250_setup_port(nr_uarts); 999 + if (!uart) 1000 + goto unlock; 1001 + nr_uarts++; 1002 + } 1003 + 1004 + if (uart->port.type != PORT_8250_CIR) { 1026 1005 struct mctrl_gpios *gpios; 1027 1006 1028 1007 if (uart->port.dev) 1029 1008 uart_remove_one_port(&serial8250_reg, &uart->port); 1030 1009 1010 + uart->port.ctrl_id = up->port.ctrl_id; 1031 1011 uart->port.iobase = up->port.iobase; 1032 1012 uart->port.membase = up->port.membase; 1033 1013 uart->port.irq = up->port.irq; ··· 1164 1120 } 1165 1121 } 1166 1122 1123 + unlock: 1167 1124 mutex_unlock(&serial_mutex); 1168 1125 1169 1126 return ret;

-21

drivers/tty/serial/8250/8250_early.c

··· 36 36 37 37 static unsigned int serial8250_early_in(struct uart_port *port, int offset) 38 38 { 39 - int reg_offset = offset; 40 39 offset <<= port->regshift; 41 40 42 41 switch (port->iotype) { ··· 49 50 return ioread32be(port->membase + offset); 50 51 case UPIO_PORT: 51 52 return inb(port->iobase + offset); 52 - case UPIO_AU: 53 - return port->serial_in(port, reg_offset); 54 53 default: 55 54 return 0; 56 55 } ··· 56 59 57 60 static void serial8250_early_out(struct uart_port *port, int offset, int value) 58 61 { 59 - int reg_offset = offset; 60 62 offset <<= port->regshift; 61 63 62 64 switch (port->iotype) { ··· 73 77 break; 74 78 case UPIO_PORT: 75 79 outb(value, port->iobase + offset); 76 - break; 77 - case UPIO_AU: 78 - port->serial_out(port, reg_offset, value); 79 80 break; 80 81 } 81 82 } ··· 190 197 OF_EARLYCON_DECLARE(omap8250, "ti,omap2-uart", early_omap8250_setup); 191 198 OF_EARLYCON_DECLARE(omap8250, "ti,omap3-uart", early_omap8250_setup); 192 199 OF_EARLYCON_DECLARE(omap8250, "ti,omap4-uart", early_omap8250_setup); 193 - 194 - #endif 195 - 196 - #ifdef CONFIG_SERIAL_8250_RT288X 197 - 198 - static int __init early_au_setup(struct earlycon_device *dev, const char *opt) 199 - { 200 - dev->port.serial_in = au_serial_in; 201 - dev->port.serial_out = au_serial_out; 202 - dev->port.iotype = UPIO_AU; 203 - dev->con->write = early_serial8250_write; 204 - return 0; 205 - } 206 - OF_EARLYCON_DECLARE(palmchip, "ralink,rt2880-uart", early_au_setup); 207 200 208 201 #endif

+2 -2

drivers/tty/serial/8250/8250_em.c

··· 139 139 } 140 140 } 141 141 142 - static int serial8250_em_serial_dl_read(struct uart_8250_port *up) 142 + static u32 serial8250_em_serial_dl_read(struct uart_8250_port *up) 143 143 { 144 144 return serial_in(up, UART_DLL_EM) | serial_in(up, UART_DLM_EM) << 8; 145 145 } 146 146 147 - static void serial8250_em_serial_dl_write(struct uart_8250_port *up, int value) 147 + static void serial8250_em_serial_dl_write(struct uart_8250_port *up, u32 value) 148 148 { 149 149 serial_out(up, UART_DLL_EM, value & 0xff); 150 150 serial_out(up, UART_DLM_EM, value >> 8 & 0xff);

+4

drivers/tty/serial/8250/8250_exar.c

··· 198 198 /* 199 199 * Make sure all interrups are masked until initialization is 200 200 * complete and the FIFOs are cleared 201 + * 202 + * Synchronize UART_IER access against the console. 201 203 */ 204 + spin_lock_irq(&port->lock); 202 205 serial_port_out(port, UART_IER, 0); 206 + spin_unlock_irq(&port->lock); 203 207 204 208 return serial8250_do_startup(port); 205 209 }

+16 -1

drivers/tty/serial/8250/8250_fsl.c

··· 38 38 return 0; 39 39 } 40 40 41 - /* This is the WAR; if last event was BRK, then read and return */ 41 + /* 42 + * For a single break the hardware reports LSR.BI for each character 43 + * time. This is described in the MPC8313E chip errata as "General17". 44 + * A typical break has a duration of 0.3s, with a 115200n8 configuration 45 + * that (theoretically) corresponds to ~3500 interrupts in these 0.3s. 46 + * In practise it's less (around 500) because of hardware 47 + * and software latencies. The workaround recommended by the vendor is 48 + * to read the RX register (to clear LSR.DR and thus prevent a FIFO 49 + * aging interrupt). To prevent the irq from retriggering LSR must not be 50 + * read. (This would clear LSR.BI, hardware would reassert the BI event 51 + * immediately and interrupt the CPU again. The hardware clears LSR.BI 52 + * when the next valid char is read.) 53 + */ 42 54 if (unlikely(up->lsr_saved_flags & UART_LSR_BI)) { 43 55 up->lsr_saved_flags &= ~UART_LSR_BI; 44 56 port->serial_in(port, UART_RX); ··· 184 172 185 173 module_platform_driver(fsl8250_platform_driver); 186 174 #endif 175 + 176 + MODULE_LICENSE("GPL"); 177 + MODULE_DESCRIPTION("Handling of Freescale specific 8250 variants");

+19 -40

drivers/tty/serial/8250/8250_mtk.c

··· 222 222 223 223 static void mtk8250_disable_intrs(struct uart_8250_port *up, int mask) 224 224 { 225 + /* Port locked to synchronize UART_IER access against the console. */ 226 + lockdep_assert_held_once(&up->port.lock); 227 + 225 228 serial_out(up, UART_IER, serial_in(up, UART_IER) & (~mask)); 226 229 } 227 230 228 231 static void mtk8250_enable_intrs(struct uart_8250_port *up, int mask) 229 232 { 233 + /* Port locked to synchronize UART_IER access against the console. */ 234 + lockdep_assert_held_once(&up->port.lock); 235 + 230 236 serial_out(up, UART_IER, serial_in(up, UART_IER) | mask); 231 237 } 232 238 ··· 240 234 { 241 235 struct uart_port *port = &up->port; 242 236 int lcr = serial_in(up, UART_LCR); 237 + 238 + /* Port locked to synchronize UART_IER access against the console. */ 239 + lockdep_assert_held_once(&port->lock); 243 240 244 241 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 245 242 serial_out(up, MTK_UART_EFR, UART_EFR_ECB); ··· 431 422 while 432 423 (serial_in(up, MTK_UART_DEBUG0)); 433 424 434 - if (data->clk_count == 0U) { 435 - dev_dbg(dev, "%s clock count is 0\n", __func__); 436 - } else { 437 - clk_disable_unprepare(data->bus_clk); 438 - data->clk_count--; 439 - } 425 + clk_disable_unprepare(data->bus_clk); 440 426 441 427 return 0; 442 428 } ··· 439 435 static int __maybe_unused mtk8250_runtime_resume(struct device *dev) 440 436 { 441 437 struct mtk8250_data *data = dev_get_drvdata(dev); 442 - int err; 443 438 444 - if (data->clk_count > 0U) { 445 - dev_dbg(dev, "%s clock count is %d\n", __func__, 446 - data->clk_count); 447 - } else { 448 - err = clk_prepare_enable(data->bus_clk); 449 - if (err) { 450 - dev_warn(dev, "Can't enable bus clock\n"); 451 - return err; 452 - } 453 - data->clk_count++; 454 - } 439 + clk_prepare_enable(data->bus_clk); 455 440 456 441 return 0; 457 442 } ··· 449 456 mtk8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) 450 457 { 451 458 if (!state) 452 - if (!mtk8250_runtime_resume(port->dev)) 453 - pm_runtime_get_sync(port->dev); 459 + pm_runtime_get_sync(port->dev); 454 460 455 461 serial8250_do_pm(port, state, old); 456 462 457 463 if (state) 458 - if (!pm_runtime_put_sync_suspend(port->dev)) 459 - mtk8250_runtime_suspend(port->dev); 464 + pm_runtime_put_sync_suspend(port->dev); 460 465 } 461 466 462 467 #ifdef CONFIG_SERIAL_8250_DMA ··· 486 495 return 0; 487 496 } 488 497 489 - data->bus_clk = devm_clk_get(&pdev->dev, "bus"); 498 + data->bus_clk = devm_clk_get_enabled(&pdev->dev, "bus"); 490 499 if (IS_ERR(data->bus_clk)) 491 500 return PTR_ERR(data->bus_clk); 492 501 ··· 569 578 570 579 platform_set_drvdata(pdev, data); 571 580 572 - pm_runtime_enable(&pdev->dev); 573 - err = mtk8250_runtime_resume(&pdev->dev); 574 - if (err) 575 - goto err_pm_disable; 576 - 577 581 data->line = serial8250_register_8250_port(&uart); 578 - if (data->line < 0) { 579 - err = data->line; 580 - goto err_pm_disable; 581 - } 582 + if (data->line < 0) 583 + return data->line; 582 584 583 585 data->rx_wakeup_irq = platform_get_irq_optional(pdev, 1); 584 586 587 + pm_runtime_set_active(&pdev->dev); 588 + pm_runtime_enable(&pdev->dev); 589 + 585 590 return 0; 586 - 587 - err_pm_disable: 588 - pm_runtime_disable(&pdev->dev); 589 - 590 - return err; 591 591 } 592 592 593 593 static int mtk8250_remove(struct platform_device *pdev) ··· 591 609 592 610 pm_runtime_disable(&pdev->dev); 593 611 pm_runtime_put_noidle(&pdev->dev); 594 - 595 - if (!pm_runtime_status_suspended(&pdev->dev)) 596 - mtk8250_runtime_suspend(&pdev->dev); 597 612 598 613 return 0; 599 614 }

+4 -2

drivers/tty/serial/8250/8250_of.c

··· 171 171 172 172 switch (type) { 173 173 case PORT_RT2880: 174 - port->iotype = UPIO_AU; 174 + ret = rt288x_setup(port); 175 + if (ret) 176 + goto err_unprepare; 175 177 break; 176 178 } 177 179 178 - if (IS_ENABLED(CONFIG_SERIAL_8250_FSL) && 180 + if (IS_REACHABLE(CONFIG_SERIAL_8250_FSL) && 179 181 (of_device_is_compatible(np, "fsl,ns16550") || 180 182 of_device_is_compatible(np, "fsl,16550-FIFO64"))) { 181 183 port->handle_irq = fsl8250_handle_irq;

+132 -83

drivers/tty/serial/8250/8250_omap.c

··· 32 32 #include "8250.h" 33 33 34 34 #define DEFAULT_CLK_SPEED 48000000 35 + #define OMAP_UART_REGSHIFT 2 35 36 36 37 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 37 38 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) ··· 116 115 #define UART_OMAP_RX_LVL 0x19 117 116 118 117 struct omap8250_priv { 118 + void __iomem *membase; 119 119 int line; 120 120 u8 habit; 121 121 u8 mdr1; ··· 161 159 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 162 160 #endif 163 161 164 - static u32 uart_read(struct uart_8250_port *up, u32 reg) 162 + static u32 uart_read(struct omap8250_priv *priv, u32 reg) 165 163 { 166 - return readl(up->port.membase + (reg << up->port.regshift)); 164 + return readl(priv->membase + (reg << OMAP_UART_REGSHIFT)); 167 165 } 168 166 169 167 /* ··· 303 301 struct omap8250_priv *priv = up->port.private_data; 304 302 struct uart_8250_dma *dma = up->dma; 305 303 u8 mcr = serial8250_in_MCR(up); 304 + 305 + /* Port locked to synchronize UART_IER access against the console. */ 306 + lockdep_assert_held_once(&up->port.lock); 306 307 307 308 if (dma && dma->tx_running) { 308 309 /* ··· 528 523 u8 efr; 529 524 530 525 pm_runtime_get_sync(port->dev); 526 + 527 + /* Synchronize UART_IER access against the console. */ 528 + spin_lock_irq(&port->lock); 529 + 531 530 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 532 531 efr = serial_in(up, UART_EFR); 533 532 serial_out(up, UART_EFR, efr | UART_EFR_ECB); ··· 541 532 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 542 533 serial_out(up, UART_EFR, efr); 543 534 serial_out(up, UART_LCR, 0); 535 + 536 + spin_unlock_irq(&port->lock); 544 537 545 538 pm_runtime_mark_last_busy(port->dev); 546 539 pm_runtime_put_autosuspend(port->dev); ··· 559 548 u32 mvr, scheme; 560 549 u16 revision, major, minor; 561 550 562 - mvr = uart_read(up, UART_OMAP_MVER); 551 + mvr = uart_read(priv, UART_OMAP_MVER); 563 552 564 553 /* Check revision register scheme */ 565 554 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; ··· 627 616 628 617 static irqreturn_t omap8250_irq(int irq, void *dev_id) 629 618 { 630 - struct uart_port *port = dev_id; 631 - struct omap8250_priv *priv = port->private_data; 632 - struct uart_8250_port *up = up_to_u8250p(port); 619 + struct omap8250_priv *priv = dev_id; 620 + struct uart_8250_port *up = serial8250_get_port(priv->line); 621 + struct uart_port *port = &up->port; 633 622 unsigned int iir, lsr; 634 623 int ret; 635 624 ··· 660 649 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { 661 650 unsigned long delay; 662 651 652 + /* Synchronize UART_IER access against the console. */ 653 + spin_lock(&port->lock); 663 654 up->ier = port->serial_in(port, UART_IER); 664 655 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { 665 656 port->ops->stop_rx(port); ··· 671 658 */ 672 659 cancel_delayed_work(&up->overrun_backoff); 673 660 } 661 + spin_unlock(&port->lock); 674 662 675 663 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); 676 664 schedule_delayed_work(&up->overrun_backoff, delay); ··· 686 672 { 687 673 struct uart_8250_port *up = up_to_u8250p(port); 688 674 struct omap8250_priv *priv = port->private_data; 675 + struct uart_8250_dma *dma = &priv->omap8250_dma; 689 676 int ret; 690 677 691 678 if (priv->wakeirq) { ··· 705 690 up->msr_saved_flags = 0; 706 691 707 692 /* Disable DMA for console UART */ 708 - if (uart_console(port)) 709 - up->dma = NULL; 710 - 711 - if (up->dma) { 693 + if (dma->fn && !uart_console(port)) { 694 + up->dma = &priv->omap8250_dma; 712 695 ret = serial8250_request_dma(up); 713 696 if (ret) { 714 697 dev_warn_ratelimited(port->dev, 715 698 "failed to request DMA\n"); 716 699 up->dma = NULL; 717 700 } 701 + } else { 702 + up->dma = NULL; 718 703 } 719 704 720 - ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED, 721 - dev_name(port->dev), port); 722 - if (ret < 0) 723 - goto err; 724 - 705 + /* Synchronize UART_IER access against the console. */ 706 + spin_lock_irq(&port->lock); 725 707 up->ier = UART_IER_RLSI | UART_IER_RDI; 726 708 serial_out(up, UART_IER, up->ier); 709 + spin_unlock_irq(&port->lock); 727 710 728 711 #ifdef CONFIG_PM 729 712 up->capabilities |= UART_CAP_RPM; ··· 733 720 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 734 721 serial_out(up, UART_OMAP_WER, priv->wer); 735 722 736 - if (up->dma && !(priv->habit & UART_HAS_EFR2)) 723 + if (up->dma && !(priv->habit & UART_HAS_EFR2)) { 724 + spin_lock_irq(&port->lock); 737 725 up->dma->rx_dma(up); 726 + spin_unlock_irq(&port->lock); 727 + } 728 + 729 + enable_irq(up->port.irq); 738 730 739 731 pm_runtime_mark_last_busy(port->dev); 740 732 pm_runtime_put_autosuspend(port->dev); 741 733 return 0; 742 - err: 743 - pm_runtime_mark_last_busy(port->dev); 744 - pm_runtime_put_autosuspend(port->dev); 745 - dev_pm_clear_wake_irq(port->dev); 746 - return ret; 747 734 } 748 735 749 736 static void omap_8250_shutdown(struct uart_port *port) ··· 761 748 if (priv->habit & UART_HAS_EFR2) 762 749 serial_out(up, UART_OMAP_EFR2, 0x0); 763 750 751 + /* Synchronize UART_IER access against the console. */ 752 + spin_lock_irq(&port->lock); 764 753 up->ier = 0; 765 754 serial_out(up, UART_IER, 0); 755 + spin_unlock_irq(&port->lock); 756 + disable_irq_nosync(up->port.irq); 757 + dev_pm_clear_wake_irq(port->dev); 766 758 767 - if (up->dma) 768 - serial8250_release_dma(up); 759 + serial8250_release_dma(up); 760 + up->dma = NULL; 769 761 770 762 /* 771 763 * Disable break condition and FIFOs ··· 781 763 782 764 pm_runtime_mark_last_busy(port->dev); 783 765 pm_runtime_put_autosuspend(port->dev); 784 - free_irq(port->irq, port); 785 - dev_pm_clear_wake_irq(port->dev); 786 766 } 787 767 788 768 static void omap_8250_throttle(struct uart_port *port) ··· 807 791 808 792 pm_runtime_get_sync(port->dev); 809 793 794 + /* Synchronize UART_IER access against the console. */ 810 795 spin_lock_irqsave(&port->lock, flags); 811 796 priv->throttled = false; 812 797 if (up->dma) ··· 958 941 struct dma_tx_state state; 959 942 unsigned long flags; 960 943 944 + /* Synchronize UART_IER access against the console. */ 961 945 spin_lock_irqsave(&p->port.lock, flags); 962 946 963 947 /* ··· 1015 997 struct dma_async_tx_descriptor *desc; 1016 998 unsigned long flags; 1017 999 u32 reg; 1000 + 1001 + /* Port locked to synchronize UART_IER access against the console. */ 1002 + lockdep_assert_held_once(&p->port.lock); 1018 1003 1019 1004 if (priv->rx_dma_broken) 1020 1005 return -EINVAL; ··· 1233 1212 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, 1234 1213 u16 status) 1235 1214 { 1215 + /* Port locked to synchronize UART_IER access against the console. */ 1216 + lockdep_assert_held_once(&up->port.lock); 1217 + 1236 1218 /* 1237 1219 * Queue a new transfer if FIFO has data. 1238 1220 */ ··· 1418 1394 UPF_HARD_FLOW; 1419 1395 up.port.private_data = priv; 1420 1396 1421 - up.port.regshift = 2; 1397 + up.port.regshift = OMAP_UART_REGSHIFT; 1422 1398 up.port.fifosize = 64; 1423 1399 up.tx_loadsz = 64; 1424 1400 up.capabilities = UART_CAP_FIFO; ··· 1468 1444 &up.overrun_backoff_time_ms) != 0) 1469 1445 up.overrun_backoff_time_ms = 0; 1470 1446 1471 - priv->wakeirq = irq_of_parse_and_map(np, 1); 1472 - 1473 1447 pdata = of_device_get_match_data(&pdev->dev); 1474 1448 if (pdata) 1475 1449 priv->habit |= pdata->habit; ··· 1479 1457 DEFAULT_CLK_SPEED); 1480 1458 } 1481 1459 1460 + priv->membase = membase; 1461 + priv->line = -ENODEV; 1482 1462 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1483 1463 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1484 1464 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); 1485 1465 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1486 1466 1487 1467 spin_lock_init(&priv->rx_dma_lock); 1468 + 1469 + platform_set_drvdata(pdev, priv); 1488 1470 1489 1471 device_init_wakeup(&pdev->dev, true); 1490 1472 pm_runtime_enable(&pdev->dev); ··· 1524 1498 ret = of_property_count_strings(np, "dma-names"); 1525 1499 if (ret == 2) { 1526 1500 struct omap8250_dma_params *dma_params = NULL; 1501 + struct uart_8250_dma *dma = &priv->omap8250_dma; 1527 1502 1528 - up.dma = &priv->omap8250_dma; 1529 - up.dma->fn = the_no_dma_filter_fn; 1530 - up.dma->tx_dma = omap_8250_tx_dma; 1531 - up.dma->rx_dma = omap_8250_rx_dma; 1503 + dma->fn = the_no_dma_filter_fn; 1504 + dma->tx_dma = omap_8250_tx_dma; 1505 + dma->rx_dma = omap_8250_rx_dma; 1532 1506 if (pdata) 1533 1507 dma_params = pdata->dma_params; 1534 1508 1535 1509 if (dma_params) { 1536 - up.dma->rx_size = dma_params->rx_size; 1537 - up.dma->rxconf.src_maxburst = dma_params->rx_trigger; 1538 - up.dma->txconf.dst_maxburst = dma_params->tx_trigger; 1510 + dma->rx_size = dma_params->rx_size; 1511 + dma->rxconf.src_maxburst = dma_params->rx_trigger; 1512 + dma->txconf.dst_maxburst = dma_params->tx_trigger; 1539 1513 priv->rx_trigger = dma_params->rx_trigger; 1540 1514 priv->tx_trigger = dma_params->tx_trigger; 1541 1515 } else { 1542 - up.dma->rx_size = RX_TRIGGER; 1543 - up.dma->rxconf.src_maxburst = RX_TRIGGER; 1544 - up.dma->txconf.dst_maxburst = TX_TRIGGER; 1516 + dma->rx_size = RX_TRIGGER; 1517 + dma->rxconf.src_maxburst = RX_TRIGGER; 1518 + dma->txconf.dst_maxburst = TX_TRIGGER; 1545 1519 } 1546 1520 } 1547 1521 #endif 1522 + 1523 + irq_set_status_flags(irq, IRQ_NOAUTOEN); 1524 + ret = devm_request_irq(&pdev->dev, irq, omap8250_irq, 0, 1525 + dev_name(&pdev->dev), priv); 1526 + if (ret < 0) 1527 + return ret; 1528 + 1529 + priv->wakeirq = irq_of_parse_and_map(np, 1); 1530 + 1548 1531 ret = serial8250_register_8250_port(&up); 1549 1532 if (ret < 0) { 1550 1533 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1551 1534 goto err; 1552 1535 } 1553 1536 priv->line = ret; 1554 - platform_set_drvdata(pdev, priv); 1555 1537 pm_runtime_mark_last_busy(&pdev->dev); 1556 1538 pm_runtime_put_autosuspend(&pdev->dev); 1557 1539 return 0; 1558 1540 err: 1559 1541 pm_runtime_dont_use_autosuspend(&pdev->dev); 1560 1542 pm_runtime_put_sync(&pdev->dev); 1543 + flush_work(&priv->qos_work); 1561 1544 pm_runtime_disable(&pdev->dev); 1545 + cpu_latency_qos_remove_request(&priv->pm_qos_request); 1562 1546 return ret; 1563 1547 } 1564 1548 1565 1549 static int omap8250_remove(struct platform_device *pdev) 1566 1550 { 1567 1551 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1552 + struct uart_8250_port *up; 1568 1553 int err; 1569 1554 1570 1555 err = pm_runtime_resume_and_get(&pdev->dev); 1571 1556 if (err) 1572 1557 return err; 1573 1558 1559 + up = serial8250_get_port(priv->line); 1560 + omap_8250_shutdown(&up->port); 1561 + serial8250_unregister_port(priv->line); 1562 + priv->line = -ENODEV; 1574 1563 pm_runtime_dont_use_autosuspend(&pdev->dev); 1575 1564 pm_runtime_put_sync(&pdev->dev); 1576 1565 flush_work(&priv->qos_work); 1577 1566 pm_runtime_disable(&pdev->dev); 1578 - serial8250_unregister_port(priv->line); 1579 1567 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1580 1568 device_init_wakeup(&pdev->dev, false); 1581 1569 return 0; 1582 1570 } 1583 1571 1584 - #ifdef CONFIG_PM_SLEEP 1585 1572 static int omap8250_prepare(struct device *dev) 1586 1573 { 1587 1574 struct omap8250_priv *priv = dev_get_drvdata(dev); ··· 1618 1579 { 1619 1580 struct omap8250_priv *priv = dev_get_drvdata(dev); 1620 1581 struct uart_8250_port *up = serial8250_get_port(priv->line); 1582 + int err; 1621 1583 1622 1584 serial8250_suspend_port(priv->line); 1623 1585 1624 - pm_runtime_get_sync(dev); 1586 + err = pm_runtime_resume_and_get(dev); 1587 + if (err) 1588 + return err; 1625 1589 if (!device_may_wakeup(dev)) 1626 1590 priv->wer = 0; 1627 1591 serial_out(up, UART_OMAP_WER, priv->wer); 1628 - pm_runtime_mark_last_busy(dev); 1629 - pm_runtime_put_autosuspend(dev); 1630 - 1592 + err = pm_runtime_force_suspend(dev); 1631 1593 flush_work(&priv->qos_work); 1632 - return 0; 1594 + 1595 + return err; 1633 1596 } 1634 1597 1635 1598 static int omap8250_resume(struct device *dev) 1636 1599 { 1637 1600 struct omap8250_priv *priv = dev_get_drvdata(dev); 1601 + int err; 1638 1602 1603 + err = pm_runtime_force_resume(dev); 1604 + if (err) 1605 + return err; 1639 1606 serial8250_resume_port(priv->line); 1607 + /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */ 1608 + pm_runtime_mark_last_busy(dev); 1609 + pm_runtime_put_autosuspend(dev); 1610 + 1640 1611 return 0; 1641 1612 } 1642 - #else 1643 - #define omap8250_prepare NULL 1644 - #define omap8250_complete NULL 1645 - #endif 1646 1613 1647 - #ifdef CONFIG_PM 1648 1614 static int omap8250_lost_context(struct uart_8250_port *up) 1649 1615 { 1650 1616 u32 val; ··· 1665 1621 return 0; 1666 1622 } 1667 1623 1624 + static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val) 1625 + { 1626 + writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT)); 1627 + } 1628 + 1668 1629 /* TODO: in future, this should happen via API in drivers/reset/ */ 1669 1630 static int omap8250_soft_reset(struct device *dev) 1670 1631 { 1671 1632 struct omap8250_priv *priv = dev_get_drvdata(dev); 1672 - struct uart_8250_port *up = serial8250_get_port(priv->line); 1673 1633 int timeout = 100; 1674 1634 int sysc; 1675 1635 int syss; ··· 1687 1639 * needing omap8250_soft_reset() quirk. Do it in two writes as 1688 1640 * recommended in the comment for omap8250_update_scr(). 1689 1641 */ 1690 - serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1691 - serial_out(up, UART_OMAP_SCR, 1642 + uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1643 + uart_write(priv, UART_OMAP_SCR, 1692 1644 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1693 1645 1694 - sysc = serial_in(up, UART_OMAP_SYSC); 1646 + sysc = uart_read(priv, UART_OMAP_SYSC); 1695 1647 1696 1648 /* softreset the UART */ 1697 1649 sysc |= OMAP_UART_SYSC_SOFTRESET; 1698 - serial_out(up, UART_OMAP_SYSC, sysc); 1650 + uart_write(priv, UART_OMAP_SYSC, sysc); 1699 1651 1700 1652 /* By experiments, 1us enough for reset complete on AM335x */ 1701 1653 do { 1702 1654 udelay(1); 1703 - syss = serial_in(up, UART_OMAP_SYSS); 1655 + syss = uart_read(priv, UART_OMAP_SYSS); 1704 1656 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1705 1657 1706 1658 if (!timeout) { ··· 1714 1666 static int omap8250_runtime_suspend(struct device *dev) 1715 1667 { 1716 1668 struct omap8250_priv *priv = dev_get_drvdata(dev); 1717 - struct uart_8250_port *up; 1669 + struct uart_8250_port *up = NULL; 1718 1670 1719 - /* In case runtime-pm tries this before we are setup */ 1720 - if (!priv) 1721 - return 0; 1722 - 1723 - up = serial8250_get_port(priv->line); 1671 + if (priv->line >= 0) 1672 + up = serial8250_get_port(priv->line); 1724 1673 /* 1725 1674 * When using 'no_console_suspend', the console UART must not be 1726 1675 * suspended. Since driver suspend is managed by runtime suspend, ··· 1725 1680 * active during suspend. 1726 1681 */ 1727 1682 if (priv->is_suspending && !console_suspend_enabled) { 1728 - if (uart_console(&up->port)) 1683 + if (up && uart_console(&up->port)) 1729 1684 return -EBUSY; 1730 1685 } 1731 1686 ··· 1736 1691 if (ret) 1737 1692 return ret; 1738 1693 1739 - /* Restore to UART mode after reset (for wakeup) */ 1740 - omap8250_update_mdr1(up, priv); 1741 - /* Restore wakeup enable register */ 1742 - serial_out(up, UART_OMAP_WER, priv->wer); 1694 + if (up) { 1695 + /* Restore to UART mode after reset (for wakeup) */ 1696 + omap8250_update_mdr1(up, priv); 1697 + /* Restore wakeup enable register */ 1698 + serial_out(up, UART_OMAP_WER, priv->wer); 1699 + } 1743 1700 } 1744 1701 1745 - if (up->dma && up->dma->rxchan) 1702 + if (up && up->dma && up->dma->rxchan) 1746 1703 omap_8250_rx_dma_flush(up); 1747 1704 1748 1705 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; ··· 1756 1709 static int omap8250_runtime_resume(struct device *dev) 1757 1710 { 1758 1711 struct omap8250_priv *priv = dev_get_drvdata(dev); 1759 - struct uart_8250_port *up; 1712 + struct uart_8250_port *up = NULL; 1760 1713 1761 - /* In case runtime-pm tries this before we are setup */ 1762 - if (!priv) 1763 - return 0; 1714 + if (priv->line >= 0) 1715 + up = serial8250_get_port(priv->line); 1764 1716 1765 - up = serial8250_get_port(priv->line); 1766 - 1767 - if (omap8250_lost_context(up)) 1717 + if (up && omap8250_lost_context(up)) { 1718 + spin_lock_irq(&up->port.lock); 1768 1719 omap8250_restore_regs(up); 1720 + spin_unlock_irq(&up->port.lock); 1721 + } 1769 1722 1770 - if (up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) 1723 + if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) { 1724 + spin_lock_irq(&up->port.lock); 1771 1725 omap_8250_rx_dma(up); 1726 + spin_unlock_irq(&up->port.lock); 1727 + } 1772 1728 1773 1729 priv->latency = priv->calc_latency; 1774 1730 schedule_work(&priv->qos_work); 1775 1731 return 0; 1776 1732 } 1777 - #endif 1778 1733 1779 1734 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1780 1735 static int __init omap8250_console_fixup(void) ··· 1819 1770 #endif 1820 1771 1821 1772 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1822 - SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1823 - SET_RUNTIME_PM_OPS(omap8250_runtime_suspend, 1773 + SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1774 + RUNTIME_PM_OPS(omap8250_runtime_suspend, 1824 1775 omap8250_runtime_resume, NULL) 1825 - .prepare = omap8250_prepare, 1826 - .complete = omap8250_complete, 1776 + .prepare = pm_sleep_ptr(omap8250_prepare), 1777 + .complete = pm_sleep_ptr(omap8250_complete), 1827 1778 }; 1828 1779 1829 1780 static struct platform_driver omap8250_platform_driver = { 1830 1781 .driver = { 1831 1782 .name = "omap8250", 1832 - .pm = &omap8250_dev_pm_ops, 1783 + .pm = pm_ptr(&omap8250_dev_pm_ops), 1833 1784 .of_match_table = omap8250_dt_ids, 1834 1785 }, 1835 1786 .probe = omap8250_probe,

-19

drivers/tty/serial/8250/8250_pci.c

··· 1232 1232 return pci_default_setup(priv, board, up, idx); 1233 1233 } 1234 1234 1235 - static int pci_asix_setup(struct serial_private *priv, 1236 - const struct pciserial_board *board, 1237 - struct uart_8250_port *port, int idx) 1238 - { 1239 - port->bugs |= UART_BUG_PARITY; 1240 - return pci_default_setup(priv, board, port, idx); 1241 - } 1242 - 1243 1235 #define QPCR_TEST_FOR1 0x3F 1244 1236 #define QPCR_TEST_GET1 0x00 1245 1237 #define QPCR_TEST_FOR2 0x40 ··· 1947 1955 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 1948 1956 #define PCI_VENDOR_ID_AGESTAR 0x5372 1949 1957 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1950 - #define PCI_VENDOR_ID_ASIX 0x9710 1951 1958 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1952 1959 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1953 1960 ··· 2590 2599 .init = pci_wch_ch38x_init, 2591 2600 .exit = pci_wch_ch38x_exit, 2592 2601 .setup = pci_wch_ch38x_setup, 2593 - }, 2594 - /* 2595 - * ASIX devices with FIFO bug 2596 - */ 2597 - { 2598 - .vendor = PCI_VENDOR_ID_ASIX, 2599 - .device = PCI_ANY_ID, 2600 - .subvendor = PCI_ANY_ID, 2601 - .subdevice = PCI_ANY_ID, 2602 - .setup = pci_asix_setup, 2603 2602 }, 2604 2603 /* 2605 2604 * Broadcom TruManage (NetXtreme)

+76 -91

drivers/tty/serial/8250/8250_port.c

··· 325 325 }; 326 326 327 327 /* Uart divisor latch read */ 328 - static int default_serial_dl_read(struct uart_8250_port *up) 328 + static u32 default_serial_dl_read(struct uart_8250_port *up) 329 329 { 330 330 /* Assign these in pieces to truncate any bits above 7. */ 331 331 unsigned char dll = serial_in(up, UART_DLL); ··· 335 335 } 336 336 337 337 /* Uart divisor latch write */ 338 - static void default_serial_dl_write(struct uart_8250_port *up, int value) 338 + static void default_serial_dl_write(struct uart_8250_port *up, u32 value) 339 339 { 340 340 serial_out(up, UART_DLL, value & 0xff); 341 341 serial_out(up, UART_DLM, value >> 8 & 0xff); 342 342 } 343 - 344 - #ifdef CONFIG_SERIAL_8250_RT288X 345 - 346 - #define UART_REG_UNMAPPED -1 347 - 348 - /* Au1x00/RT288x UART hardware has a weird register layout */ 349 - static const s8 au_io_in_map[8] = { 350 - [UART_RX] = 0, 351 - [UART_IER] = 2, 352 - [UART_IIR] = 3, 353 - [UART_LCR] = 5, 354 - [UART_MCR] = 6, 355 - [UART_LSR] = 7, 356 - [UART_MSR] = 8, 357 - [UART_SCR] = UART_REG_UNMAPPED, 358 - }; 359 - 360 - static const s8 au_io_out_map[8] = { 361 - [UART_TX] = 1, 362 - [UART_IER] = 2, 363 - [UART_FCR] = 4, 364 - [UART_LCR] = 5, 365 - [UART_MCR] = 6, 366 - [UART_LSR] = UART_REG_UNMAPPED, 367 - [UART_MSR] = UART_REG_UNMAPPED, 368 - [UART_SCR] = UART_REG_UNMAPPED, 369 - }; 370 - 371 - unsigned int au_serial_in(struct uart_port *p, int offset) 372 - { 373 - if (offset >= ARRAY_SIZE(au_io_in_map)) 374 - return UINT_MAX; 375 - offset = au_io_in_map[offset]; 376 - if (offset == UART_REG_UNMAPPED) 377 - return UINT_MAX; 378 - return __raw_readl(p->membase + (offset << p->regshift)); 379 - } 380 - 381 - void au_serial_out(struct uart_port *p, int offset, int value) 382 - { 383 - if (offset >= ARRAY_SIZE(au_io_out_map)) 384 - return; 385 - offset = au_io_out_map[offset]; 386 - if (offset == UART_REG_UNMAPPED) 387 - return; 388 - __raw_writel(value, p->membase + (offset << p->regshift)); 389 - } 390 - 391 - /* Au1x00 haven't got a standard divisor latch */ 392 - static int au_serial_dl_read(struct uart_8250_port *up) 393 - { 394 - return __raw_readl(up->port.membase + 0x28); 395 - } 396 - 397 - static void au_serial_dl_write(struct uart_8250_port *up, int value) 398 - { 399 - __raw_writel(value, up->port.membase + 0x28); 400 - } 401 - 402 - #endif 403 343 404 344 static unsigned int hub6_serial_in(struct uart_port *p, int offset) 405 345 { ··· 450 510 p->serial_out = mem32be_serial_out; 451 511 break; 452 512 453 - #ifdef CONFIG_SERIAL_8250_RT288X 454 - case UPIO_AU: 455 - p->serial_in = au_serial_in; 456 - p->serial_out = au_serial_out; 457 - up->dl_read = au_serial_dl_read; 458 - up->dl_write = au_serial_dl_write; 459 - break; 460 - #endif 461 - 462 513 default: 463 514 p->serial_in = io_serial_in; 464 515 p->serial_out = io_serial_out; ··· 539 608 */ 540 609 static int serial8250_em485_init(struct uart_8250_port *p) 541 610 { 611 + /* Port locked to synchronize UART_IER access against the console. */ 612 + lockdep_assert_held_once(&p->port.lock); 613 + 542 614 if (p->em485) 543 615 goto deassert_rts; 544 616 ··· 680 746 serial8250_rpm_get(p); 681 747 682 748 if (p->capabilities & UART_CAP_SLEEP) { 749 + /* Synchronize UART_IER access against the console. */ 750 + spin_lock_irq(&p->port.lock); 683 751 if (p->capabilities & UART_CAP_EFR) { 684 752 lcr = serial_in(p, UART_LCR); 685 753 efr = serial_in(p, UART_EFR); ··· 695 759 serial_out(p, UART_EFR, efr); 696 760 serial_out(p, UART_LCR, lcr); 697 761 } 762 + spin_unlock_irq(&p->port.lock); 698 763 } 699 764 700 765 serial8250_rpm_put(p); ··· 703 766 704 767 static void serial8250_clear_IER(struct uart_8250_port *up) 705 768 { 769 + /* Port locked to synchronize UART_IER access against the console. */ 770 + lockdep_assert_held_once(&up->port.lock); 771 + 706 772 if (up->capabilities & UART_CAP_UUE) 707 773 serial_out(up, UART_IER, UART_IER_UUE); 708 774 else ··· 788 848 static int size_fifo(struct uart_8250_port *up) 789 849 { 790 850 unsigned char old_fcr, old_mcr, old_lcr; 791 - unsigned short old_dl; 851 + u32 old_dl; 792 852 int count; 793 853 794 854 old_lcr = serial_in(up, UART_LCR); ··· 978 1038 unsigned char status1, status2; 979 1039 unsigned int iersave; 980 1040 1041 + /* Port locked to synchronize UART_IER access against the console. */ 1042 + lockdep_assert_held_once(&up->port.lock); 1043 + 981 1044 up->port.type = PORT_16550A; 982 1045 up->capabilities |= UART_CAP_FIFO; 983 1046 ··· 1164 1221 /* 1165 1222 * We really do need global IRQs disabled here - we're going to 1166 1223 * be frobbing the chips IRQ enable register to see if it exists. 1224 + * 1225 + * Synchronize UART_IER access against the console. 1167 1226 */ 1168 1227 spin_lock_irqsave(&port->lock, flags); 1169 1228 ··· 1338 1393 /* forget possible initially masked and pending IRQ */ 1339 1394 probe_irq_off(probe_irq_on()); 1340 1395 save_mcr = serial8250_in_MCR(up); 1396 + /* Synchronize UART_IER access against the console. */ 1397 + spin_lock_irq(&port->lock); 1341 1398 save_ier = serial_in(up, UART_IER); 1399 + spin_unlock_irq(&port->lock); 1342 1400 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2); 1343 1401 1344 1402 irqs = probe_irq_on(); ··· 1353 1405 serial8250_out_MCR(up, 1354 1406 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); 1355 1407 } 1408 + /* Synchronize UART_IER access against the console. */ 1409 + spin_lock_irq(&port->lock); 1356 1410 serial_out(up, UART_IER, UART_IER_ALL_INTR); 1411 + spin_unlock_irq(&port->lock); 1357 1412 serial_in(up, UART_LSR); 1358 1413 serial_in(up, UART_RX); 1359 1414 serial_in(up, UART_IIR); ··· 1366 1415 irq = probe_irq_off(irqs); 1367 1416 1368 1417 serial8250_out_MCR(up, save_mcr); 1418 + /* Synchronize UART_IER access against the console. */ 1419 + spin_lock_irq(&port->lock); 1369 1420 serial_out(up, UART_IER, save_ier); 1421 + spin_unlock_irq(&port->lock); 1370 1422 1371 1423 if (port->flags & UPF_FOURPORT) 1372 1424 outb_p(save_ICP, ICP); ··· 1383 1429 static void serial8250_stop_rx(struct uart_port *port) 1384 1430 { 1385 1431 struct uart_8250_port *up = up_to_u8250p(port); 1432 + 1433 + /* Port locked to synchronize UART_IER access against the console. */ 1434 + lockdep_assert_held_once(&port->lock); 1386 1435 1387 1436 serial8250_rpm_get(up); 1388 1437 ··· 1405 1448 void serial8250_em485_stop_tx(struct uart_8250_port *p) 1406 1449 { 1407 1450 unsigned char mcr = serial8250_in_MCR(p); 1451 + 1452 + /* Port locked to synchronize UART_IER access against the console. */ 1453 + lockdep_assert_held_once(&p->port.lock); 1408 1454 1409 1455 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND) 1410 1456 mcr |= UART_MCR_RTS; ··· 1457 1497 static void __stop_tx_rs485(struct uart_8250_port *p, u64 stop_delay) 1458 1498 { 1459 1499 struct uart_8250_em485 *em485 = p->em485; 1500 + 1501 + /* Port locked to synchronize UART_IER access against the console. */ 1502 + lockdep_assert_held_once(&p->port.lock); 1460 1503 1461 1504 stop_delay += (u64)p->port.rs485.delay_rts_after_send * NSEC_PER_MSEC; 1462 1505 ··· 1640 1677 struct uart_8250_port *up = up_to_u8250p(port); 1641 1678 struct uart_8250_em485 *em485 = up->em485; 1642 1679 1680 + /* Port locked to synchronize UART_IER access against the console. */ 1681 + lockdep_assert_held_once(&port->lock); 1682 + 1643 1683 if (!port->x_char && uart_circ_empty(&port->state->xmit)) 1644 1684 return; 1645 1685 ··· 1670 1704 { 1671 1705 struct uart_8250_port *up = up_to_u8250p(port); 1672 1706 1707 + /* Port locked to synchronize UART_IER access against the console. */ 1708 + lockdep_assert_held_once(&port->lock); 1709 + 1673 1710 /* no MSR capabilities */ 1674 1711 if (up->bugs & UART_BUG_NOMSR) 1675 1712 return; ··· 1686 1717 static void serial8250_enable_ms(struct uart_port *port) 1687 1718 { 1688 1719 struct uart_8250_port *up = up_to_u8250p(port); 1720 + 1721 + /* Port locked to synchronize UART_IER access against the console. */ 1722 + lockdep_assert_held_once(&port->lock); 1689 1723 1690 1724 /* no MSR capabilities */ 1691 1725 if (up->bugs & UART_BUG_NOMSR) ··· 2146 2174 unsigned int ier; 2147 2175 struct uart_8250_port *up = up_to_u8250p(port); 2148 2176 2177 + /* 2178 + * Normally the port is locked to synchronize UART_IER access 2179 + * against the console. However, this function is only used by 2180 + * KDB/KGDB, where it may not be possible to acquire the port 2181 + * lock because all other CPUs are quiesced. The quiescence 2182 + * should allow safe lockless usage here. 2183 + */ 2184 + 2149 2185 serial8250_rpm_get(up); 2150 2186 /* 2151 2187 * First save the IER then disable the interrupts ··· 2199 2219 2200 2220 serial8250_rpm_get(up); 2201 2221 if (port->type == PORT_16C950) { 2202 - /* Wake up and initialize UART */ 2222 + /* 2223 + * Wake up and initialize UART 2224 + * 2225 + * Synchronize UART_IER access against the console. 2226 + */ 2227 + spin_lock_irqsave(&port->lock, flags); 2203 2228 up->acr = 0; 2204 2229 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); 2205 2230 serial_port_out(port, UART_EFR, UART_EFR_ECB); ··· 2214 2229 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); 2215 2230 serial_port_out(port, UART_EFR, UART_EFR_ECB); 2216 2231 serial_port_out(port, UART_LCR, 0); 2232 + spin_unlock_irqrestore(&port->lock, flags); 2217 2233 } 2218 2234 2219 2235 if (port->type == PORT_DA830) { 2220 - /* Reset the port */ 2236 + /* 2237 + * Reset the port 2238 + * 2239 + * Synchronize UART_IER access against the console. 2240 + */ 2241 + spin_lock_irqsave(&port->lock, flags); 2221 2242 serial_port_out(port, UART_IER, 0); 2222 2243 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0); 2244 + spin_unlock_irqrestore(&port->lock, flags); 2223 2245 mdelay(10); 2224 2246 2225 2247 /* Enable Tx, Rx and free run mode */ ··· 2337 2345 * this interrupt whenever the transmitter is idle and 2338 2346 * the interrupt is enabled. Delays are necessary to 2339 2347 * allow register changes to become visible. 2348 + * 2349 + * Synchronize UART_IER access against the console. 2340 2350 */ 2341 2351 spin_lock_irqsave(&port->lock, flags); 2342 2352 ··· 2489 2495 serial8250_rpm_get(up); 2490 2496 /* 2491 2497 * Disable interrupts from this port 2498 + * 2499 + * Synchronize UART_IER access against the console. 2492 2500 */ 2493 2501 spin_lock_irqsave(&port->lock, flags); 2494 2502 up->ier = 0; ··· 2632 2636 2633 2637 if (c_cflag & CSTOPB) 2634 2638 cval |= UART_LCR_STOP; 2635 - if (c_cflag & PARENB) { 2639 + if (c_cflag & PARENB) 2636 2640 cval |= UART_LCR_PARITY; 2637 - if (up->bugs & UART_BUG_PARITY) 2638 - up->fifo_bug = true; 2639 - } 2640 2641 if (!(c_cflag & PARODD)) 2641 2642 cval |= UART_LCR_EPAR; 2642 2643 if (c_cflag & CMSPAR) ··· 2787 2794 /* 2788 2795 * Ok, we're now changing the port state. Do it with 2789 2796 * interrupts disabled. 2797 + * 2798 + * Synchronize UART_IER access against the console. 2790 2799 */ 2791 2800 serial8250_rpm_get(up); 2792 2801 spin_lock_irqsave(&port->lock, flags); ··· 2796 2801 up->lcr = cval; /* Save computed LCR */ 2797 2802 2798 2803 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) { 2799 - /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */ 2800 - if ((baud < 2400 && !up->dma) || up->fifo_bug) { 2804 + if (baud < 2400 && !up->dma) { 2801 2805 up->fcr &= ~UART_FCR_TRIGGER_MASK; 2802 2806 up->fcr |= UART_FCR_TRIGGER_1; 2803 2807 } ··· 2963 2969 { 2964 2970 if (pt->port.mapsize) 2965 2971 return pt->port.mapsize; 2966 - if (pt->port.iotype == UPIO_AU) { 2967 - if (pt->port.type == PORT_RT2880) 2968 - return 0x100; 2969 - return 0x1000; 2970 - } 2971 2972 if (is_omap1_8250(pt)) 2972 2973 return 0x16 << pt->port.regshift; 2973 2974 ··· 3127 3138 struct uart_8250_port *up = up_to_u8250p(uport); 3128 3139 int rxtrig; 3129 3140 3130 - if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 || 3131 - up->fifo_bug) 3141 + if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1) 3132 3142 return -EINVAL; 3133 3143 3134 3144 rxtrig = bytes_to_fcr_rxtrig(up, bytes); ··· 3211 3223 if (flags & UART_CONFIG_TYPE) 3212 3224 autoconfig(up); 3213 3225 3214 - /* if access method is AU, it is a 16550 with a quirk */ 3215 - if (port->type == PORT_16550A && port->iotype == UPIO_AU) 3216 - up->bugs |= UART_BUG_NOMSR; 3217 - 3218 3226 /* HW bugs may trigger IRQ while IIR == NO_INT */ 3219 3227 if (port->type == PORT_TEGRA) 3220 3228 up->bugs |= UART_BUG_NOMSR; ··· 3277 3293 struct uart_port *port = &up->port; 3278 3294 3279 3295 spin_lock_init(&port->lock); 3296 + port->ctrl_id = 0; 3280 3297 port->ops = &serial8250_pops; 3281 3298 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 3282 3299

+1 -1

drivers/tty/serial/8250/8250_pxa.c

··· 60 60 MODULE_DEVICE_TABLE(of, serial_pxa_dt_ids); 61 61 62 62 /* Uart divisor latch write */ 63 - static void serial_pxa_dl_write(struct uart_8250_port *up, int value) 63 + static void serial_pxa_dl_write(struct uart_8250_port *up, u32 value) 64 64 { 65 65 unsigned int dll; 66 66

+136

drivers/tty/serial/8250/8250_rt288x.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * RT288x/Au1xxx driver 4 + */ 5 + 6 + #include <linux/module.h> 7 + #include <linux/io.h> 8 + #include <linux/init.h> 9 + #include <linux/console.h> 10 + #include <linux/serial.h> 11 + #include <linux/serial_8250.h> 12 + 13 + #include "8250.h" 14 + 15 + #define RT288X_DL 0x28 16 + 17 + /* Au1x00/RT288x UART hardware has a weird register layout */ 18 + static const u8 au_io_in_map[7] = { 19 + [UART_RX] = 0, 20 + [UART_IER] = 2, 21 + [UART_IIR] = 3, 22 + [UART_LCR] = 5, 23 + [UART_MCR] = 6, 24 + [UART_LSR] = 7, 25 + [UART_MSR] = 8, 26 + }; 27 + 28 + static const u8 au_io_out_map[5] = { 29 + [UART_TX] = 1, 30 + [UART_IER] = 2, 31 + [UART_FCR] = 4, 32 + [UART_LCR] = 5, 33 + [UART_MCR] = 6, 34 + }; 35 + 36 + static unsigned int au_serial_in(struct uart_port *p, int offset) 37 + { 38 + if (offset >= ARRAY_SIZE(au_io_in_map)) 39 + return UINT_MAX; 40 + offset = au_io_in_map[offset]; 41 + 42 + return __raw_readl(p->membase + (offset << p->regshift)); 43 + } 44 + 45 + static void au_serial_out(struct uart_port *p, int offset, int value) 46 + { 47 + if (offset >= ARRAY_SIZE(au_io_out_map)) 48 + return; 49 + offset = au_io_out_map[offset]; 50 + 51 + __raw_writel(value, p->membase + (offset << p->regshift)); 52 + } 53 + 54 + /* Au1x00 haven't got a standard divisor latch */ 55 + static u32 au_serial_dl_read(struct uart_8250_port *up) 56 + { 57 + return __raw_readl(up->port.membase + RT288X_DL); 58 + } 59 + 60 + static void au_serial_dl_write(struct uart_8250_port *up, u32 value) 61 + { 62 + __raw_writel(value, up->port.membase + RT288X_DL); 63 + } 64 + 65 + int au_platform_setup(struct plat_serial8250_port *p) 66 + { 67 + p->iotype = UPIO_AU; 68 + 69 + p->serial_in = au_serial_in; 70 + p->serial_out = au_serial_out; 71 + p->dl_read = au_serial_dl_read; 72 + p->dl_write = au_serial_dl_write; 73 + 74 + p->mapsize = 0x1000; 75 + 76 + p->bugs |= UART_BUG_NOMSR; 77 + 78 + return 0; 79 + } 80 + EXPORT_SYMBOL_GPL(au_platform_setup); 81 + 82 + int rt288x_setup(struct uart_port *p) 83 + { 84 + struct uart_8250_port *up = up_to_u8250p(p); 85 + 86 + p->iotype = UPIO_AU; 87 + 88 + p->serial_in = au_serial_in; 89 + p->serial_out = au_serial_out; 90 + up->dl_read = au_serial_dl_read; 91 + up->dl_write = au_serial_dl_write; 92 + 93 + p->mapsize = 0x100; 94 + 95 + up->bugs |= UART_BUG_NOMSR; 96 + 97 + return 0; 98 + } 99 + EXPORT_SYMBOL_GPL(rt288x_setup); 100 + 101 + #ifdef CONFIG_SERIAL_8250_CONSOLE 102 + static void au_putc(struct uart_port *port, unsigned char c) 103 + { 104 + unsigned int status; 105 + 106 + au_serial_out(port, UART_TX, c); 107 + 108 + for (;;) { 109 + status = au_serial_in(port, UART_LSR); 110 + if (uart_lsr_tx_empty(status)) 111 + break; 112 + cpu_relax(); 113 + } 114 + } 115 + 116 + static void au_early_serial8250_write(struct console *console, 117 + const char *s, unsigned int count) 118 + { 119 + struct earlycon_device *device = console->data; 120 + struct uart_port *port = &device->port; 121 + 122 + uart_console_write(port, s, count, au_putc); 123 + } 124 + 125 + static int __init early_au_setup(struct earlycon_device *dev, const char *opt) 126 + { 127 + rt288x_setup(&dev->port); 128 + dev->con->write = au_early_serial8250_write; 129 + 130 + return 0; 131 + } 132 + OF_EARLYCON_DECLARE(palmchip, "ralink,rt2880-uart", early_au_setup); 133 + #endif 134 + 135 + MODULE_DESCRIPTION("RT288x/Au1xxx UART driver"); 136 + MODULE_LICENSE("GPL");

+2 -2

drivers/tty/serial/8250/8250_uniphier.c

··· 145 145 * The divisor latch register exists at different address. 146 146 * Override dl_read/write callbacks. 147 147 */ 148 - static int uniphier_serial_dl_read(struct uart_8250_port *up) 148 + static u32 uniphier_serial_dl_read(struct uart_8250_port *up) 149 149 { 150 150 return readl(up->port.membase + UNIPHIER_UART_DLR); 151 151 } 152 152 153 - static void uniphier_serial_dl_write(struct uart_8250_port *up, int value) 153 + static void uniphier_serial_dl_write(struct uart_8250_port *up, u32 value) 154 154 { 155 155 writel(value, up->port.membase + UNIPHIER_UART_DLR); 156 156 }

+9 -7

drivers/tty/serial/8250/Kconfig

··· 71 71 console, you can say N here. 72 72 73 73 config SERIAL_8250_FINTEK 74 - bool "Support for Fintek F81216A LPC to 4 UART RS485 API" 74 + bool "Support for Fintek variants" 75 75 depends on SERIAL_8250 76 76 help 77 - Selecting this option will add support for the RS485 capabilities 78 - of the Fintek F81216A LPC to 4 UART. 77 + Selecting this option will add support for the RS232 and RS485 78 + capabilities of the Fintek F81216A LPC to 4 UART as well similar 79 + variants. 79 80 80 81 If this option is not selected the device will be configured as a 81 - standard 16550A serial port. 82 + standard 16550A serial port, however the device may not function 83 + correctly without this option enabled. 82 84 83 85 If unsure, say N. 84 86 ··· 379 377 If unsure, say N. 380 378 381 379 config SERIAL_8250_FSL 382 - bool "Freescale 16550 UART support" if COMPILE_TEST && !(PPC || ARM || ARM64) 383 - depends on SERIAL_8250_CONSOLE 384 - default PPC || ARM || ARM64 380 + tristate "Freescale 16550 UART support" if COMPILE_TEST && !(PPC || ARM || ARM64) 381 + depends on SERIAL_8250 382 + default SERIAL_8250 if PPC || ARM || ARM64 385 383 help 386 384 Selecting this option enables a workaround for a break-detection 387 385 erratum for Freescale 16550 UARTs in the 8250 driver. It also

+1

drivers/tty/serial/8250/Makefile

··· 35 35 obj-$(CONFIG_SERIAL_8250_EM) += 8250_em.o 36 36 obj-$(CONFIG_SERIAL_8250_IOC3) += 8250_ioc3.o 37 37 obj-$(CONFIG_SERIAL_8250_OMAP) += 8250_omap.o 38 + obj-$(CONFIG_SERIAL_8250_RT288X) += 8250_rt288x.o 38 39 obj-$(CONFIG_SERIAL_8250_LPC18XX) += 8250_lpc18xx.o 39 40 obj-$(CONFIG_SERIAL_8250_MT6577) += 8250_mtk.o 40 41 obj-$(CONFIG_SERIAL_8250_UNIPHIER) += 8250_uniphier.o

+23

drivers/tty/serial/Kconfig

··· 1555 1555 you can alter that using a kernel command line option such as 1556 1556 "console=ttySUPx". 1557 1557 1558 + config SERIAL_NUVOTON_MA35D1 1559 + tristate "Nuvoton MA35D1 family UART support" 1560 + depends on ARCH_MA35 || COMPILE_TEST 1561 + select SERIAL_CORE 1562 + help 1563 + This driver supports Nuvoton MA35D1 family UART ports. If you would 1564 + like to use them, you must answer Y or M to this option. Note that 1565 + for use as console, it must be included in kernel and not as a 1566 + module. If you enable this option, Ma35D1 serial ports in the system 1567 + will be registered as ttyNVTx. 1568 + 1569 + config SERIAL_NUVOTON_MA35D1_CONSOLE 1570 + bool "Console on a Nuvotn MA35D1 family UART port" 1571 + depends on SERIAL_NUVOTON_MA35D1=y 1572 + select SERIAL_CORE_CONSOLE 1573 + help 1574 + Select this options if you'd like to use the UART port0 of the 1575 + Nuvoton MA35D1 family as a console. 1576 + Even if you say Y here, the currently visible virtual console 1577 + (/dev/tty0) will still be used as the system console by default, 1578 + but you can alter that using a kernel command line option such as 1579 + "console=ttyNVTx". 1580 + 1558 1581 endmenu 1559 1582 1560 1583 config SERIAL_MCTRL_GPIO

+4 -2

drivers/tty/serial/Makefile

··· 3 3 # Makefile for the kernel serial device drivers. 4 4 # 5 5 6 - obj-$(CONFIG_SERIAL_CORE) += serial_core.o 6 + obj-$(CONFIG_SERIAL_CORE) += serial_base.o 7 + serial_base-y := serial_core.o serial_base_bus.o serial_ctrl.o serial_port.o 7 8 8 9 obj-$(CONFIG_SERIAL_EARLYCON) += earlycon.o 9 10 obj-$(CONFIG_SERIAL_EARLYCON_SEMIHOST) += earlycon-semihost.o ··· 22 21 obj-$(CONFIG_SERIAL_21285) += 21285.o 23 22 24 23 # Now bring in any enabled 8250/16450/16550 type drivers. 25 - obj-$(CONFIG_SERIAL_8250) += 8250/ 24 + obj-y += 8250/ 26 25 27 26 obj-$(CONFIG_SERIAL_AMBA_PL010) += amba-pl010.o 28 27 obj-$(CONFIG_SERIAL_AMBA_PL011) += amba-pl011.o ··· 94 93 95 94 obj-$(CONFIG_SERIAL_KGDB_NMI) += kgdb_nmi.o 96 95 obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o 96 + obj-$(CONFIG_SERIAL_NUVOTON_MA35D1) += ma35d1_serial.o

+7

drivers/tty/serial/amba-pl011.c

··· 2166 2166 * ----------^----------^----------^----------^----- 2167 2167 */ 2168 2168 pl011_write_lcr_h(uap, lcr_h); 2169 + 2170 + /* 2171 + * Receive was disabled by pl011_disable_uart during shutdown. 2172 + * Need to reenable receive if you need to use a tty_driver 2173 + * returns from tty_find_polling_driver() after a port shutdown. 2174 + */ 2175 + old_cr |= UART011_CR_RXE; 2169 2176 pl011_write(old_cr, uap, REG_CR); 2170 2177 2171 2178 spin_unlock_irqrestore(&port->lock, flags);

+4 -5

drivers/tty/serial/atmel_serial.c

··· 868 868 dmaengine_terminate_all(chan); 869 869 uart_xmit_advance(port, atmel_port->tx_len); 870 870 871 - spin_lock_irq(&atmel_port->lock_tx); 871 + spin_lock(&atmel_port->lock_tx); 872 872 async_tx_ack(atmel_port->desc_tx); 873 873 atmel_port->cookie_tx = -EINVAL; 874 874 atmel_port->desc_tx = NULL; 875 - spin_unlock_irq(&atmel_port->lock_tx); 875 + spin_unlock(&atmel_port->lock_tx); 876 876 877 877 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 878 878 uart_write_wakeup(port); ··· 3006 3006 { 3007 3007 struct uart_port *port = platform_get_drvdata(pdev); 3008 3008 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 3009 - int ret = 0; 3010 3009 3011 3010 tasklet_kill(&atmel_port->tasklet_rx); 3012 3011 tasklet_kill(&atmel_port->tasklet_tx); 3013 3012 3014 3013 device_init_wakeup(&pdev->dev, 0); 3015 3014 3016 - ret = uart_remove_one_port(&atmel_uart, port); 3015 + uart_remove_one_port(&atmel_uart, port); 3017 3016 3018 3017 kfree(atmel_port->rx_ring.buf); 3019 3018 ··· 3022 3023 3023 3024 pdev->dev.of_node = NULL; 3024 3025 3025 - return ret; 3026 + return 0; 3026 3027 } 3027 3028 3028 3029 static SIMPLE_DEV_PM_OPS(atmel_serial_pm_ops, atmel_serial_suspend,

+3 -1

drivers/tty/serial/clps711x.c

··· 514 514 { 515 515 struct clps711x_port *s = platform_get_drvdata(pdev); 516 516 517 - return uart_remove_one_port(&clps711x_uart, &s->port); 517 + uart_remove_one_port(&clps711x_uart, &s->port); 518 + 519 + return 0; 518 520 } 519 521 520 522 static const struct of_device_id __maybe_unused clps711x_uart_dt_ids[] = {

+4 -1

drivers/tty/serial/cpm_uart/cpm_uart_core.c

··· 1431 1431 static int cpm_uart_remove(struct platform_device *ofdev) 1432 1432 { 1433 1433 struct uart_cpm_port *pinfo = platform_get_drvdata(ofdev); 1434 - return uart_remove_one_port(&cpm_reg, &pinfo->port); 1434 + 1435 + uart_remove_one_port(&cpm_reg, &pinfo->port); 1436 + 1437 + return 0; 1435 1438 } 1436 1439 1437 1440 static const struct of_device_id cpm_uart_match[] = {

+53 -4

drivers/tty/serial/fsl_lpuart.c

··· 238 238 239 239 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 240 240 #define DMA_RX_TIMEOUT (10) 241 + #define DMA_RX_IDLE_CHARS 8 241 242 #define UART_AUTOSUSPEND_TIMEOUT 3000 242 243 243 244 #define DRIVER_NAME "fsl-lpuart" ··· 283 282 struct scatterlist rx_sgl, tx_sgl[2]; 284 283 struct circ_buf rx_ring; 285 284 int rx_dma_rng_buf_len; 285 + int last_residue; 286 286 unsigned int dma_tx_nents; 287 287 wait_queue_head_t dma_wait; 288 288 bool is_cs7; /* Set to true when character size is 7 */ ··· 333 331 .devtype = IMX8QXP_LPUART, 334 332 .iotype = UPIO_MEM32, 335 333 .reg_off = IMX_REG_OFF, 336 - .rx_watermark = 31, 334 + .rx_watermark = 7, /* A lower watermark is ideal for low baud rates. */ 337 335 }; 338 336 static struct lpuart_soc_data imxrt1050_data = { 339 337 .devtype = IMXRT1050_LPUART, ··· 1257 1255 sport->port.icount.rx += copied; 1258 1256 } 1259 1257 1258 + sport->last_residue = state.residue; 1259 + 1260 1260 exit: 1261 1261 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, 1262 1262 DMA_FROM_DEVICE); ··· 1276 1272 lpuart_copy_rx_to_tty(sport); 1277 1273 } 1278 1274 1275 + /* 1276 + * Timer function to simulate the hardware EOP (End Of Package) event. 1277 + * The timer callback is to check for new RX data and copy to TTY buffer. 1278 + * If no new data are received since last interval, the EOP condition is 1279 + * met, complete the DMA transfer by copying the data. Otherwise, just 1280 + * restart timer. 1281 + */ 1279 1282 static void lpuart_timer_func(struct timer_list *t) 1280 1283 { 1281 1284 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); 1285 + enum dma_status dmastat; 1286 + struct dma_chan *chan = sport->dma_rx_chan; 1287 + struct circ_buf *ring = &sport->rx_ring; 1288 + struct dma_tx_state state; 1289 + unsigned long flags; 1290 + int count; 1282 1291 1283 - lpuart_copy_rx_to_tty(sport); 1292 + dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); 1293 + if (dmastat == DMA_ERROR) { 1294 + dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1295 + return; 1296 + } 1297 + 1298 + ring->head = sport->rx_sgl.length - state.residue; 1299 + count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length); 1300 + 1301 + /* Check if new data received before copying */ 1302 + if ((count != 0) && (sport->last_residue == state.residue)) 1303 + lpuart_copy_rx_to_tty(sport); 1304 + else 1305 + mod_timer(&sport->lpuart_timer, 1306 + jiffies + sport->dma_rx_timeout); 1307 + 1308 + if (spin_trylock_irqsave(&sport->port.lock, flags)) { 1309 + sport->last_residue = state.residue; 1310 + spin_unlock_irqrestore(&sport->port.lock, flags); 1311 + } 1284 1312 } 1285 1313 1286 1314 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) ··· 1333 1297 */ 1334 1298 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 1335 1299 sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len)); 1300 + sport->rx_dma_rng_buf_len = max_t(int, 1301 + sport->rxfifo_size * 2, 1302 + sport->rx_dma_rng_buf_len); 1303 + /* 1304 + * Keep this condition check in case rxfifo_size is unavailable 1305 + * for some SoCs. 1306 + */ 1336 1307 if (sport->rx_dma_rng_buf_len < 16) 1337 1308 sport->rx_dma_rng_buf_len = 16; 1309 + 1310 + sport->last_residue = 0; 1311 + sport->dma_rx_timeout = max(nsecs_to_jiffies( 1312 + sport->port.frame_time * DMA_RX_IDLE_CHARS), 1UL); 1338 1313 1339 1314 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 1340 1315 if (!ring->buf) ··· 1736 1689 if (!sport->dma_rx_chan) 1737 1690 goto err; 1738 1691 1692 + /* set default Rx DMA timeout */ 1693 + sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1694 + 1739 1695 ret = lpuart_start_rx_dma(sport); 1740 1696 if (ret) 1741 1697 goto err; 1742 1698 1743 - /* set Rx DMA timeout */ 1744 - sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1745 1699 if (!sport->dma_rx_timeout) 1746 1700 sport->dma_rx_timeout = 1; 1747 1701 ··· 2724 2676 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 2725 2677 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup); 2726 2678 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); 2679 + OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup); 2727 2680 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup); 2728 2681 OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup); 2729 2682 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);

+16 -6

drivers/tty/serial/imx.c

··· 369 369 sport->idle_counter = 0; 370 370 } 371 371 372 + static void imx_uart_disable_loopback_rs485(struct imx_port *sport) 373 + { 374 + unsigned int uts; 375 + 376 + /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */ 377 + uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); 378 + uts &= ~UTS_LOOP; 379 + imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 380 + } 381 + 372 382 /* called with port.lock taken and irqs off */ 373 383 static void imx_uart_start_rx(struct uart_port *port) 374 384 { ··· 400 390 /* Write UCR2 first as it includes RXEN */ 401 391 imx_uart_writel(sport, ucr2, UCR2); 402 392 imx_uart_writel(sport, ucr1, UCR1); 393 + imx_uart_disable_loopback_rs485(sport); 403 394 } 404 395 405 396 /* called with port.lock taken and irqs off */ ··· 1433 1422 int retval; 1434 1423 unsigned long flags; 1435 1424 int dma_is_inited = 0; 1436 - u32 ucr1, ucr2, ucr3, ucr4, uts; 1425 + u32 ucr1, ucr2, ucr3, ucr4; 1437 1426 1438 1427 retval = clk_prepare_enable(sport->clk_per); 1439 1428 if (retval) ··· 1532 1521 imx_uart_writel(sport, ucr2, UCR2); 1533 1522 } 1534 1523 1535 - /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */ 1536 - uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); 1537 - uts &= ~UTS_LOOP; 1538 - imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 1524 + imx_uart_disable_loopback_rs485(sport); 1539 1525 1540 1526 spin_unlock_irqrestore(&sport->port.lock, flags); 1541 1527 ··· 2475 2467 { 2476 2468 struct imx_port *sport = platform_get_drvdata(pdev); 2477 2469 2478 - return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2470 + uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2471 + 2472 + return 0; 2479 2473 } 2480 2474 2481 2475 static void imx_uart_restore_context(struct imx_port *sport)

+3 -1

drivers/tty/serial/lantiq.c

··· 890 890 { 891 891 struct uart_port *port = platform_get_drvdata(pdev); 892 892 893 - return uart_remove_one_port(&lqasc_reg, port); 893 + uart_remove_one_port(&lqasc_reg, port); 894 + 895 + return 0; 894 896 } 895 897 896 898 static const struct ltq_soc_data soc_data_lantiq = {

+821

drivers/tty/serial/ma35d1_serial.c

··· 1 + // SPDX-License-Identifier: GPL-2.0+ 2 + /* 3 + * MA35D1 serial driver 4 + * Copyright (C) 2023 Nuvoton Technology Corp. 5 + */ 6 + 7 + #include <linux/bitfield.h> 8 + #include <linux/clk.h> 9 + #include <linux/delay.h> 10 + #include <linux/of.h> 11 + #include <linux/of_platform.h> 12 + #include <linux/iopoll.h> 13 + #include <linux/serial_core.h> 14 + #include <linux/slab.h> 15 + #include <linux/tty_flip.h> 16 + #include <linux/units.h> 17 + 18 + #define MA35_UART_NR 17 19 + 20 + #define MA35_RBR_REG 0x00 21 + #define MA35_THR_REG 0x00 22 + #define MA35_IER_REG 0x04 23 + #define MA35_FCR_REG 0x08 24 + #define MA35_LCR_REG 0x0C 25 + #define MA35_MCR_REG 0x10 26 + #define MA35_MSR_REG 0x14 27 + #define MA35_FSR_REG 0x18 28 + #define MA35_ISR_REG 0x1C 29 + #define MA35_TOR_REG 0x20 30 + #define MA35_BAUD_REG 0x24 31 + #define MA35_ALTCTL_REG 0x2C 32 + #define MA35_FUN_SEL_REG 0x30 33 + #define MA35_WKCTL_REG 0x40 34 + #define MA35_WKSTS_REG 0x44 35 + 36 + /* MA35_IER_REG - Interrupt Enable Register */ 37 + #define MA35_IER_RDA_IEN BIT(0) /* RBR Available Interrupt Enable */ 38 + #define MA35_IER_THRE_IEN BIT(1) /* THR Empty Interrupt Enable */ 39 + #define MA35_IER_RLS_IEN BIT(2) /* RX Line Status Interrupt Enable */ 40 + #define MA35_IER_RTO_IEN BIT(4) /* RX Time-out Interrupt Enable */ 41 + #define MA35_IER_BUFERR_IEN BIT(5) /* Buffer Error Interrupt Enable */ 42 + #define MA35_IER_TIME_OUT_EN BIT(11) /* RX Buffer Time-out Counter Enable */ 43 + #define MA35_IER_AUTO_RTS BIT(12) /* nRTS Auto-flow Control Enable */ 44 + #define MA35_IER_AUTO_CTS BIT(13) /* nCTS Auto-flow Control Enable */ 45 + 46 + /* MA35_FCR_REG - FIFO Control Register */ 47 + #define MA35_FCR_RFR BIT(1) /* RX Field Software Reset */ 48 + #define MA35_FCR_TFR BIT(2) /* TX Field Software Reset */ 49 + #define MA35_FCR_RFITL_MASK GENMASK(7, 4) /* RX FIFO Interrupt Trigger Level */ 50 + #define MA35_FCR_RFITL_1BYTE FIELD_PREP(MA35_FCR_RFITL_MASK, 0) 51 + #define MA35_FCR_RFITL_4BYTES FIELD_PREP(MA35_FCR_RFITL_MASK, 1) 52 + #define MA35_FCR_RFITL_8BYTES FIELD_PREP(MA35_FCR_RFITL_MASK, 2) 53 + #define MA35_FCR_RFITL_14BYTES FIELD_PREP(MA35_FCR_RFITL_MASK, 3) 54 + #define MA35_FCR_RFITL_30BYTES FIELD_PREP(MA35_FCR_RFITL_MASK, 4) 55 + #define MA35_FCR_RTSTL_MASK GENMASK(19, 16) /* nRTS Trigger Level */ 56 + #define MA35_FCR_RTSTL_1BYTE FIELD_PREP(MA35_FCR_RTSTL_MASK, 0) 57 + #define MA35_FCR_RTSTL_4BYTES FIELD_PREP(MA35_FCR_RTSTL_MASK, 1) 58 + #define MA35_FCR_RTSTL_8BYTES FIELD_PREP(MA35_FCR_RTSTL_MASK, 2) 59 + #define MA35_FCR_RTSTL_14BYTES FIELD_PREP(MA35_FCR_RTSTL_MASK, 3) 60 + #define MA35_FCR_RTSTLL_30BYTES FIELD_PREP(MA35_FCR_RTSTL_MASK, 4) 61 + 62 + /* MA35_LCR_REG - Line Control Register */ 63 + #define MA35_LCR_NSB BIT(2) /* Number of “STOP Bit” */ 64 + #define MA35_LCR_PBE BIT(3) /* Parity Bit Enable */ 65 + #define MA35_LCR_EPE BIT(4) /* Even Parity Enable */ 66 + #define MA35_LCR_SPE BIT(5) /* Stick Parity Enable */ 67 + #define MA35_LCR_BREAK BIT(6) /* Break Control */ 68 + #define MA35_LCR_WLS_MASK GENMASK(1, 0) /* Word Length Selection */ 69 + #define MA35_LCR_WLS_5BITS FIELD_PREP(MA35_LCR_WLS_MASK, 0) 70 + #define MA35_LCR_WLS_6BITS FIELD_PREP(MA35_LCR_WLS_MASK, 1) 71 + #define MA35_LCR_WLS_7BITS FIELD_PREP(MA35_LCR_WLS_MASK, 2) 72 + #define MA35_LCR_WLS_8BITS FIELD_PREP(MA35_LCR_WLS_MASK, 3) 73 + 74 + /* MA35_MCR_REG - Modem Control Register */ 75 + #define MA35_MCR_RTS_CTRL BIT(1) /* nRTS Signal Control */ 76 + #define MA35_MCR_RTSACTLV BIT(9) /* nRTS Pin Active Level */ 77 + #define MA35_MCR_RTSSTS BIT(13) /* nRTS Pin Status (Read Only) */ 78 + 79 + /* MA35_MSR_REG - Modem Status Register */ 80 + #define MA35_MSR_CTSDETF BIT(0) /* Detect nCTS State Change Flag */ 81 + #define MA35_MSR_CTSSTS BIT(4) /* nCTS Pin Status (Read Only) */ 82 + #define MA35_MSR_CTSACTLV BIT(8) /* nCTS Pin Active Level */ 83 + 84 + /* MA35_FSR_REG - FIFO Status Register */ 85 + #define MA35_FSR_RX_OVER_IF BIT(0) /* RX Overflow Error Interrupt Flag */ 86 + #define MA35_FSR_PEF BIT(4) /* Parity Error Flag*/ 87 + #define MA35_FSR_FEF BIT(5) /* Framing Error Flag */ 88 + #define MA35_FSR_BIF BIT(6) /* Break Interrupt Flag */ 89 + #define MA35_FSR_RX_EMPTY BIT(14) /* Receiver FIFO Empty (Read Only) */ 90 + #define MA35_FSR_RX_FULL BIT(15) /* Receiver FIFO Full (Read Only) */ 91 + #define MA35_FSR_TX_EMPTY BIT(22) /* Transmitter FIFO Empty (Read Only) */ 92 + #define MA35_FSR_TX_FULL BIT(23) /* Transmitter FIFO Full (Read Only) */ 93 + #define MA35_FSR_TX_OVER_IF BIT(24) /* TX Overflow Error Interrupt Flag */ 94 + #define MA35_FSR_TE_FLAG BIT(28) /* Transmitter Empty Flag (Read Only) */ 95 + #define MA35_FSR_RXPTR_MSK GENMASK(13, 8) /* TX FIFO Pointer mask */ 96 + #define MA35_FSR_TXPTR_MSK GENMASK(21, 16) /* RX FIFO Pointer mask */ 97 + 98 + /* MA35_ISR_REG - Interrupt Status Register */ 99 + #define MA35_ISR_RDA_IF BIT(0) /* RBR Available Interrupt Flag */ 100 + #define MA35_ISR_THRE_IF BIT(1) /* THR Empty Interrupt Flag */ 101 + #define MA35_ISR_RLSIF BIT(2) /* Receive Line Interrupt Flag */ 102 + #define MA35_ISR_MODEMIF BIT(3) /* MODEM Interrupt Flag */ 103 + #define MA35_ISR_RXTO_IF BIT(4) /* RX Time-out Interrupt Flag */ 104 + #define MA35_ISR_BUFEIF BIT(5) /* Buffer Error Interrupt Flag */ 105 + #define MA35_ISR_WK_IF BIT(6) /* UART Wake-up Interrupt Flag */ 106 + #define MA35_ISR_RDAINT BIT(8) /* RBR Available Interrupt Indicator */ 107 + #define MA35_ISR_THRE_INT BIT(9) /* THR Empty Interrupt Indicator */ 108 + #define MA35_ISR_ALL 0xFFFFFFFF 109 + 110 + /* MA35_BAUD_REG - Baud Rate Divider Register */ 111 + #define MA35_BAUD_MODE_MASK GENMASK(29, 28) 112 + #define MA35_BAUD_MODE0 FIELD_PREP(MA35_BAUD_MODE_MASK, 0) 113 + #define MA35_BAUD_MODE1 FIELD_PREP(MA35_BAUD_MODE_MASK, 2) 114 + #define MA35_BAUD_MODE2 FIELD_PREP(MA35_BAUD_MODE_MASK, 3) 115 + #define MA35_BAUD_MASK GENMASK(15, 0) 116 + 117 + /* MA35_ALTCTL_REG - Alternate Control/Status Register */ 118 + #define MA35_ALTCTL_RS485AUD BIT(10) /* RS-485 Auto Direction Function */ 119 + 120 + /* MA35_FUN_SEL_REG - Function Select Register */ 121 + #define MA35_FUN_SEL_MASK GENMASK(2, 0) 122 + #define MA35_FUN_SEL_UART FIELD_PREP(MA35_FUN_SEL_MASK, 0) 123 + #define MA35_FUN_SEL_RS485 FIELD_PREP(MA35_FUN_SEL_MASK, 3) 124 + 125 + /* The constrain for MA35D1 UART baud rate divider */ 126 + #define MA35_BAUD_DIV_MAX 0xFFFF 127 + #define MA35_BAUD_DIV_MIN 11 128 + 129 + /* UART FIFO depth */ 130 + #define MA35_UART_FIFO_DEPTH 32 131 + /* UART console clock */ 132 + #define MA35_UART_CONSOLE_CLK (24 * HZ_PER_MHZ) 133 + /* UART register ioremap size */ 134 + #define MA35_UART_REG_SIZE 0x100 135 + /* Rx Timeout */ 136 + #define MA35_UART_RX_TOUT 0x40 137 + 138 + #define MA35_IER_CONFIG (MA35_IER_RTO_IEN | MA35_IER_RDA_IEN | \ 139 + MA35_IER_TIME_OUT_EN | MA35_IER_BUFERR_IEN) 140 + 141 + #define MA35_ISR_IF_CHECK (MA35_ISR_RDA_IF | MA35_ISR_RXTO_IF | \ 142 + MA35_ISR_THRE_INT | MA35_ISR_BUFEIF) 143 + 144 + #define MA35_FSR_TX_BOTH_EMPTY (MA35_FSR_TE_FLAG | MA35_FSR_TX_EMPTY) 145 + 146 + static struct uart_driver ma35d1serial_reg; 147 + 148 + struct uart_ma35d1_port { 149 + struct uart_port port; 150 + struct clk *clk; 151 + u16 capabilities; /* port capabilities */ 152 + u8 ier; 153 + u8 lcr; 154 + u8 mcr; 155 + u32 baud_rate; 156 + u32 console_baud_rate; 157 + u32 console_line; 158 + u32 console_int; 159 + }; 160 + 161 + static struct uart_ma35d1_port ma35d1serial_ports[MA35_UART_NR]; 162 + 163 + static struct uart_ma35d1_port *to_ma35d1_uart_port(struct uart_port *uart) 164 + { 165 + return container_of(uart, struct uart_ma35d1_port, port); 166 + } 167 + 168 + static u32 serial_in(struct uart_ma35d1_port *p, u32 offset) 169 + { 170 + return readl_relaxed(p->port.membase + offset); 171 + } 172 + 173 + static void serial_out(struct uart_ma35d1_port *p, u32 offset, u32 value) 174 + { 175 + writel_relaxed(value, p->port.membase + offset); 176 + } 177 + 178 + static void __stop_tx(struct uart_ma35d1_port *p) 179 + { 180 + u32 ier; 181 + 182 + ier = serial_in(p, MA35_IER_REG); 183 + if (ier & MA35_IER_THRE_IEN) 184 + serial_out(p, MA35_IER_REG, ier & ~MA35_IER_THRE_IEN); 185 + } 186 + 187 + static void ma35d1serial_stop_tx(struct uart_port *port) 188 + { 189 + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); 190 + 191 + __stop_tx(up); 192 + } 193 + 194 + static void transmit_chars(struct uart_ma35d1_port *up) 195 + { 196 + u32 count; 197 + u8 ch; 198 + 199 + if (uart_tx_stopped(&up->port)) { 200 + ma35d1serial_stop_tx(&up->port); 201 + return; 202 + } 203 + count = MA35_UART_FIFO_DEPTH - FIELD_GET(MA35_FSR_TXPTR_MSK, 204 + serial_in(up, MA35_FSR_REG)); 205 + uart_port_tx_limited(&up->port, ch, count, 206 + !(serial_in(up, MA35_FSR_REG) & MA35_FSR_TX_FULL), 207 + serial_out(up, MA35_THR_REG, ch), 208 + ({})); 209 + } 210 + 211 + static void ma35d1serial_start_tx(struct uart_port *port) 212 + { 213 + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); 214 + u32 ier; 215 + 216 + ier = serial_in(up, MA35_IER_REG); 217 + serial_out(up, MA35_IER_REG, ier & ~MA35_IER_THRE_IEN); 218 + transmit_chars(up); 219 + serial_out(up, MA35_IER_REG, ier | MA35_IER_THRE_IEN); 220 + } 221 + 222 + static void ma35d1serial_stop_rx(struct uart_port *port) 223 + { 224 + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); 225 + u32 ier; 226 + 227 + ier = serial_in(up, MA35_IER_REG); 228 + ier &= ~MA35_IER_RDA_IEN; 229 + serial_out(up, MA35_IER_REG, ier); 230 + } 231 + 232 + static void receive_chars(struct uart_ma35d1_port *up) 233 + { 234 + int max_count = 256; 235 + u8 ch, flag; 236 + u32 fsr; 237 + 238 + fsr = serial_in(up, MA35_FSR_REG); 239 + do { 240 + flag = TTY_NORMAL; 241 + up->port.icount.rx++; 242 + 243 + if (unlikely(fsr & (MA35_FSR_BIF | MA35_FSR_FEF | 244 + MA35_FSR_PEF | MA35_FSR_RX_OVER_IF))) { 245 + if (fsr & MA35_FSR_BIF) { 246 + up->port.icount.brk++; 247 + if (uart_handle_break(&up->port)) 248 + continue; 249 + } 250 + if (fsr & MA35_FSR_FEF) 251 + up->port.icount.frame++; 252 + if (fsr & MA35_FSR_PEF) 253 + up->port.icount.parity++; 254 + if (fsr & MA35_FSR_RX_OVER_IF) 255 + up->port.icount.overrun++; 256 + 257 + serial_out(up, MA35_FSR_REG, 258 + fsr & (MA35_FSR_BIF | MA35_FSR_FEF | 259 + MA35_FSR_PEF | MA35_FSR_RX_OVER_IF)); 260 + if (fsr & MA35_FSR_BIF) 261 + flag = TTY_BREAK; 262 + else if (fsr & MA35_FSR_PEF) 263 + flag = TTY_PARITY; 264 + else if (fsr & MA35_FSR_FEF) 265 + flag = TTY_FRAME; 266 + } 267 + 268 + ch = serial_in(up, MA35_RBR_REG); 269 + if (uart_handle_sysrq_char(&up->port, ch)) 270 + continue; 271 + 272 + spin_lock(&up->port.lock); 273 + uart_insert_char(&up->port, fsr, MA35_FSR_RX_OVER_IF, ch, flag); 274 + spin_unlock(&up->port.lock); 275 + 276 + fsr = serial_in(up, MA35_FSR_REG); 277 + } while (!(fsr & MA35_FSR_RX_EMPTY) && (max_count-- > 0)); 278 + 279 + spin_lock(&up->port.lock); 280 + tty_flip_buffer_push(&up->port.state->port); 281 + spin_unlock(&up->port.lock); 282 + } 283 + 284 + static irqreturn_t ma35d1serial_interrupt(int irq, void *dev_id) 285 + { 286 + struct uart_port *port = dev_id; 287 + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); 288 + u32 isr, fsr; 289 + 290 + isr = serial_in(up, MA35_ISR_REG); 291 + fsr = serial_in(up, MA35_FSR_REG); 292 + 293 + if (!(isr & MA35_ISR_IF_CHECK)) 294 + return IRQ_NONE; 295 + 296 + if (isr & (MA35_ISR_RDA_IF | MA35_ISR_RXTO_IF)) 297 + receive_chars(up); 298 + if (isr & MA35_ISR_THRE_INT) 299 + transmit_chars(up); 300 + if (fsr & MA35_FSR_TX_OVER_IF) 301 + serial_out(up, MA35_FSR_REG, MA35_FSR_TX_OVER_IF); 302 + 303 + return IRQ_HANDLED; 304 + } 305 + 306 + static u32 ma35d1serial_tx_empty(struct uart_port *port) 307 + { 308 + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); 309 + u32 fsr; 310 + 311 + fsr = serial_in(up, MA35_FSR_REG); 312 + if ((fsr & MA35_FSR_TX_BOTH_EMPTY) == MA35_FSR_TX_BOTH_EMPTY) 313 + return TIOCSER_TEMT; 314 + else 315 + return 0; 316 + } 317 + 318 + static u32 ma35d1serial_get_mctrl(struct uart_port *port) 319 + { 320 + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); 321 + u32 status; 322 + u32 ret = 0; 323 + 324 + status = serial_in(up, MA35_MSR_REG); 325 + if (!(status & MA35_MSR_CTSSTS)) 326 + ret |= TIOCM_CTS; 327 + return ret; 328 + } 329 + 330 + static void ma35d1serial_set_mctrl(struct uart_port *port, u32 mctrl) 331 + { 332 + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); 333 + u32 mcr, msr, ier; 334 + 335 + mcr = serial_in(up, MA35_MCR_REG); 336 + mcr &= ~MA35_MCR_RTS_CTRL; 337 + 338 + if (mctrl & TIOCM_RTS) 339 + mcr |= MA35_MCR_RTSACTLV; 340 + else 341 + mcr &= ~MA35_MCR_RTSACTLV; 342 + 343 + if (up->mcr & UART_MCR_AFE) { 344 + ier = serial_in(up, MA35_IER_REG); 345 + ier |= MA35_IER_AUTO_RTS | MA35_IER_AUTO_CTS; 346 + serial_out(up, MA35_IER_REG, ier); 347 + up->port.flags |= UPF_HARD_FLOW; 348 + } else { 349 + ier = serial_in(up, MA35_IER_REG); 350 + ier &= ~(MA35_IER_AUTO_RTS | MA35_IER_AUTO_CTS); 351 + serial_out(up, MA35_IER_REG, ier); 352 + up->port.flags &= ~UPF_HARD_FLOW; 353 + } 354 + 355 + msr = serial_in(up, MA35_MSR_REG); 356 + msr |= MA35_MSR_CTSACTLV; 357 + serial_out(up, MA35_MSR_REG, msr); 358 + serial_out(up, MA35_MCR_REG, mcr); 359 + } 360 + 361 + static void ma35d1serial_break_ctl(struct uart_port *port, int break_state) 362 + { 363 + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); 364 + unsigned long flags; 365 + u32 lcr; 366 + 367 + spin_lock_irqsave(&up->port.lock, flags); 368 + lcr = serial_in(up, MA35_LCR_REG); 369 + if (break_state != 0) 370 + lcr |= MA35_LCR_BREAK; 371 + else 372 + lcr &= ~MA35_LCR_BREAK; 373 + serial_out(up, MA35_LCR_REG, lcr); 374 + spin_unlock_irqrestore(&up->port.lock, flags); 375 + } 376 + 377 + static int ma35d1serial_startup(struct uart_port *port) 378 + { 379 + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); 380 + u32 fcr; 381 + int retval; 382 + 383 + /* Reset FIFO */ 384 + serial_out(up, MA35_FCR_REG, MA35_FCR_TFR | MA35_FCR_RFR); 385 + 386 + /* Clear pending interrupts */ 387 + serial_out(up, MA35_ISR_REG, MA35_ISR_ALL); 388 + 389 + retval = request_irq(port->irq, ma35d1serial_interrupt, 0, 390 + dev_name(port->dev), port); 391 + if (retval) { 392 + dev_err(up->port.dev, "request irq failed.\n"); 393 + return retval; 394 + } 395 + 396 + fcr = serial_in(up, MA35_FCR_REG); 397 + fcr |= MA35_FCR_RFITL_4BYTES | MA35_FCR_RTSTL_8BYTES; 398 + serial_out(up, MA35_FCR_REG, fcr); 399 + serial_out(up, MA35_LCR_REG, MA35_LCR_WLS_8BITS); 400 + serial_out(up, MA35_TOR_REG, MA35_UART_RX_TOUT); 401 + serial_out(up, MA35_IER_REG, MA35_IER_CONFIG); 402 + return 0; 403 + } 404 + 405 + static void ma35d1serial_shutdown(struct uart_port *port) 406 + { 407 + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); 408 + 409 + serial_out(up, MA35_IER_REG, 0); 410 + free_irq(port->irq, port); 411 + } 412 + 413 + static void ma35d1serial_set_termios(struct uart_port *port, 414 + struct ktermios *termios, 415 + const struct ktermios *old) 416 + { 417 + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); 418 + unsigned long flags; 419 + u32 baud, quot; 420 + u32 lcr = 0; 421 + 422 + lcr = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 423 + 424 + if (termios->c_cflag & CSTOPB) 425 + lcr |= MA35_LCR_NSB; 426 + if (termios->c_cflag & PARENB) 427 + lcr |= MA35_LCR_PBE; 428 + if (!(termios->c_cflag & PARODD)) 429 + lcr |= MA35_LCR_EPE; 430 + if (termios->c_cflag & CMSPAR) 431 + lcr |= MA35_LCR_SPE; 432 + 433 + baud = uart_get_baud_rate(port, termios, old, 434 + port->uartclk / MA35_BAUD_DIV_MAX, 435 + port->uartclk / MA35_BAUD_DIV_MIN); 436 + 437 + /* MA35D1 UART baud rate equation: baudrate = UART_CLK / (quot + 2) */ 438 + quot = (port->uartclk / baud) - 2; 439 + 440 + /* 441 + * Ok, we're now changing the port state. Do it with 442 + * interrupts disabled. 443 + */ 444 + spin_lock_irqsave(&up->port.lock, flags); 445 + 446 + up->port.read_status_mask = MA35_FSR_RX_OVER_IF; 447 + if (termios->c_iflag & INPCK) 448 + up->port.read_status_mask |= MA35_FSR_FEF | MA35_FSR_PEF; 449 + if (termios->c_iflag & (BRKINT | PARMRK)) 450 + up->port.read_status_mask |= MA35_FSR_BIF; 451 + 452 + /* Characteres to ignore */ 453 + up->port.ignore_status_mask = 0; 454 + if (termios->c_iflag & IGNPAR) 455 + up->port.ignore_status_mask |= MA35_FSR_FEF | MA35_FSR_PEF; 456 + if (termios->c_iflag & IGNBRK) { 457 + up->port.ignore_status_mask |= MA35_FSR_BIF; 458 + /* 459 + * If we're ignoring parity and break indicators, 460 + * ignore overruns too (for real raw support). 461 + */ 462 + if (termios->c_iflag & IGNPAR) 463 + up->port.ignore_status_mask |= MA35_FSR_RX_OVER_IF; 464 + } 465 + if (termios->c_cflag & CRTSCTS) 466 + up->mcr |= UART_MCR_AFE; 467 + else 468 + up->mcr &= ~UART_MCR_AFE; 469 + 470 + uart_update_timeout(port, termios->c_cflag, baud); 471 + 472 + ma35d1serial_set_mctrl(&up->port, up->port.mctrl); 473 + 474 + serial_out(up, MA35_BAUD_REG, MA35_BAUD_MODE2 | FIELD_PREP(MA35_BAUD_MASK, quot)); 475 + 476 + serial_out(up, MA35_LCR_REG, lcr); 477 + 478 + spin_unlock_irqrestore(&up->port.lock, flags); 479 + } 480 + 481 + static const char *ma35d1serial_type(struct uart_port *port) 482 + { 483 + return "ma35d1-uart"; 484 + } 485 + 486 + static void ma35d1serial_config_port(struct uart_port *port, int flags) 487 + { 488 + /* 489 + * Driver core for serial ports forces a non-zero value for port type. 490 + * Write an arbitrary value here to accommodate the serial core driver, 491 + * as ID part of UAPI is redundant. 492 + */ 493 + port->type = 1; 494 + } 495 + 496 + static int ma35d1serial_verify_port(struct uart_port *port, struct serial_struct *ser) 497 + { 498 + if (port->type != PORT_UNKNOWN && ser->type != 1) 499 + return -EINVAL; 500 + 501 + return 0; 502 + } 503 + 504 + static const struct uart_ops ma35d1serial_ops = { 505 + .tx_empty = ma35d1serial_tx_empty, 506 + .set_mctrl = ma35d1serial_set_mctrl, 507 + .get_mctrl = ma35d1serial_get_mctrl, 508 + .stop_tx = ma35d1serial_stop_tx, 509 + .start_tx = ma35d1serial_start_tx, 510 + .stop_rx = ma35d1serial_stop_rx, 511 + .break_ctl = ma35d1serial_break_ctl, 512 + .startup = ma35d1serial_startup, 513 + .shutdown = ma35d1serial_shutdown, 514 + .set_termios = ma35d1serial_set_termios, 515 + .type = ma35d1serial_type, 516 + .config_port = ma35d1serial_config_port, 517 + .verify_port = ma35d1serial_verify_port, 518 + }; 519 + 520 + static const struct of_device_id ma35d1_serial_of_match[] = { 521 + { .compatible = "nuvoton,ma35d1-uart" }, 522 + {}, 523 + }; 524 + MODULE_DEVICE_TABLE(of, ma35d1_serial_of_match); 525 + 526 + #ifdef CONFIG_SERIAL_NUVOTON_MA35D1_CONSOLE 527 + 528 + static struct device_node *ma35d1serial_uart_nodes[MA35_UART_NR]; 529 + 530 + static void wait_for_xmitr(struct uart_ma35d1_port *up) 531 + { 532 + unsigned int reg = 0; 533 + 534 + read_poll_timeout_atomic(serial_in, reg, reg & MA35_FSR_TX_EMPTY, 535 + 1, 10000, false, 536 + up, MA35_FSR_REG); 537 + } 538 + 539 + static void ma35d1serial_console_putchar(struct uart_port *port, unsigned char ch) 540 + { 541 + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); 542 + 543 + wait_for_xmitr(up); 544 + serial_out(up, MA35_THR_REG, ch); 545 + } 546 + 547 + /* 548 + * Print a string to the serial port trying not to disturb 549 + * any possible real use of the port... 550 + * 551 + * The console_lock must be held when we get here. 552 + */ 553 + static void ma35d1serial_console_write(struct console *co, const char *s, u32 count) 554 + { 555 + struct uart_ma35d1_port *up = &ma35d1serial_ports[co->index]; 556 + unsigned long flags; 557 + int locked = 1; 558 + u32 ier; 559 + 560 + if (up->port.sysrq) 561 + locked = 0; 562 + else if (oops_in_progress) 563 + locked = spin_trylock_irqsave(&up->port.lock, flags); 564 + else 565 + spin_lock_irqsave(&up->port.lock, flags); 566 + 567 + /* 568 + * First save the IER then disable the interrupts 569 + */ 570 + ier = serial_in(up, MA35_IER_REG); 571 + serial_out(up, MA35_IER_REG, 0); 572 + 573 + uart_console_write(&up->port, s, count, ma35d1serial_console_putchar); 574 + 575 + wait_for_xmitr(up); 576 + serial_out(up, MA35_IER_REG, ier); 577 + 578 + if (locked) 579 + spin_unlock_irqrestore(&up->port.lock, flags); 580 + } 581 + 582 + static int __init ma35d1serial_console_setup(struct console *co, char *options) 583 + { 584 + struct device_node *np; 585 + struct uart_ma35d1_port *p; 586 + u32 val32[4]; 587 + struct uart_port *port; 588 + int baud = 115200; 589 + int bits = 8; 590 + int parity = 'n'; 591 + int flow = 'n'; 592 + 593 + if ((co->index < 0) || (co->index >= MA35_UART_NR)) { 594 + pr_debug("Console Port%x out of range\n", co->index); 595 + return -EINVAL; 596 + } 597 + 598 + np = ma35d1serial_uart_nodes[co->index]; 599 + p = &ma35d1serial_ports[co->index]; 600 + if (!np || !p) 601 + return -ENODEV; 602 + 603 + if (of_property_read_u32_array(np, "reg", val32, ARRAY_SIZE(val32)) != 0) 604 + return -EINVAL; 605 + 606 + p->port.iobase = val32[1]; 607 + p->port.membase = ioremap(p->port.iobase, MA35_UART_REG_SIZE); 608 + if (!p->port.membase) 609 + return -ENOMEM; 610 + 611 + p->port.ops = &ma35d1serial_ops; 612 + p->port.line = 0; 613 + p->port.uartclk = MA35_UART_CONSOLE_CLK; 614 + 615 + port = &ma35d1serial_ports[co->index].port; 616 + 617 + if (options) 618 + uart_parse_options(options, &baud, &parity, &bits, &flow); 619 + 620 + return uart_set_options(port, co, baud, parity, bits, flow); 621 + } 622 + 623 + static struct console ma35d1serial_console = { 624 + .name = "ttyNVT", 625 + .write = ma35d1serial_console_write, 626 + .device = uart_console_device, 627 + .setup = ma35d1serial_console_setup, 628 + .flags = CON_PRINTBUFFER | CON_ENABLED, 629 + .index = -1, 630 + .data = &ma35d1serial_reg, 631 + }; 632 + 633 + static void ma35d1serial_console_init_port(void) 634 + { 635 + u32 i = 0; 636 + struct device_node *np; 637 + 638 + for_each_matching_node(np, ma35d1_serial_of_match) { 639 + if (ma35d1serial_uart_nodes[i] == NULL) { 640 + of_node_get(np); 641 + ma35d1serial_uart_nodes[i] = np; 642 + i++; 643 + if (i == MA35_UART_NR) 644 + break; 645 + } 646 + } 647 + } 648 + 649 + static int __init ma35d1serial_console_init(void) 650 + { 651 + ma35d1serial_console_init_port(); 652 + register_console(&ma35d1serial_console); 653 + return 0; 654 + } 655 + console_initcall(ma35d1serial_console_init); 656 + 657 + #define MA35D1SERIAL_CONSOLE (&ma35d1serial_console) 658 + #else 659 + #define MA35D1SERIAL_CONSOLE NULL 660 + #endif 661 + 662 + static struct uart_driver ma35d1serial_reg = { 663 + .owner = THIS_MODULE, 664 + .driver_name = "serial", 665 + .dev_name = "ttyNVT", 666 + .major = TTY_MAJOR, 667 + .minor = 64, 668 + .cons = MA35D1SERIAL_CONSOLE, 669 + .nr = MA35_UART_NR, 670 + }; 671 + 672 + /* 673 + * Register a set of serial devices attached to a platform device. 674 + * The list is terminated with a zero flags entry, which means we expect 675 + * all entries to have at least UPF_BOOT_AUTOCONF set. 676 + */ 677 + static int ma35d1serial_probe(struct platform_device *pdev) 678 + { 679 + struct resource *res_mem; 680 + struct uart_ma35d1_port *up; 681 + int ret = 0; 682 + 683 + if (pdev->dev.of_node) { 684 + ret = of_alias_get_id(pdev->dev.of_node, "serial"); 685 + if (ret < 0) { 686 + dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", ret); 687 + return ret; 688 + } 689 + } 690 + up = &ma35d1serial_ports[ret]; 691 + up->port.line = ret; 692 + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 693 + if (!res_mem) 694 + return -ENODEV; 695 + 696 + up->port.iobase = res_mem->start; 697 + up->port.membase = ioremap(up->port.iobase, MA35_UART_REG_SIZE); 698 + up->port.ops = &ma35d1serial_ops; 699 + 700 + spin_lock_init(&up->port.lock); 701 + 702 + up->clk = of_clk_get(pdev->dev.of_node, 0); 703 + if (IS_ERR(up->clk)) { 704 + ret = PTR_ERR(up->clk); 705 + dev_err(&pdev->dev, "failed to get core clk: %d\n", ret); 706 + goto err_iounmap; 707 + } 708 + 709 + ret = clk_prepare_enable(up->clk); 710 + if (ret) 711 + goto err_iounmap; 712 + 713 + if (up->port.line != 0) 714 + up->port.uartclk = clk_get_rate(up->clk); 715 + 716 + ret = platform_get_irq(pdev, 0); 717 + if (ret < 0) 718 + goto err_clk_disable; 719 + 720 + up->port.irq = ret; 721 + up->port.dev = &pdev->dev; 722 + up->port.flags = UPF_BOOT_AUTOCONF; 723 + 724 + platform_set_drvdata(pdev, up); 725 + 726 + ret = uart_add_one_port(&ma35d1serial_reg, &up->port); 727 + if (ret < 0) 728 + goto err_free_irq; 729 + 730 + return 0; 731 + 732 + err_free_irq: 733 + free_irq(up->port.irq, &up->port); 734 + 735 + err_clk_disable: 736 + clk_disable_unprepare(up->clk); 737 + 738 + err_iounmap: 739 + iounmap(up->port.membase); 740 + return ret; 741 + } 742 + 743 + /* 744 + * Remove serial ports registered against a platform device. 745 + */ 746 + static int ma35d1serial_remove(struct platform_device *dev) 747 + { 748 + struct uart_port *port = platform_get_drvdata(dev); 749 + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); 750 + 751 + uart_remove_one_port(&ma35d1serial_reg, port); 752 + clk_disable_unprepare(up->clk); 753 + return 0; 754 + } 755 + 756 + static int ma35d1serial_suspend(struct platform_device *dev, pm_message_t state) 757 + { 758 + struct uart_port *port = platform_get_drvdata(dev); 759 + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); 760 + 761 + uart_suspend_port(&ma35d1serial_reg, &up->port); 762 + if (up->port.line == 0) { 763 + up->console_baud_rate = serial_in(up, MA35_BAUD_REG); 764 + up->console_line = serial_in(up, MA35_LCR_REG); 765 + up->console_int = serial_in(up, MA35_IER_REG); 766 + } 767 + return 0; 768 + } 769 + 770 + static int ma35d1serial_resume(struct platform_device *dev) 771 + { 772 + struct uart_port *port = platform_get_drvdata(dev); 773 + struct uart_ma35d1_port *up = to_ma35d1_uart_port(port); 774 + 775 + if (up->port.line == 0) { 776 + serial_out(up, MA35_BAUD_REG, up->console_baud_rate); 777 + serial_out(up, MA35_LCR_REG, up->console_line); 778 + serial_out(up, MA35_IER_REG, up->console_int); 779 + } 780 + uart_resume_port(&ma35d1serial_reg, &up->port); 781 + return 0; 782 + } 783 + 784 + static struct platform_driver ma35d1serial_driver = { 785 + .probe = ma35d1serial_probe, 786 + .remove = ma35d1serial_remove, 787 + .suspend = ma35d1serial_suspend, 788 + .resume = ma35d1serial_resume, 789 + .driver = { 790 + .name = "ma35d1-uart", 791 + .owner = THIS_MODULE, 792 + .of_match_table = of_match_ptr(ma35d1_serial_of_match), 793 + }, 794 + }; 795 + 796 + static int __init ma35d1serial_init(void) 797 + { 798 + int ret; 799 + 800 + ret = uart_register_driver(&ma35d1serial_reg); 801 + if (ret) 802 + return ret; 803 + 804 + ret = platform_driver_register(&ma35d1serial_driver); 805 + if (ret) 806 + uart_unregister_driver(&ma35d1serial_reg); 807 + 808 + return ret; 809 + } 810 + 811 + static void __exit ma35d1serial_exit(void) 812 + { 813 + platform_driver_unregister(&ma35d1serial_driver); 814 + uart_unregister_driver(&ma35d1serial_reg); 815 + } 816 + 817 + module_init(ma35d1serial_init); 818 + module_exit(ma35d1serial_exit); 819 + 820 + MODULE_LICENSE("GPL"); 821 + MODULE_DESCRIPTION("MA35D1 serial driver");

+1 -1

drivers/tty/serial/max310x.c

··· 1636 1636 .of_match_table = max310x_dt_ids, 1637 1637 .pm = &max310x_pm_ops, 1638 1638 }, 1639 - .probe_new = max310x_i2c_probe, 1639 + .probe = max310x_i2c_probe, 1640 1640 .remove = max310x_i2c_remove, 1641 1641 }; 1642 1642 #endif

+15 -4

drivers/tty/serial/samsung_tty.c

··· 24 24 #include <linux/dmaengine.h> 25 25 #include <linux/dma-mapping.h> 26 26 #include <linux/slab.h> 27 + #include <linux/math.h> 27 28 #include <linux/module.h> 28 29 #include <linux/ioport.h> 29 30 #include <linux/io.h> ··· 1460 1459 continue; 1461 1460 1462 1461 rate = clk_get_rate(clk); 1463 - if (!rate) 1462 + if (!rate) { 1463 + dev_err(ourport->port.dev, 1464 + "Failed to get clock rate for %s.\n", clkname); 1465 + clk_put(clk); 1464 1466 continue; 1467 + } 1465 1468 1466 1469 if (ourport->info->has_divslot) { 1467 1470 unsigned long div = rate / req_baud; ··· 1486 1481 } 1487 1482 quot--; 1488 1483 1489 - calc_deviation = req_baud - baud; 1490 - if (calc_deviation < 0) 1491 - calc_deviation = -calc_deviation; 1484 + calc_deviation = abs(req_baud - baud); 1492 1485 1493 1486 if (calc_deviation < deviation) { 1487 + /* 1488 + * If we find a better clk, release the previous one, if 1489 + * any. 1490 + */ 1491 + if (!IS_ERR(*best_clk)) 1492 + clk_put(*best_clk); 1494 1493 *best_clk = clk; 1495 1494 best_quot = quot; 1496 1495 *clk_num = cnt; 1497 1496 deviation = calc_deviation; 1497 + } else { 1498 + clk_put(clk); 1498 1499 } 1499 1500 } 1500 1501

+1 -1

drivers/tty/serial/sc16is7xx.c

··· 1709 1709 .name = SC16IS7XX_NAME, 1710 1710 .of_match_table = sc16is7xx_dt_ids, 1711 1711 }, 1712 - .probe_new = sc16is7xx_i2c_probe, 1712 + .probe = sc16is7xx_i2c_probe, 1713 1713 .remove = sc16is7xx_i2c_remove, 1714 1714 .id_table = sc16is7xx_i2c_id_table, 1715 1715 };

+46

drivers/tty/serial/serial_base.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0+ */ 2 + /* 3 + * Serial core related functions, serial port device drivers do not need this. 4 + * 5 + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 6 + * Author: Tony Lindgren <tony@atomide.com> 7 + */ 8 + 9 + #define to_serial_base_ctrl_device(d) container_of((d), struct serial_ctrl_device, dev) 10 + #define to_serial_base_port_device(d) container_of((d), struct serial_port_device, dev) 11 + 12 + struct uart_driver; 13 + struct uart_port; 14 + struct device_driver; 15 + struct device; 16 + 17 + struct serial_ctrl_device { 18 + struct device dev; 19 + }; 20 + 21 + struct serial_port_device { 22 + struct device dev; 23 + struct uart_port *port; 24 + }; 25 + 26 + int serial_base_ctrl_init(void); 27 + void serial_base_ctrl_exit(void); 28 + 29 + int serial_base_port_init(void); 30 + void serial_base_port_exit(void); 31 + 32 + int serial_base_driver_register(struct device_driver *driver); 33 + void serial_base_driver_unregister(struct device_driver *driver); 34 + 35 + struct serial_ctrl_device *serial_base_ctrl_add(struct uart_port *port, 36 + struct device *parent); 37 + struct serial_port_device *serial_base_port_add(struct uart_port *port, 38 + struct serial_ctrl_device *parent); 39 + void serial_base_ctrl_device_remove(struct serial_ctrl_device *ctrl_dev); 40 + void serial_base_port_device_remove(struct serial_port_device *port_dev); 41 + 42 + int serial_ctrl_register_port(struct uart_driver *drv, struct uart_port *port); 43 + void serial_ctrl_unregister_port(struct uart_driver *drv, struct uart_port *port); 44 + 45 + int serial_core_register_port(struct uart_driver *drv, struct uart_port *port); 46 + void serial_core_unregister_port(struct uart_driver *drv, struct uart_port *port);

+205

drivers/tty/serial/serial_base_bus.c

··· 1 + // SPDX-License-Identifier: GPL-2.0+ 2 + /* 3 + * Serial base bus layer for controllers 4 + * 5 + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 6 + * Author: Tony Lindgren <tony@atomide.com> 7 + * 8 + * The serial core bus manages the serial core controller instances. 9 + */ 10 + 11 + #include <linux/container_of.h> 12 + #include <linux/device.h> 13 + #include <linux/module.h> 14 + #include <linux/serial_core.h> 15 + #include <linux/slab.h> 16 + #include <linux/spinlock.h> 17 + 18 + #include "serial_base.h" 19 + 20 + static bool serial_base_initialized; 21 + 22 + static int serial_base_match(struct device *dev, struct device_driver *drv) 23 + { 24 + int len = strlen(drv->name); 25 + 26 + return !strncmp(dev_name(dev), drv->name, len); 27 + } 28 + 29 + static struct bus_type serial_base_bus_type = { 30 + .name = "serial-base", 31 + .match = serial_base_match, 32 + }; 33 + 34 + int serial_base_driver_register(struct device_driver *driver) 35 + { 36 + driver->bus = &serial_base_bus_type; 37 + 38 + return driver_register(driver); 39 + } 40 + 41 + void serial_base_driver_unregister(struct device_driver *driver) 42 + { 43 + driver_unregister(driver); 44 + } 45 + 46 + static int serial_base_device_init(struct uart_port *port, 47 + struct device *dev, 48 + struct device *parent_dev, 49 + const struct device_type *type, 50 + void (*release)(struct device *dev), 51 + int id) 52 + { 53 + device_initialize(dev); 54 + dev->type = type; 55 + dev->parent = parent_dev; 56 + dev->bus = &serial_base_bus_type; 57 + dev->release = release; 58 + 59 + if (!serial_base_initialized) { 60 + dev_dbg(port->dev, "uart_add_one_port() called before arch_initcall()?\n"); 61 + return -EPROBE_DEFER; 62 + } 63 + 64 + return dev_set_name(dev, "%s.%s.%d", type->name, dev_name(port->dev), id); 65 + } 66 + 67 + static const struct device_type serial_ctrl_type = { 68 + .name = "ctrl", 69 + }; 70 + 71 + static void serial_base_ctrl_release(struct device *dev) 72 + { 73 + struct serial_ctrl_device *ctrl_dev = to_serial_base_ctrl_device(dev); 74 + 75 + kfree(ctrl_dev); 76 + } 77 + 78 + void serial_base_ctrl_device_remove(struct serial_ctrl_device *ctrl_dev) 79 + { 80 + if (!ctrl_dev) 81 + return; 82 + 83 + device_del(&ctrl_dev->dev); 84 + } 85 + 86 + struct serial_ctrl_device *serial_base_ctrl_add(struct uart_port *port, 87 + struct device *parent) 88 + { 89 + struct serial_ctrl_device *ctrl_dev; 90 + int err; 91 + 92 + ctrl_dev = kzalloc(sizeof(*ctrl_dev), GFP_KERNEL); 93 + if (!ctrl_dev) 94 + return ERR_PTR(-ENOMEM); 95 + 96 + err = serial_base_device_init(port, &ctrl_dev->dev, 97 + parent, &serial_ctrl_type, 98 + serial_base_ctrl_release, 99 + port->ctrl_id); 100 + if (err) 101 + goto err_put_device; 102 + 103 + err = device_add(&ctrl_dev->dev); 104 + if (err) 105 + goto err_put_device; 106 + 107 + return ctrl_dev; 108 + 109 + err_put_device: 110 + put_device(&ctrl_dev->dev); 111 + 112 + return ERR_PTR(err); 113 + } 114 + 115 + static const struct device_type serial_port_type = { 116 + .name = "port", 117 + }; 118 + 119 + static void serial_base_port_release(struct device *dev) 120 + { 121 + struct serial_port_device *port_dev = to_serial_base_port_device(dev); 122 + 123 + kfree(port_dev); 124 + } 125 + 126 + struct serial_port_device *serial_base_port_add(struct uart_port *port, 127 + struct serial_ctrl_device *ctrl_dev) 128 + { 129 + struct serial_port_device *port_dev; 130 + int err; 131 + 132 + port_dev = kzalloc(sizeof(*port_dev), GFP_KERNEL); 133 + if (!port_dev) 134 + return ERR_PTR(-ENOMEM); 135 + 136 + err = serial_base_device_init(port, &port_dev->dev, 137 + &ctrl_dev->dev, &serial_port_type, 138 + serial_base_port_release, 139 + port->line); 140 + if (err) 141 + goto err_put_device; 142 + 143 + port_dev->port = port; 144 + 145 + err = device_add(&port_dev->dev); 146 + if (err) 147 + goto err_put_device; 148 + 149 + return port_dev; 150 + 151 + err_put_device: 152 + put_device(&port_dev->dev); 153 + 154 + return ERR_PTR(err); 155 + } 156 + 157 + void serial_base_port_device_remove(struct serial_port_device *port_dev) 158 + { 159 + if (!port_dev) 160 + return; 161 + 162 + device_del(&port_dev->dev); 163 + } 164 + 165 + static int serial_base_init(void) 166 + { 167 + int ret; 168 + 169 + ret = bus_register(&serial_base_bus_type); 170 + if (ret) 171 + return ret; 172 + 173 + ret = serial_base_ctrl_init(); 174 + if (ret) 175 + goto err_bus_unregister; 176 + 177 + ret = serial_base_port_init(); 178 + if (ret) 179 + goto err_ctrl_exit; 180 + 181 + serial_base_initialized = true; 182 + 183 + return 0; 184 + 185 + err_ctrl_exit: 186 + serial_base_ctrl_exit(); 187 + 188 + err_bus_unregister: 189 + bus_unregister(&serial_base_bus_type); 190 + 191 + return ret; 192 + } 193 + arch_initcall(serial_base_init); 194 + 195 + static void serial_base_exit(void) 196 + { 197 + serial_base_port_exit(); 198 + serial_base_ctrl_exit(); 199 + bus_unregister(&serial_base_bus_type); 200 + } 201 + module_exit(serial_base_exit); 202 + 203 + MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>"); 204 + MODULE_DESCRIPTION("Serial core bus"); 205 + MODULE_LICENSE("GPL");

+180 -30

drivers/tty/serial/serial_core.c

··· 17 17 #include <linux/gpio/consumer.h> 18 18 #include <linux/kernel.h> 19 19 #include <linux/of.h> 20 + #include <linux/pm_runtime.h> 20 21 #include <linux/proc_fs.h> 21 22 #include <linux/seq_file.h> 22 23 #include <linux/device.h> ··· 31 30 32 31 #include <linux/irq.h> 33 32 #include <linux/uaccess.h> 33 + 34 + #include "serial_base.h" 34 35 35 36 /* 36 37 * This is used to lock changes in serial line configuration. ··· 137 134 { 138 135 struct uart_state *state = tty->driver_data; 139 136 struct uart_port *port = state->uart_port; 137 + struct serial_port_device *port_dev; 138 + int err; 140 139 141 - if (port && !(port->flags & UPF_DEAD) && !uart_tx_stopped(port)) 140 + if (!port || port->flags & UPF_DEAD || uart_tx_stopped(port)) 141 + return; 142 + 143 + port_dev = port->port_dev; 144 + 145 + /* Increment the runtime PM usage count for the active check below */ 146 + err = pm_runtime_get(&port_dev->dev); 147 + if (err < 0) { 148 + pm_runtime_put_noidle(&port_dev->dev); 149 + return; 150 + } 151 + 152 + /* 153 + * Start TX if enabled, and kick runtime PM. If the device is not 154 + * enabled, serial_port_runtime_resume() calls start_tx() again 155 + * after enabling the device. 156 + */ 157 + if (pm_runtime_active(&port_dev->dev)) 142 158 port->ops->start_tx(port); 159 + pm_runtime_mark_last_busy(&port_dev->dev); 160 + pm_runtime_put_autosuspend(&port_dev->dev); 143 161 } 144 162 145 163 static void uart_start(struct tty_struct *tty) ··· 2357 2333 * able to Re-start_rx later. 2358 2334 */ 2359 2335 if (!console_suspend_enabled && uart_console(uport)) { 2360 - if (uport->ops->start_rx) 2336 + if (uport->ops->start_rx) { 2337 + spin_lock_irq(&uport->lock); 2361 2338 uport->ops->stop_rx(uport); 2339 + spin_unlock_irq(&uport->lock); 2340 + } 2362 2341 goto unlock; 2363 2342 } 2364 2343 ··· 2454 2427 if (console_suspend_enabled) 2455 2428 uart_change_pm(state, UART_PM_STATE_ON); 2456 2429 uport->ops->set_termios(uport, &termios, NULL); 2457 - if (!console_suspend_enabled && uport->ops->start_rx) 2430 + if (!console_suspend_enabled && uport->ops->start_rx) { 2431 + spin_lock_irq(&uport->lock); 2458 2432 uport->ops->start_rx(uport); 2433 + spin_unlock_irq(&uport->lock); 2434 + } 2459 2435 if (console_suspend_enabled) 2460 2436 console_start(uport->cons); 2461 2437 } ··· 3072 3042 }; 3073 3043 3074 3044 /** 3075 - * uart_add_one_port - attach a driver-defined port structure 3045 + * serial_core_add_one_port - attach a driver-defined port structure 3076 3046 * @drv: pointer to the uart low level driver structure for this port 3077 3047 * @uport: uart port structure to use for this port. 3078 3048 * ··· 3081 3051 * This allows the driver @drv to register its own uart_port structure with the 3082 3052 * core driver. The main purpose is to allow the low level uart drivers to 3083 3053 * expand uart_port, rather than having yet more levels of structures. 3054 + * Caller must hold port_mutex. 3084 3055 */ 3085 - int uart_add_one_port(struct uart_driver *drv, struct uart_port *uport) 3056 + static int serial_core_add_one_port(struct uart_driver *drv, struct uart_port *uport) 3086 3057 { 3087 3058 struct uart_state *state; 3088 3059 struct tty_port *port; ··· 3097 3066 state = drv->state + uport->line; 3098 3067 port = &state->port; 3099 3068 3100 - mutex_lock(&port_mutex); 3101 3069 mutex_lock(&port->mutex); 3102 3070 if (state->uart_port) { 3103 3071 ret = -EINVAL; ··· 3161 3131 uport->line); 3162 3132 } 3163 3133 3164 - /* 3165 - * Ensure UPF_DEAD is not set. 3166 - */ 3167 - uport->flags &= ~UPF_DEAD; 3168 - 3169 3134 out: 3170 3135 mutex_unlock(&port->mutex); 3171 - mutex_unlock(&port_mutex); 3172 3136 3173 3137 return ret; 3174 3138 } 3175 - EXPORT_SYMBOL(uart_add_one_port); 3176 3139 3177 3140 /** 3178 - * uart_remove_one_port - detach a driver defined port structure 3141 + * serial_core_remove_one_port - detach a driver defined port structure 3179 3142 * @drv: pointer to the uart low level driver structure for this port 3180 3143 * @uport: uart port structure for this port 3181 3144 * ··· 3176 3153 * 3177 3154 * This unhooks (and hangs up) the specified port structure from the core 3178 3155 * driver. No further calls will be made to the low-level code for this port. 3156 + * Caller must hold port_mutex. 3179 3157 */ 3180 - int uart_remove_one_port(struct uart_driver *drv, struct uart_port *uport) 3158 + static void serial_core_remove_one_port(struct uart_driver *drv, 3159 + struct uart_port *uport) 3181 3160 { 3182 3161 struct uart_state *state = drv->state + uport->line; 3183 3162 struct tty_port *port = &state->port; 3184 3163 struct uart_port *uart_port; 3185 3164 struct tty_struct *tty; 3186 - int ret = 0; 3187 3165 3188 - mutex_lock(&port_mutex); 3189 - 3190 - /* 3191 - * Mark the port "dead" - this prevents any opens from 3192 - * succeeding while we shut down the port. 3193 - */ 3194 3166 mutex_lock(&port->mutex); 3195 3167 uart_port = uart_port_check(state); 3196 3168 if (uart_port != uport) ··· 3194 3176 3195 3177 if (!uart_port) { 3196 3178 mutex_unlock(&port->mutex); 3197 - ret = -EINVAL; 3198 - goto out; 3179 + return; 3199 3180 } 3200 - uport->flags |= UPF_DEAD; 3201 3181 mutex_unlock(&port->mutex); 3202 3182 3203 3183 /* ··· 3227 3211 * Indicate that there isn't a port here anymore. 3228 3212 */ 3229 3213 uport->type = PORT_UNKNOWN; 3214 + uport->port_dev = NULL; 3230 3215 3231 3216 mutex_lock(&port->mutex); 3232 3217 WARN_ON(atomic_dec_return(&state->refcount) < 0); 3233 3218 wait_event(state->remove_wait, !atomic_read(&state->refcount)); 3234 3219 state->uart_port = NULL; 3235 3220 mutex_unlock(&port->mutex); 3236 - out: 3237 - mutex_unlock(&port_mutex); 3238 - 3239 - return ret; 3240 3221 } 3241 - EXPORT_SYMBOL(uart_remove_one_port); 3242 3222 3243 3223 /** 3244 3224 * uart_match_port - are the two ports equivalent? ··· 3268 3256 return false; 3269 3257 } 3270 3258 EXPORT_SYMBOL(uart_match_port); 3259 + 3260 + static struct serial_ctrl_device * 3261 + serial_core_get_ctrl_dev(struct serial_port_device *port_dev) 3262 + { 3263 + struct device *dev = &port_dev->dev; 3264 + 3265 + return to_serial_base_ctrl_device(dev->parent); 3266 + } 3267 + 3268 + /* 3269 + * Find a registered serial core controller device if one exists. Returns 3270 + * the first device matching the ctrl_id. Caller must hold port_mutex. 3271 + */ 3272 + static struct serial_ctrl_device *serial_core_ctrl_find(struct uart_driver *drv, 3273 + struct device *phys_dev, 3274 + int ctrl_id) 3275 + { 3276 + struct uart_state *state; 3277 + int i; 3278 + 3279 + lockdep_assert_held(&port_mutex); 3280 + 3281 + for (i = 0; i < drv->nr; i++) { 3282 + state = drv->state + i; 3283 + if (!state->uart_port || !state->uart_port->port_dev) 3284 + continue; 3285 + 3286 + if (state->uart_port->dev == phys_dev && 3287 + state->uart_port->ctrl_id == ctrl_id) 3288 + return serial_core_get_ctrl_dev(state->uart_port->port_dev); 3289 + } 3290 + 3291 + return NULL; 3292 + } 3293 + 3294 + static struct serial_ctrl_device *serial_core_ctrl_device_add(struct uart_port *port) 3295 + { 3296 + return serial_base_ctrl_add(port, port->dev); 3297 + } 3298 + 3299 + static int serial_core_port_device_add(struct serial_ctrl_device *ctrl_dev, 3300 + struct uart_port *port) 3301 + { 3302 + struct serial_port_device *port_dev; 3303 + 3304 + port_dev = serial_base_port_add(port, ctrl_dev); 3305 + if (IS_ERR(port_dev)) 3306 + return PTR_ERR(port_dev); 3307 + 3308 + port->port_dev = port_dev; 3309 + 3310 + return 0; 3311 + } 3312 + 3313 + /* 3314 + * Initialize a serial core port device, and a controller device if needed. 3315 + */ 3316 + int serial_core_register_port(struct uart_driver *drv, struct uart_port *port) 3317 + { 3318 + struct serial_ctrl_device *ctrl_dev, *new_ctrl_dev = NULL; 3319 + int ret; 3320 + 3321 + mutex_lock(&port_mutex); 3322 + 3323 + /* 3324 + * Prevent serial_port_runtime_resume() from trying to use the port 3325 + * until serial_core_add_one_port() has completed 3326 + */ 3327 + port->flags |= UPF_DEAD; 3328 + 3329 + /* Inititalize a serial core controller device if needed */ 3330 + ctrl_dev = serial_core_ctrl_find(drv, port->dev, port->ctrl_id); 3331 + if (!ctrl_dev) { 3332 + new_ctrl_dev = serial_core_ctrl_device_add(port); 3333 + if (IS_ERR(new_ctrl_dev)) { 3334 + ret = PTR_ERR(new_ctrl_dev); 3335 + goto err_unlock; 3336 + } 3337 + ctrl_dev = new_ctrl_dev; 3338 + } 3339 + 3340 + /* 3341 + * Initialize a serial core port device. Tag the port dead to prevent 3342 + * serial_port_runtime_resume() trying to do anything until port has 3343 + * been registered. It gets cleared by serial_core_add_one_port(). 3344 + */ 3345 + ret = serial_core_port_device_add(ctrl_dev, port); 3346 + if (ret) 3347 + goto err_unregister_ctrl_dev; 3348 + 3349 + ret = serial_core_add_one_port(drv, port); 3350 + if (ret) 3351 + goto err_unregister_port_dev; 3352 + 3353 + port->flags &= ~UPF_DEAD; 3354 + 3355 + mutex_unlock(&port_mutex); 3356 + 3357 + return 0; 3358 + 3359 + err_unregister_port_dev: 3360 + serial_base_port_device_remove(port->port_dev); 3361 + 3362 + err_unregister_ctrl_dev: 3363 + serial_base_ctrl_device_remove(new_ctrl_dev); 3364 + 3365 + err_unlock: 3366 + mutex_unlock(&port_mutex); 3367 + 3368 + return ret; 3369 + } 3370 + 3371 + /* 3372 + * Removes a serial core port device, and the related serial core controller 3373 + * device if the last instance. 3374 + */ 3375 + void serial_core_unregister_port(struct uart_driver *drv, struct uart_port *port) 3376 + { 3377 + struct device *phys_dev = port->dev; 3378 + struct serial_port_device *port_dev = port->port_dev; 3379 + struct serial_ctrl_device *ctrl_dev = serial_core_get_ctrl_dev(port_dev); 3380 + int ctrl_id = port->ctrl_id; 3381 + 3382 + mutex_lock(&port_mutex); 3383 + 3384 + port->flags |= UPF_DEAD; 3385 + 3386 + serial_core_remove_one_port(drv, port); 3387 + 3388 + /* Note that struct uart_port *port is no longer valid at this point */ 3389 + serial_base_port_device_remove(port_dev); 3390 + 3391 + /* Drop the serial core controller device if no ports are using it */ 3392 + if (!serial_core_ctrl_find(drv, phys_dev, ctrl_id)) 3393 + serial_base_ctrl_device_remove(ctrl_dev); 3394 + 3395 + mutex_unlock(&port_mutex); 3396 + } 3271 3397 3272 3398 /** 3273 3399 * uart_handle_dcd_change - handle a change of carrier detect state

+68

drivers/tty/serial/serial_ctrl.c

··· 1 + // SPDX-License-Identifier: GPL-2.0+ 2 + /* 3 + * Serial core controller driver 4 + * 5 + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 6 + * Author: Tony Lindgren <tony@atomide.com> 7 + * 8 + * This driver manages the serial core controller struct device instances. 9 + * The serial core controller devices are children of the physical serial 10 + * port device. 11 + */ 12 + 13 + #include <linux/device.h> 14 + #include <linux/module.h> 15 + #include <linux/pm_runtime.h> 16 + #include <linux/serial_core.h> 17 + #include <linux/spinlock.h> 18 + 19 + #include "serial_base.h" 20 + 21 + static int serial_ctrl_probe(struct device *dev) 22 + { 23 + pm_runtime_enable(dev); 24 + 25 + return 0; 26 + } 27 + 28 + static int serial_ctrl_remove(struct device *dev) 29 + { 30 + pm_runtime_disable(dev); 31 + 32 + return 0; 33 + } 34 + 35 + /* 36 + * Serial core controller device init functions. Note that the physical 37 + * serial port device driver may not have completed probe at this point. 38 + */ 39 + int serial_ctrl_register_port(struct uart_driver *drv, struct uart_port *port) 40 + { 41 + return serial_core_register_port(drv, port); 42 + } 43 + 44 + void serial_ctrl_unregister_port(struct uart_driver *drv, struct uart_port *port) 45 + { 46 + serial_core_unregister_port(drv, port); 47 + } 48 + 49 + static struct device_driver serial_ctrl_driver = { 50 + .name = "ctrl", 51 + .suppress_bind_attrs = true, 52 + .probe = serial_ctrl_probe, 53 + .remove = serial_ctrl_remove, 54 + }; 55 + 56 + int serial_base_ctrl_init(void) 57 + { 58 + return serial_base_driver_register(&serial_ctrl_driver); 59 + } 60 + 61 + void serial_base_ctrl_exit(void) 62 + { 63 + serial_base_driver_unregister(&serial_ctrl_driver); 64 + } 65 + 66 + MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>"); 67 + MODULE_DESCRIPTION("Serial core controller driver"); 68 + MODULE_LICENSE("GPL");

+105

drivers/tty/serial/serial_port.c

··· 1 + // SPDX-License-Identifier: GPL-2.0+ 2 + /* 3 + * Serial core port device driver 4 + * 5 + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 6 + * Author: Tony Lindgren <tony@atomide.com> 7 + */ 8 + 9 + #include <linux/device.h> 10 + #include <linux/module.h> 11 + #include <linux/pm_runtime.h> 12 + #include <linux/serial_core.h> 13 + #include <linux/spinlock.h> 14 + 15 + #include "serial_base.h" 16 + 17 + #define SERIAL_PORT_AUTOSUSPEND_DELAY_MS 500 18 + 19 + /* Only considers pending TX for now. Caller must take care of locking */ 20 + static int __serial_port_busy(struct uart_port *port) 21 + { 22 + return !uart_tx_stopped(port) && 23 + uart_circ_chars_pending(&port->state->xmit); 24 + } 25 + 26 + static int serial_port_runtime_resume(struct device *dev) 27 + { 28 + struct serial_port_device *port_dev = to_serial_base_port_device(dev); 29 + struct uart_port *port; 30 + unsigned long flags; 31 + 32 + port = port_dev->port; 33 + 34 + if (port->flags & UPF_DEAD) 35 + goto out; 36 + 37 + /* Flush any pending TX for the port */ 38 + spin_lock_irqsave(&port->lock, flags); 39 + if (__serial_port_busy(port)) 40 + port->ops->start_tx(port); 41 + spin_unlock_irqrestore(&port->lock, flags); 42 + 43 + out: 44 + pm_runtime_mark_last_busy(dev); 45 + 46 + return 0; 47 + } 48 + 49 + static DEFINE_RUNTIME_DEV_PM_OPS(serial_port_pm, 50 + NULL, serial_port_runtime_resume, NULL); 51 + 52 + static int serial_port_probe(struct device *dev) 53 + { 54 + pm_runtime_enable(dev); 55 + pm_runtime_set_autosuspend_delay(dev, SERIAL_PORT_AUTOSUSPEND_DELAY_MS); 56 + pm_runtime_use_autosuspend(dev); 57 + 58 + return 0; 59 + } 60 + 61 + static int serial_port_remove(struct device *dev) 62 + { 63 + pm_runtime_dont_use_autosuspend(dev); 64 + pm_runtime_disable(dev); 65 + 66 + return 0; 67 + } 68 + 69 + /* 70 + * Serial core port device init functions. Note that the physical serial 71 + * port device driver may not have completed probe at this point. 72 + */ 73 + int uart_add_one_port(struct uart_driver *drv, struct uart_port *port) 74 + { 75 + return serial_ctrl_register_port(drv, port); 76 + } 77 + EXPORT_SYMBOL(uart_add_one_port); 78 + 79 + void uart_remove_one_port(struct uart_driver *drv, struct uart_port *port) 80 + { 81 + serial_ctrl_unregister_port(drv, port); 82 + } 83 + EXPORT_SYMBOL(uart_remove_one_port); 84 + 85 + static struct device_driver serial_port_driver = { 86 + .name = "port", 87 + .suppress_bind_attrs = true, 88 + .probe = serial_port_probe, 89 + .remove = serial_port_remove, 90 + .pm = pm_ptr(&serial_port_pm), 91 + }; 92 + 93 + int serial_base_port_init(void) 94 + { 95 + return serial_base_driver_register(&serial_port_driver); 96 + } 97 + 98 + void serial_base_port_exit(void) 99 + { 100 + serial_base_driver_unregister(&serial_port_driver); 101 + } 102 + 103 + MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>"); 104 + MODULE_DESCRIPTION("Serial controller port driver"); 105 + MODULE_LICENSE("GPL");

+4 -2

drivers/tty/serial/st-asc.c

··· 754 754 755 755 asc_ports[id].hw_flow_control = of_property_read_bool(np, 756 756 "uart-has-rtscts"); 757 - asc_ports[id].force_m1 = of_property_read_bool(np, "st,force_m1"); 757 + asc_ports[id].force_m1 = of_property_read_bool(np, "st,force-m1"); 758 758 asc_ports[id].port.line = id; 759 759 asc_ports[id].rts = NULL; 760 760 ··· 796 796 { 797 797 struct uart_port *port = platform_get_drvdata(pdev); 798 798 799 - return uart_remove_one_port(&asc_uart_driver, port); 799 + uart_remove_one_port(&asc_uart_driver, port); 800 + 801 + return 0; 800 802 } 801 803 802 804 #ifdef CONFIG_PM_SLEEP

+1 -4

drivers/tty/serial/stm32-usart.c

··· 1755 1755 struct uart_port *port = platform_get_drvdata(pdev); 1756 1756 struct stm32_port *stm32_port = to_stm32_port(port); 1757 1757 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1758 - int err; 1759 1758 u32 cr3; 1760 1759 1761 1760 pm_runtime_get_sync(&pdev->dev); 1762 - err = uart_remove_one_port(&stm32_usart_driver, port); 1763 - if (err) 1764 - return(err); 1761 + uart_remove_one_port(&stm32_usart_driver, port); 1765 1762 1766 1763 pm_runtime_disable(&pdev->dev); 1767 1764 pm_runtime_set_suspended(&pdev->dev);

+4 -8

drivers/tty/serial/uartlite.c

··· 685 685 * 686 686 * @dev: pointer to device structure 687 687 */ 688 - static int ulite_release(struct device *dev) 688 + static void ulite_release(struct device *dev) 689 689 { 690 690 struct uart_port *port = dev_get_drvdata(dev); 691 - int rc = 0; 692 691 693 692 if (port) { 694 - rc = uart_remove_one_port(&ulite_uart_driver, port); 693 + uart_remove_one_port(&ulite_uart_driver, port); 695 694 dev_set_drvdata(dev, NULL); 696 695 port->mapbase = 0; 697 696 } 698 - 699 - return rc; 700 697 } 701 698 702 699 /** ··· 897 900 { 898 901 struct uart_port *port = dev_get_drvdata(&pdev->dev); 899 902 struct uartlite_data *pdata = port->private_data; 900 - int rc; 901 903 902 904 clk_disable_unprepare(pdata->clk); 903 - rc = ulite_release(&pdev->dev); 905 + ulite_release(&pdev->dev); 904 906 pm_runtime_disable(&pdev->dev); 905 907 pm_runtime_set_suspended(&pdev->dev); 906 908 pm_runtime_dont_use_autosuspend(&pdev->dev); 907 - return rc; 909 + return 0; 908 910 } 909 911 910 912 /* work with hotplug and coldplug */

+2 -3

drivers/tty/serial/xilinx_uartps.c

··· 1670 1670 { 1671 1671 struct uart_port *port = platform_get_drvdata(pdev); 1672 1672 struct cdns_uart *cdns_uart_data = port->private_data; 1673 - int rc; 1674 1673 1675 1674 /* Remove the cdns_uart port from the serial core */ 1676 1675 #ifdef CONFIG_COMMON_CLK 1677 1676 clk_notifier_unregister(cdns_uart_data->uartclk, 1678 1677 &cdns_uart_data->clk_rate_change_nb); 1679 1678 #endif 1680 - rc = uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port); 1679 + uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port); 1681 1680 port->mapbase = 0; 1682 1681 clk_disable_unprepare(cdns_uart_data->uartclk); 1683 1682 clk_disable_unprepare(cdns_uart_data->pclk); ··· 1692 1693 1693 1694 if (!--instances) 1694 1695 uart_unregister_driver(cdns_uart_data->cdns_uart_driver); 1695 - return rc; 1696 + return 0; 1696 1697 } 1697 1698 1698 1699 static struct platform_driver cdns_uart_platform_driver = {

+6 -5

drivers/tty/tty.h

··· 99 99 100 100 /* tty_audit.c */ 101 101 #ifdef CONFIG_AUDIT 102 - void tty_audit_add_data(struct tty_struct *tty, const void *data, size_t size); 103 - void tty_audit_tiocsti(struct tty_struct *tty, char ch); 102 + void tty_audit_add_data(const struct tty_struct *tty, const void *data, 103 + size_t size); 104 + void tty_audit_tiocsti(const struct tty_struct *tty, char ch); 104 105 #else 105 - static inline void tty_audit_add_data(struct tty_struct *tty, const void *data, 106 - size_t size) 106 + static inline void tty_audit_add_data(const struct tty_struct *tty, 107 + const void *data, size_t size) 107 108 { 108 109 } 109 - static inline void tty_audit_tiocsti(struct tty_struct *tty, char ch) 110 + static inline void tty_audit_tiocsti(const struct tty_struct *tty, char ch) 110 111 { 111 112 } 112 113 #endif

+21 -20

drivers/tty/tty_audit.c

··· 15 15 struct tty_audit_buf { 16 16 struct mutex mutex; /* Protects all data below */ 17 17 dev_t dev; /* The TTY which the data is from */ 18 - unsigned icanon:1; 18 + bool icanon; 19 19 size_t valid; 20 20 unsigned char *data; /* Allocated size N_TTY_BUF_SIZE */ 21 21 }; ··· 33 33 { 34 34 struct tty_audit_buf *buf; 35 35 36 - buf = kmalloc(sizeof(*buf), GFP_KERNEL); 36 + buf = kzalloc(sizeof(*buf), GFP_KERNEL); 37 37 if (!buf) 38 38 goto err; 39 + 39 40 buf->data = kmalloc(N_TTY_BUF_SIZE, GFP_KERNEL); 40 41 if (!buf->data) 41 42 goto err_buf; 43 + 42 44 mutex_init(&buf->mutex); 43 - buf->dev = MKDEV(0, 0); 44 - buf->icanon = 0; 45 - buf->valid = 0; 45 + 46 46 return buf; 47 47 48 48 err_buf: ··· 59 59 } 60 60 61 61 static void tty_audit_log(const char *description, dev_t dev, 62 - unsigned char *data, size_t size) 62 + const unsigned char *data, size_t size) 63 63 { 64 64 struct audit_buffer *ab; 65 65 pid_t pid = task_pid_nr(current); 66 66 uid_t uid = from_kuid(&init_user_ns, task_uid(current)); 67 67 uid_t loginuid = from_kuid(&init_user_ns, audit_get_loginuid(current)); 68 68 unsigned int sessionid = audit_get_sessionid(current); 69 + char name[TASK_COMM_LEN]; 69 70 70 71 ab = audit_log_start(audit_context(), GFP_KERNEL, AUDIT_TTY); 71 - if (ab) { 72 - char name[sizeof(current->comm)]; 72 + if (!ab) 73 + return; 73 74 74 - audit_log_format(ab, "%s pid=%u uid=%u auid=%u ses=%u major=%d" 75 - " minor=%d comm=", description, pid, uid, 76 - loginuid, sessionid, MAJOR(dev), MINOR(dev)); 77 - get_task_comm(name, current); 78 - audit_log_untrustedstring(ab, name); 79 - audit_log_format(ab, " data="); 80 - audit_log_n_hex(ab, data, size); 81 - audit_log_end(ab); 82 - } 75 + audit_log_format(ab, "%s pid=%u uid=%u auid=%u ses=%u major=%d minor=%d comm=", 76 + description, pid, uid, loginuid, sessionid, 77 + MAJOR(dev), MINOR(dev)); 78 + get_task_comm(name, current); 79 + audit_log_untrustedstring(ab, name); 80 + audit_log_format(ab, " data="); 81 + audit_log_n_hex(ab, data, size); 82 + audit_log_end(ab); 83 83 } 84 84 85 85 /* ··· 134 134 /* 135 135 * tty_audit_tiocsti - Log TIOCSTI 136 136 */ 137 - void tty_audit_tiocsti(struct tty_struct *tty, char ch) 137 + void tty_audit_tiocsti(const struct tty_struct *tty, char ch) 138 138 { 139 139 dev_t dev; 140 140 ··· 199 199 * 200 200 * Audit @data of @size from @tty, if necessary. 201 201 */ 202 - void tty_audit_add_data(struct tty_struct *tty, const void *data, size_t size) 202 + void tty_audit_add_data(const struct tty_struct *tty, const void *data, 203 + size_t size) 203 204 { 204 205 struct tty_audit_buf *buf; 205 - unsigned int icanon = !!L_ICANON(tty); 206 206 unsigned int audit_tty; 207 + bool icanon = L_ICANON(tty); 207 208 dev_t dev; 208 209 209 210 audit_tty = READ_ONCE(current->signal->audit_tty);

+20 -11

drivers/tty/tty_io.c

··· 101 101 #include <linux/compat.h> 102 102 #include <linux/uaccess.h> 103 103 #include <linux/termios_internal.h> 104 + #include <linux/fs.h> 104 105 105 106 #include <linux/kbd_kern.h> 106 107 #include <linux/vt_kern.h> ··· 812 811 } 813 812 EXPORT_SYMBOL(start_tty); 814 813 815 - static void tty_update_time(struct timespec64 *time) 814 + static void tty_update_time(struct tty_struct *tty, bool mtime) 816 815 { 817 816 time64_t sec = ktime_get_real_seconds(); 817 + struct tty_file_private *priv; 818 818 819 - /* 820 - * We only care if the two values differ in anything other than the 821 - * lower three bits (i.e every 8 seconds). If so, then we can update 822 - * the time of the tty device, otherwise it could be construded as a 823 - * security leak to let userspace know the exact timing of the tty. 824 - */ 825 - if ((sec ^ time->tv_sec) & ~7) 826 - time->tv_sec = sec; 819 + spin_lock(&tty->files_lock); 820 + list_for_each_entry(priv, &tty->tty_files, list) { 821 + struct inode *inode = file_inode(priv->file); 822 + struct timespec64 *time = mtime ? &inode->i_mtime : &inode->i_atime; 823 + 824 + /* 825 + * We only care if the two values differ in anything other than the 826 + * lower three bits (i.e every 8 seconds). If so, then we can update 827 + * the time of the tty device, otherwise it could be construded as a 828 + * security leak to let userspace know the exact timing of the tty. 829 + */ 830 + if ((sec ^ time->tv_sec) & ~7) 831 + time->tv_sec = sec; 832 + } 833 + spin_unlock(&tty->files_lock); 827 834 } 828 835 829 836 /* ··· 937 928 tty_ldisc_deref(ld); 938 929 939 930 if (i > 0) 940 - tty_update_time(&inode->i_atime); 931 + tty_update_time(tty, false); 941 932 942 933 return i; 943 934 } ··· 1045 1036 cond_resched(); 1046 1037 } 1047 1038 if (written) { 1048 - tty_update_time(&file_inode(file)->i_mtime); 1039 + tty_update_time(tty, true); 1049 1040 ret = written; 1050 1041 } 1051 1042 out:

+38 -7

include/linux/serial_8250.h

··· 7 7 #ifndef _LINUX_SERIAL_8250_H 8 8 #define _LINUX_SERIAL_8250_H 9 9 10 + #include <linux/errno.h> 10 11 #include <linux/serial_core.h> 11 12 #include <linux/serial_reg.h> 12 13 #include <linux/platform_device.h> 13 14 15 + struct uart_8250_port; 16 + 14 17 /* 15 18 * This is the platform device platform_data structure 19 + * 20 + * @mapsize: Port size for ioremap() 21 + * @bugs: Port bugs 22 + * 23 + * @dl_read: ``u32 ()(struct uart_8250_port *up)`` 24 + * 25 + * UART divisor latch read. 26 + * 27 + * @dl_write: ``void ()(struct uart_8250_port *up, u32 value)`` 28 + * 29 + * Write @value into UART divisor latch. 30 + * 31 + * Locking: Caller holds port's lock. 16 32 */ 17 33 struct plat_serial8250_port { 18 34 unsigned long iobase; /* io base address */ 19 35 void __iomem *membase; /* ioremap cookie or NULL */ 20 36 resource_size_t mapbase; /* resource base */ 37 + resource_size_t mapsize; 21 38 unsigned int uartclk; /* UART clock rate */ 22 39 unsigned int irq; /* interrupt number */ 23 40 unsigned long irqflags; /* request_irq flags */ ··· 45 28 unsigned char has_sysrq; /* supports magic SysRq */ 46 29 unsigned int type; /* If UPF_FIXED_TYPE */ 47 30 upf_t flags; /* UPF_* flags */ 31 + u16 bugs; /* port bugs */ 48 32 unsigned int (*serial_in)(struct uart_port *, int); 49 33 void (*serial_out)(struct uart_port *, int, int); 34 + u32 (*dl_read)(struct uart_8250_port *up); 35 + void (*dl_write)(struct uart_8250_port *up, u32 value); 50 36 void (*set_termios)(struct uart_port *, 51 37 struct ktermios *new, 52 38 const struct ktermios *old); ··· 110 90 * their own 8250 ports without registering their own 111 91 * platform device. Using these will make your driver 112 92 * dependent on the 8250 driver. 93 + * 94 + * @dl_read: ``u32 ()(struct uart_8250_port *port)`` 95 + * 96 + * UART divisor latch read. 97 + * 98 + * @dl_write: ``void ()(struct uart_8250_port *port, u32 value)`` 99 + * 100 + * Write @value into UART divisor latch. 101 + * 102 + * Locking: Caller holds port's lock. 113 103 */ 114 - 115 104 struct uart_8250_port { 116 105 struct uart_port port; 117 106 struct timer_list timer; /* "no irq" timer */ 118 107 struct list_head list; /* ports on this IRQ */ 119 108 u32 capabilities; /* port capabilities */ 120 - unsigned short bugs; /* port bugs */ 121 - bool fifo_bug; /* min RX trigger if enabled */ 109 + u16 bugs; /* port bugs */ 122 110 unsigned int tx_loadsz; /* transmit fifo load size */ 123 111 unsigned char acr; 124 112 unsigned char fcr; ··· 157 129 const struct uart_8250_ops *ops; 158 130 159 131 /* 8250 specific callbacks */ 160 - int (*dl_read)(struct uart_8250_port *); 161 - void (*dl_write)(struct uart_8250_port *, int); 132 + u32 (*dl_read)(struct uart_8250_port *up); 133 + void (*dl_write)(struct uart_8250_port *up, u32 value); 162 134 163 135 struct uart_8250_em485 *em485; 164 136 void (*rs485_start_tx)(struct uart_8250_port *); ··· 211 183 u32 *capabilities)); 212 184 213 185 #ifdef CONFIG_SERIAL_8250_RT288X 214 - unsigned int au_serial_in(struct uart_port *p, int offset); 215 - void au_serial_out(struct uart_port *p, int offset, int value); 186 + int rt288x_setup(struct uart_port *p); 187 + int au_platform_setup(struct plat_serial8250_port *p); 188 + #else 189 + static inline int rt288x_setup(struct uart_port *p) { return -ENODEV; } 190 + static inline int au_platform_setup(struct plat_serial8250_port *p) { return -ENODEV; } 216 191 #endif 217 192 218 193 #endif

+5 -2

include/linux/serial_core.h

··· 28 28 29 29 struct uart_port; 30 30 struct serial_struct; 31 + struct serial_port_device; 31 32 struct device; 32 33 struct gpio_desc; 33 34 ··· 459 458 struct serial_rs485 *rs485); 460 459 int (*iso7816_config)(struct uart_port *, 461 460 struct serial_iso7816 *iso7816); 461 + int ctrl_id; /* optional serial core controller id */ 462 462 unsigned int irq; /* irq number */ 463 463 unsigned long irqflags; /* irq flags */ 464 464 unsigned int uartclk; /* base uart clock */ ··· 565 563 unsigned int minor; 566 564 resource_size_t mapbase; /* for ioremap */ 567 565 resource_size_t mapsize; 568 - struct device *dev; /* parent device */ 566 + struct device *dev; /* serial port physical parent device */ 567 + struct serial_port_device *port_dev; /* serial core port device */ 569 568 570 569 unsigned long sysrq; /* sysrq timeout */ 571 570 unsigned int sysrq_ch; /* char for sysrq */ ··· 856 853 int uart_register_driver(struct uart_driver *uart); 857 854 void uart_unregister_driver(struct uart_driver *uart); 858 855 int uart_add_one_port(struct uart_driver *reg, struct uart_port *port); 859 - int uart_remove_one_port(struct uart_driver *reg, struct uart_port *port); 856 + void uart_remove_one_port(struct uart_driver *reg, struct uart_port *port); 860 857 bool uart_match_port(const struct uart_port *port1, 861 858 const struct uart_port *port2); 862 859

+1

tools/testing/selftests/Makefile

··· 87 87 endif 88 88 TARGETS += tmpfs 89 89 TARGETS += tpm2 90 + TARGETS += tty 90 91 TARGETS += user 91 92 TARGETS += vDSO 92 93 TARGETS += mm

+2

tools/testing/selftests/tty/.gitignore

··· 1 + # SPDX-License-Identifier: GPL-2.0-only 2 + tty_tstamp_update

+5

tools/testing/selftests/tty/Makefile

··· 1 + # SPDX-License-Identifier: GPL-2.0 2 + CFLAGS = -O2 -Wall 3 + TEST_GEN_PROGS := tty_tstamp_update 4 + 5 + include ../lib.mk

+88

tools/testing/selftests/tty/tty_tstamp_update.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + 3 + #include <errno.h> 4 + #include <stdbool.h> 5 + #include <stdio.h> 6 + #include <stdlib.h> 7 + #include <string.h> 8 + #include <sys/stat.h> 9 + #include <unistd.h> 10 + #include <linux/limits.h> 11 + 12 + #include "../kselftest.h" 13 + 14 + #define MIN_TTY_PATH_LEN 8 15 + 16 + static bool tty_valid(char *tty) 17 + { 18 + if (strlen(tty) < MIN_TTY_PATH_LEN) 19 + return false; 20 + 21 + if (strncmp(tty, "/dev/tty", MIN_TTY_PATH_LEN) == 0 || 22 + strncmp(tty, "/dev/pts", MIN_TTY_PATH_LEN) == 0) 23 + return true; 24 + 25 + return false; 26 + } 27 + 28 + static int write_dev_tty(void) 29 + { 30 + FILE *f; 31 + int r = 0; 32 + 33 + f = fopen("/dev/tty", "r+"); 34 + if (!f) 35 + return -errno; 36 + 37 + r = fprintf(f, "hello, world!\n"); 38 + if (r != strlen("hello, world!\n")) 39 + r = -EIO; 40 + 41 + fclose(f); 42 + return r; 43 + } 44 + 45 + int main(int argc, char **argv) 46 + { 47 + int r; 48 + char tty[PATH_MAX] = {}; 49 + struct stat st1, st2; 50 + 51 + ksft_print_header(); 52 + ksft_set_plan(1); 53 + 54 + r = readlink("/proc/self/fd/0", tty, PATH_MAX); 55 + if (r < 0) 56 + ksft_exit_fail_msg("readlink on /proc/self/fd/0 failed: %m\n"); 57 + 58 + if (!tty_valid(tty)) 59 + ksft_exit_skip("invalid tty path '%s'\n", tty); 60 + 61 + r = stat(tty, &st1); 62 + if (r < 0) 63 + ksft_exit_fail_msg("stat failed on tty path '%s': %m\n", tty); 64 + 65 + /* We need to wait at least 8 seconds in order to observe timestamp change */ 66 + /* https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=fbf47635315ab308c9b58a1ea0906e711a9228de */ 67 + sleep(10); 68 + 69 + r = write_dev_tty(); 70 + if (r < 0) 71 + ksft_exit_fail_msg("failed to write to /dev/tty: %s\n", 72 + strerror(-r)); 73 + 74 + r = stat(tty, &st2); 75 + if (r < 0) 76 + ksft_exit_fail_msg("stat failed on tty path '%s': %m\n", tty); 77 + 78 + /* We wrote to the terminal so timestamps should have been updated */ 79 + if (st1.st_atim.tv_sec == st2.st_atim.tv_sec && 80 + st1.st_mtim.tv_sec == st2.st_mtim.tv_sec) { 81 + ksft_test_result_fail("tty timestamps not updated\n"); 82 + ksft_exit_fail(); 83 + } 84 + 85 + ksft_test_result_pass( 86 + "timestamps of terminal '%s' updated after write to /dev/tty\n", tty); 87 + return EXIT_SUCCESS; 88 + }

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