Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: qcom-qmp-ufs: Add SM7150 support
Add the tables and constants for init sequences for UFS QMP phy found in
SM7150 SoC.
Signed-off-by: David Wronek <davidwronek@gmail.com>
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230311231733.141806-3-danila@jiaxyga.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
David Wronek
and committed by
Vinod Koul
868c2a6c
001c00ef
+61
+61
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+61
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
···
349
349
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
350
350
};
351
351
352
+
static const struct qmp_phy_init_tbl sm7150_ufsphy_rx[] = {
353
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
354
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
355
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
356
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
357
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
358
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
359
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
360
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
361
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
362
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
363
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
364
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
365
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5b),
366
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
367
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
368
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
369
+
};
370
+
371
+
static const struct qmp_phy_init_tbl sm7150_ufsphy_pcs[] = {
372
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6f),
373
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
374
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
375
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
376
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
377
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
378
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
379
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
380
+
};
381
+
352
382
static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = {
353
383
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
354
384
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
···
937
907
.vreg_list = qmp_phy_vreg_l,
938
908
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
939
909
.regs = ufsphy_v2_regs_layout,
910
+
911
+
.no_pcs_sw_reset = true,
912
+
};
913
+
914
+
static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {
915
+
.lanes = 1,
916
+
917
+
.offsets = &qmp_ufs_offsets,
918
+
919
+
.tbls = {
920
+
.serdes = sdm845_ufsphy_serdes,
921
+
.serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
922
+
.tx = sdm845_ufsphy_tx,
923
+
.tx_num = ARRAY_SIZE(sdm845_ufsphy_tx),
924
+
.rx = sm7150_ufsphy_rx,
925
+
.rx_num = ARRAY_SIZE(sm7150_ufsphy_rx),
926
+
.pcs = sm7150_ufsphy_pcs,
927
+
.pcs_num = ARRAY_SIZE(sm7150_ufsphy_pcs),
928
+
},
929
+
.tbls_hs_b = {
930
+
.serdes = sdm845_ufsphy_hs_b_serdes,
931
+
.serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
932
+
},
933
+
.clk_list = sdm845_ufs_phy_clk_l,
934
+
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
935
+
.vreg_list = qmp_phy_vreg_l,
936
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
937
+
.regs = ufsphy_v3_regs_layout,
940
938
941
939
.no_pcs_sw_reset = true,
942
940
};
···
1618
1560
}, {
1619
1561
.compatible = "qcom,sm6350-qmp-ufs-phy",
1620
1562
.data = &sdm845_ufsphy_cfg,
1563
+
}, {
1564
+
.compatible = "qcom,sm7150-qmp-ufs-phy",
1565
+
.data = &sm7150_ufsphy_cfg,
1621
1566
}, {
1622
1567
.compatible = "qcom,sm8150-qmp-ufs-phy",
1623
1568
.data = &sm8150_ufsphy_cfg,