Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

+1

Documentation/arm64/silicon-errata.txt

··· 57 57 | ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 | 58 58 | ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 | 59 59 | ARM | Cortex-A76 | #1188873 | ARM64_ERRATUM_1188873 | 60 + | ARM | Cortex-A76 | #1286807 | ARM64_ERRATUM_1286807 | 60 61 | ARM | MMU-500 | #841119,#826419 | N/A | 61 62 | | | | | 62 63 | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |

+25

arch/arm64/Kconfig

··· 497 497 498 498 If unsure, say Y. 499 499 500 + config ARM64_ERRATUM_1286807 501 + bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 502 + default y 503 + select ARM64_WORKAROUND_REPEAT_TLBI 504 + help 505 + This option adds workaround for ARM Cortex-A76 erratum 1286807 506 + 507 + On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 508 + address for a cacheable mapping of a location is being 509 + accessed by a core while another core is remapping the virtual 510 + address to a new physical page using the recommended 511 + break-before-make sequence, then under very rare circumstances 512 + TLBI+DSB completes before a read using the translation being 513 + invalidated has been observed by other observers. The 514 + workaround repeats the TLBI+DSB operation. 515 + 516 + If unsure, say Y. 517 + 500 518 config CAVIUM_ERRATUM_22375 501 519 bool "Cavium erratum 22375, 24313" 502 520 default y ··· 584 566 is unchanged. Work around the erratum by invalidating the walk cache 585 567 entries for the trampoline before entering the kernel proper. 586 568 569 + config ARM64_WORKAROUND_REPEAT_TLBI 570 + bool 571 + help 572 + Enable the repeat TLBI workaround for Falkor erratum 1009 and 573 + Cortex-A76 erratum 1286807. 574 + 587 575 config QCOM_FALKOR_ERRATUM_1009 588 576 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 589 577 default y 578 + select ARM64_WORKAROUND_REPEAT_TLBI 590 579 help 591 580 On Falkor v1, the CPU may prematurely complete a DSB following a 592 581 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation

+13

arch/arm64/include/asm/ftrace.h

··· 56 56 { 57 57 return is_compat_task(); 58 58 } 59 + 60 + #define ARCH_HAS_SYSCALL_MATCH_SYM_NAME 61 + 62 + static inline bool arch_syscall_match_sym_name(const char *sym, 63 + const char *name) 64 + { 65 + /* 66 + * Since all syscall functions have __arm64_ prefix, we must skip it. 67 + * However, as we described above, we decided to ignore compat 68 + * syscalls, so we don't care about __arm64_compat_ prefix here. 69 + */ 70 + return !strcmp(sym + 8, name); 71 + } 59 72 #endif /* ifndef __ASSEMBLY__ */ 60 73 61 74 #endif /* __ASM_FTRACE_H */

+2 -2

arch/arm64/include/asm/tlbflush.h

··· 41 41 ALTERNATIVE("nop\n nop", \ 42 42 "dsb ish\n tlbi " #op, \ 43 43 ARM64_WORKAROUND_REPEAT_TLBI, \ 44 - CONFIG_QCOM_FALKOR_ERRATUM_1009) \ 44 + CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \ 45 45 : : ) 46 46 47 47 #define __TLBI_1(op, arg) asm ("tlbi " #op ", %0\n" \ 48 48 ALTERNATIVE("nop\n nop", \ 49 49 "dsb ish\n tlbi " #op ", %0", \ 50 50 ARM64_WORKAROUND_REPEAT_TLBI, \ 51 - CONFIG_QCOM_FALKOR_ERRATUM_1009) \ 51 + CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \ 52 52 : : "r" (arg)) 53 53 54 54 #define __TLBI_N(op, arg, n, ...) __TLBI_##n(op, arg)

+17 -3

arch/arm64/kernel/cpu_errata.c

··· 570 570 571 571 #endif 572 572 573 + #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI 574 + 575 + static const struct midr_range arm64_repeat_tlbi_cpus[] = { 576 + #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 577 + MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0, 0, 0, 0), 578 + #endif 579 + #ifdef CONFIG_ARM64_ERRATUM_1286807 580 + MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0), 581 + #endif 582 + {}, 583 + }; 584 + 585 + #endif 586 + 573 587 const struct arm64_cpu_capabilities arm64_errata[] = { 574 588 #if defined(CONFIG_ARM64_ERRATUM_826319) || \ 575 589 defined(CONFIG_ARM64_ERRATUM_827319) || \ ··· 709 695 .matches = is_kryo_midr, 710 696 }, 711 697 #endif 712 - #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 698 + #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI 713 699 { 714 - .desc = "Qualcomm Technologies Falkor erratum 1009", 700 + .desc = "Qualcomm erratum 1009, ARM erratum 1286807", 715 701 .capability = ARM64_WORKAROUND_REPEAT_TLBI, 716 - ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0), 702 + ERRATA_MIDR_RANGE_LIST(arm64_repeat_tlbi_cpus), 717 703 }, 718 704 #endif 719 705 #ifdef CONFIG_ARM64_ERRATUM_858921

+1 -1

drivers/acpi/arm64/iort.c

··· 700 700 */ 701 701 static struct irq_domain *iort_get_platform_device_domain(struct device *dev) 702 702 { 703 - struct acpi_iort_node *node, *msi_parent; 703 + struct acpi_iort_node *node, *msi_parent = NULL; 704 704 struct fwnode_handle *iort_fwnode; 705 705 struct acpi_iort_its_group *its; 706 706 int i;

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