Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"Two build fixes for a couple clk drivers and a fix for the Unisoc
serial clk where we want to keep it on for earlycon"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: sprd: don't gate uart console clock
clk: mmp2: fix link error without mmp2
clk: asm9260: fix __clk_hw_register_fixed_rate_with_accuracy typo
+35
-41
+1
-1
drivers/clk/clk-asm9260.c
+1
-1
drivers/clk/clk-asm9260.c
···
276
276
277
277
/* TODO: Convert to DT parent scheme */
278
278
ref_clk = of_clk_get_parent_name(np, 0);
279
-
hw = __clk_hw_register_fixed_rate_with_accuracy(NULL, NULL, pll_clk,
279
+
hw = __clk_hw_register_fixed_rate(NULL, NULL, pll_clk,
280
280
ref_clk, NULL, NULL, 0, rate, 0,
281
281
CLK_FIXED_RATE_PARENT_ACCURACY);
282
282
+32
-1
drivers/clk/mmp/clk-pll.c
+32
-1
drivers/clk/mmp/clk-pll.c
···
97
97
.recalc_rate = mmp_clk_pll_recalc_rate,
98
98
};
99
99
100
-
struct clk *mmp_clk_register_pll(char *name,
100
+
static struct clk *mmp_clk_register_pll(char *name,
101
101
unsigned long default_rate,
102
102
void __iomem *enable_reg, u32 enable,
103
103
void __iomem *reg, u8 shift,
···
136
136
kfree(pll);
137
137
138
138
return clk;
139
+
}
140
+
141
+
void mmp_register_pll_clks(struct mmp_clk_unit *unit,
142
+
struct mmp_param_pll_clk *clks,
143
+
void __iomem *base, int size)
144
+
{
145
+
struct clk *clk;
146
+
int i;
147
+
148
+
for (i = 0; i < size; i++) {
149
+
void __iomem *reg = NULL;
150
+
151
+
if (clks[i].offset)
152
+
reg = base + clks[i].offset;
153
+
154
+
clk = mmp_clk_register_pll(clks[i].name,
155
+
clks[i].default_rate,
156
+
base + clks[i].enable_offset,
157
+
clks[i].enable,
158
+
reg, clks[i].shift,
159
+
clks[i].input_rate,
160
+
base + clks[i].postdiv_offset,
161
+
clks[i].postdiv_shift);
162
+
if (IS_ERR(clk)) {
163
+
pr_err("%s: failed to register clock %s\n",
164
+
__func__, clks[i].name);
165
+
continue;
166
+
}
167
+
if (clks[i].id)
168
+
unit->clk_table[clks[i].id] = clk;
169
+
}
139
170
}
-31
drivers/clk/mmp/clk.c
-31
drivers/clk/mmp/clk.c
···
176
176
}
177
177
}
178
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179
-
void mmp_register_pll_clks(struct mmp_clk_unit *unit,
180
-
struct mmp_param_pll_clk *clks,
181
-
void __iomem *base, int size)
182
-
{
183
-
struct clk *clk;
184
-
int i;
185
-
186
-
for (i = 0; i < size; i++) {
187
-
void __iomem *reg = NULL;
188
-
189
-
if (clks[i].offset)
190
-
reg = base + clks[i].offset;
191
-
192
-
clk = mmp_clk_register_pll(clks[i].name,
193
-
clks[i].default_rate,
194
-
base + clks[i].enable_offset,
195
-
clks[i].enable,
196
-
reg, clks[i].shift,
197
-
clks[i].input_rate,
198
-
base + clks[i].postdiv_offset,
199
-
clks[i].postdiv_shift);
200
-
if (IS_ERR(clk)) {
201
-
pr_err("%s: failed to register clock %s\n",
202
-
__func__, clks[i].name);
203
-
continue;
204
-
}
205
-
if (clks[i].id)
206
-
unit->clk_table[clks[i].id] = clk;
207
-
}
208
-
}
209
-
210
179
void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
211
180
struct clk *clk)
212
181
{
-7
drivers/clk/mmp/clk.h
-7
drivers/clk/mmp/clk.h
···
238
238
struct mmp_param_pll_clk *clks,
239
239
void __iomem *base, int size);
240
240
241
-
extern struct clk *mmp_clk_register_pll(char *name,
242
-
unsigned long default_rate,
243
-
void __iomem *enable_reg, u32 enable,
244
-
void __iomem *reg, u8 shift,
245
-
unsigned long input_rate,
246
-
void __iomem *postdiv_reg, u8 postdiv_shift);
247
-
248
241
#define DEFINE_MIX_REG_INFO(w_d, s_d, w_m, s_m, fc) \
249
242
{ \
250
243
.width_div = (w_d), \
+2
-1
drivers/clk/sprd/sc9863a-clk.c
+2
-1
drivers/clk/sprd/sc9863a-clk.c
···
1641
1641
0x1000, BIT(12), 0, 0);
1642
1642
static SPRD_SC_GATE_CLK_FW_NAME(uart0_eb, "uart0-eb", "ext-26m", 0x0,
1643
1643
0x1000, BIT(13), 0, 0);
1644
+
/* uart1_eb is for console, don't gate even if unused */
1644
1645
static SPRD_SC_GATE_CLK_FW_NAME(uart1_eb, "uart1-eb", "ext-26m", 0x0,
1645
-
0x1000, BIT(14), 0, 0);
1646
+
0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
1646
1647
static SPRD_SC_GATE_CLK_FW_NAME(uart2_eb, "uart2-eb", "ext-26m", 0x0,
1647
1648
0x1000, BIT(15), 0, 0);
1648
1649
static SPRD_SC_GATE_CLK_FW_NAME(uart3_eb, "uart3-eb", "ext-26m", 0x0,