Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mips_fixes_4.16_5' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips
Pull MIPS fixes from James Hogan:
"Another miscellaneous pile of MIPS fixes for 4.16:
- lantiq: fixes for clocks and Amazon SE (4.14)
- ralink: fix booting on MT7621 (4.5)
- ralink: fix halt (3.9)"
* tag 'mips_fixes_4.16_5' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips:
MIPS: ralink: Fix booting on MT7621
MIPS: ralink: Remove ralink_halt()
MIPS: lantiq: ase: Enable MFD_SYSCON
MIPS: lantiq: Enable AHB Bus for USB
MIPS: lantiq: Fix Danube USB clock
+27
-30
+2
arch/mips/lantiq/Kconfig
+2
arch/mips/lantiq/Kconfig
+3
-3
arch/mips/lantiq/xway/sysctrl.c
+3
-3
arch/mips/lantiq/xway/sysctrl.c
···
549
549
clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
550
550
ltq_ar9_fpi_hz(), CLOCK_250M);
551
551
clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
552
-
clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
552
+
clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
553
553
clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
554
-
clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
554
+
clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);
555
555
clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
556
556
clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
557
557
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
···
560
560
} else {
561
561
clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
562
562
ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
563
-
clkdev_add_pmu("1f203018.usb2-phy", "ctrl", 1, 0, PMU_USB0);
563
+
clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
564
564
clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
565
565
clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
566
566
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
+22
-20
arch/mips/ralink/mt7621.c
+22
-20
arch/mips/ralink/mt7621.c
···
170
170
u32 n1;
171
171
u32 rev;
172
172
173
+
/* Early detection of CMP support */
174
+
mips_cm_probe();
175
+
mips_cpc_probe();
176
+
177
+
if (mips_cps_numiocu(0)) {
178
+
/*
179
+
* mips_cm_probe() wipes out bootloader
180
+
* config for CM regions and we have to configure them
181
+
* again. This SoC cannot talk to pamlbus devices
182
+
* witout proper iocu region set up.
183
+
*
184
+
* FIXME: it would be better to do this with values
185
+
* from DT, but we need this very early because
186
+
* without this we cannot talk to pretty much anything
187
+
* including serial.
188
+
*/
189
+
write_gcr_reg0_base(MT7621_PALMBUS_BASE);
190
+
write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
191
+
CM_GCR_REGn_MASK_CMTGT_IOCU0);
192
+
__sync();
193
+
}
194
+
173
195
n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
174
196
n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
175
197
···
216
194
217
195
rt2880_pinmux_data = mt7621_pinmux_data;
218
196
219
-
/* Early detection of CMP support */
220
-
mips_cm_probe();
221
-
mips_cpc_probe();
222
-
223
-
if (mips_cps_numiocu(0)) {
224
-
/*
225
-
* mips_cm_probe() wipes out bootloader
226
-
* config for CM regions and we have to configure them
227
-
* again. This SoC cannot talk to pamlbus devices
228
-
* witout proper iocu region set up.
229
-
*
230
-
* FIXME: it would be better to do this with values
231
-
* from DT, but we need this very early because
232
-
* without this we cannot talk to pretty much anything
233
-
* including serial.
234
-
*/
235
-
write_gcr_reg0_base(MT7621_PALMBUS_BASE);
236
-
write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
237
-
CM_GCR_REGn_MASK_CMTGT_IOCU0);
238
-
}
239
197
240
198
if (!register_cps_smp_ops())
241
199
return;
-7
arch/mips/ralink/reset.c
-7
arch/mips/ralink/reset.c
···
96
96
unreachable();
97
97
}
98
98
99
-
static void ralink_halt(void)
100
-
{
101
-
local_irq_disable();
102
-
unreachable();
103
-
}
104
-
105
99
static int __init mips_reboot_setup(void)
106
100
{
107
101
_machine_restart = ralink_restart;
108
-
_machine_halt = ralink_halt;
109
102
110
103
return 0;
111
104
}