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phy: ti: phy-j721e-wiz: set PMA_CMN_REFCLK_DIG_DIV based on reflk rate

For J7200-SR2.0 and AM64 we don't model Common refclock divider as
a clock divider as the divisor rate is fixed based on operating
reference clock frequency. We just program the recommended value
into the register. This simplifies the device tree and implementation
a lot.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20220628122255.24265-8-rogerq@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Roger Quadros and committed by
Vinod Koul 86d11e22 edd473d4

+24
+24
drivers/phy/ti/phy-j721e-wiz.c
··· 24 24 #include <linux/regmap.h> 25 25 #include <linux/reset-controller.h> 26 26 27 + #define REF_CLK_19_2MHZ 19200000 28 + #define REF_CLK_25MHZ 25000000 29 + #define REF_CLK_100MHZ 100000000 30 + #define REF_CLK_156_25MHZ 156250000 31 + 27 32 /* SCM offsets */ 28 33 #define SERDES_SUP_CTRL 0x4400 29 34 ··· 1057 1052 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); 1058 1053 else 1059 1054 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); 1055 + 1056 + switch (wiz->type) { 1057 + case AM64_WIZ_10G: 1058 + case J7200_WIZ_10G: 1059 + switch (rate) { 1060 + case REF_CLK_100MHZ: 1061 + regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2); 1062 + break; 1063 + case REF_CLK_156_25MHZ: 1064 + regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3); 1065 + break; 1066 + default: 1067 + regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0); 1068 + break; 1069 + } 1070 + break; 1071 + default: 1072 + break; 1073 + } 1060 1074 1061 1075 if (wiz->data->pma_cmn_refclk1_int_mode) { 1062 1076 clk = devm_clk_get(dev, "core_ref1_clk");