Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'samsung-pinctrl-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
Samsung pinctrl drivers changes for v6.16
Refactor the driver suspend and resume to handle Google GS101 EINT GPIO
pin banks and add the alive pin bank for that SoC.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+255
-154
+26
-26
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+26
-26
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
···
1419
1419
.pin_banks = exynosautov920_pin_banks0,
1420
1420
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks0),
1421
1421
.eint_wkup_init = exynos_eint_wkup_init,
1422
-
.suspend = exynos_pinctrl_suspend,
1423
-
.resume = exynos_pinctrl_resume,
1422
+
.suspend = exynosautov920_pinctrl_suspend,
1423
+
.resume = exynosautov920_pinctrl_resume,
1424
1424
.retention_data = &exynosautov920_retention_data,
1425
1425
}, {
1426
1426
/* pin-controller instance 1 AUD data */
···
1431
1431
.pin_banks = exynosautov920_pin_banks2,
1432
1432
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks2),
1433
1433
.eint_gpio_init = exynos_eint_gpio_init,
1434
-
.suspend = exynos_pinctrl_suspend,
1435
-
.resume = exynos_pinctrl_resume,
1434
+
.suspend = exynosautov920_pinctrl_suspend,
1435
+
.resume = exynosautov920_pinctrl_resume,
1436
1436
}, {
1437
1437
/* pin-controller instance 3 HSI1 data */
1438
1438
.pin_banks = exynosautov920_pin_banks3,
1439
1439
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks3),
1440
1440
.eint_gpio_init = exynos_eint_gpio_init,
1441
-
.suspend = exynos_pinctrl_suspend,
1442
-
.resume = exynos_pinctrl_resume,
1441
+
.suspend = exynosautov920_pinctrl_suspend,
1442
+
.resume = exynosautov920_pinctrl_resume,
1443
1443
}, {
1444
1444
/* pin-controller instance 4 HSI2 data */
1445
1445
.pin_banks = exynosautov920_pin_banks4,
1446
1446
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks4),
1447
1447
.eint_gpio_init = exynos_eint_gpio_init,
1448
-
.suspend = exynos_pinctrl_suspend,
1449
-
.resume = exynos_pinctrl_resume,
1448
+
.suspend = exynosautov920_pinctrl_suspend,
1449
+
.resume = exynosautov920_pinctrl_resume,
1450
1450
}, {
1451
1451
/* pin-controller instance 5 HSI2UFS data */
1452
1452
.pin_banks = exynosautov920_pin_banks5,
1453
1453
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks5),
1454
1454
.eint_gpio_init = exynos_eint_gpio_init,
1455
-
.suspend = exynos_pinctrl_suspend,
1456
-
.resume = exynos_pinctrl_resume,
1455
+
.suspend = exynosautov920_pinctrl_suspend,
1456
+
.resume = exynosautov920_pinctrl_resume,
1457
1457
}, {
1458
1458
/* pin-controller instance 6 PERIC0 data */
1459
1459
.pin_banks = exynosautov920_pin_banks6,
1460
1460
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks6),
1461
1461
.eint_gpio_init = exynos_eint_gpio_init,
1462
-
.suspend = exynos_pinctrl_suspend,
1463
-
.resume = exynos_pinctrl_resume,
1462
+
.suspend = exynosautov920_pinctrl_suspend,
1463
+
.resume = exynosautov920_pinctrl_resume,
1464
1464
}, {
1465
1465
/* pin-controller instance 7 PERIC1 data */
1466
1466
.pin_banks = exynosautov920_pin_banks7,
1467
1467
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks7),
1468
1468
.eint_gpio_init = exynos_eint_gpio_init,
1469
-
.suspend = exynos_pinctrl_suspend,
1470
-
.resume = exynos_pinctrl_resume,
1469
+
.suspend = exynosautov920_pinctrl_suspend,
1470
+
.resume = exynosautov920_pinctrl_resume,
1471
1471
},
1472
1472
};
1473
1473
···
1762
1762
.pin_banks = gs101_pin_alive,
1763
1763
.nr_banks = ARRAY_SIZE(gs101_pin_alive),
1764
1764
.eint_wkup_init = exynos_eint_wkup_init,
1765
-
.suspend = exynos_pinctrl_suspend,
1766
-
.resume = exynos_pinctrl_resume,
1765
+
.suspend = gs101_pinctrl_suspend,
1766
+
.resume = gs101_pinctrl_resume,
1767
1767
}, {
1768
1768
/* pin banks of gs101 pin-controller (FAR_ALIVE) */
1769
1769
.pin_banks = gs101_pin_far_alive,
1770
1770
.nr_banks = ARRAY_SIZE(gs101_pin_far_alive),
1771
1771
.eint_wkup_init = exynos_eint_wkup_init,
1772
-
.suspend = exynos_pinctrl_suspend,
1773
-
.resume = exynos_pinctrl_resume,
1772
+
.suspend = gs101_pinctrl_suspend,
1773
+
.resume = gs101_pinctrl_resume,
1774
1774
}, {
1775
1775
/* pin banks of gs101 pin-controller (GSACORE) */
1776
1776
.pin_banks = gs101_pin_gsacore,
···
1784
1784
.pin_banks = gs101_pin_peric0,
1785
1785
.nr_banks = ARRAY_SIZE(gs101_pin_peric0),
1786
1786
.eint_gpio_init = exynos_eint_gpio_init,
1787
-
.suspend = exynos_pinctrl_suspend,
1788
-
.resume = exynos_pinctrl_resume,
1787
+
.suspend = gs101_pinctrl_suspend,
1788
+
.resume = gs101_pinctrl_resume,
1789
1789
}, {
1790
1790
/* pin banks of gs101 pin-controller (PERIC1) */
1791
1791
.pin_banks = gs101_pin_peric1,
1792
1792
.nr_banks = ARRAY_SIZE(gs101_pin_peric1),
1793
1793
.eint_gpio_init = exynos_eint_gpio_init,
1794
-
.suspend = exynos_pinctrl_suspend,
1795
-
.resume = exynos_pinctrl_resume,
1794
+
.suspend = gs101_pinctrl_suspend,
1795
+
.resume = gs101_pinctrl_resume,
1796
1796
}, {
1797
1797
/* pin banks of gs101 pin-controller (HSI1) */
1798
1798
.pin_banks = gs101_pin_hsi1,
1799
1799
.nr_banks = ARRAY_SIZE(gs101_pin_hsi1),
1800
1800
.eint_gpio_init = exynos_eint_gpio_init,
1801
-
.suspend = exynos_pinctrl_suspend,
1802
-
.resume = exynos_pinctrl_resume,
1801
+
.suspend = gs101_pinctrl_suspend,
1802
+
.resume = gs101_pinctrl_resume,
1803
1803
}, {
1804
1804
/* pin banks of gs101 pin-controller (HSI2) */
1805
1805
.pin_banks = gs101_pin_hsi2,
1806
1806
.nr_banks = ARRAY_SIZE(gs101_pin_hsi2),
1807
1807
.eint_gpio_init = exynos_eint_gpio_init,
1808
-
.suspend = exynos_pinctrl_suspend,
1809
-
.resume = exynos_pinctrl_resume,
1808
+
.suspend = gs101_pinctrl_suspend,
1809
+
.resume = gs101_pinctrl_resume,
1810
1810
},
1811
1811
};
1812
1812
+184
-116
drivers/pinctrl/samsung/pinctrl-exynos.c
+184
-116
drivers/pinctrl/samsung/pinctrl-exynos.c
···
370
370
u32 eint_mask;
371
371
};
372
372
373
+
static void exynos_eint_update_flt_reg(void __iomem *reg, int cnt, int con)
374
+
{
375
+
unsigned int val, shift;
376
+
int i;
377
+
378
+
val = readl(reg);
379
+
for (i = 0; i < cnt; i++) {
380
+
shift = i * EXYNOS_FLTCON_LEN;
381
+
val &= ~(EXYNOS_FLTCON_DIGITAL << shift);
382
+
val |= con << shift;
383
+
}
384
+
writel(val, reg);
385
+
}
386
+
387
+
/*
388
+
* Set the desired filter (digital or analog delay) and enable it to
389
+
* every pin in the bank. Note the filter selection bitfield is only
390
+
* found on alive banks. The filter determines to what extent signal
391
+
* fluctuations received through the pad are considered glitches.
392
+
*/
393
+
static void exynos_eint_set_filter(struct samsung_pin_bank *bank, int filter)
394
+
{
395
+
unsigned int off = EXYNOS_GPIO_EFLTCON_OFFSET + bank->eint_fltcon_offset;
396
+
void __iomem *reg = bank->drvdata->virt_base + off;
397
+
unsigned int con = EXYNOS_FLTCON_EN | filter;
398
+
399
+
for (int n = 0; n < bank->nr_pins; n += 4)
400
+
exynos_eint_update_flt_reg(reg + n,
401
+
min(bank->nr_pins - n, 4), con);
402
+
}
403
+
373
404
/*
374
405
* exynos_eint_gpio_init() - setup handling of external gpio interrupts.
375
406
* @d: driver data of samsung pinctrl driver.
···
793
762
return 0;
794
763
}
795
764
796
-
static void exynos_pinctrl_suspend_bank(
797
-
struct samsung_pinctrl_drv_data *drvdata,
798
-
struct samsung_pin_bank *bank)
765
+
static void exynos_set_wakeup(struct samsung_pin_bank *bank)
766
+
{
767
+
struct exynos_irq_chip *irq_chip;
768
+
769
+
if (bank->irq_chip) {
770
+
irq_chip = bank->irq_chip;
771
+
irq_chip->set_eint_wakeup_mask(bank->drvdata, irq_chip);
772
+
}
773
+
}
774
+
775
+
void exynos_pinctrl_suspend(struct samsung_pin_bank *bank)
799
776
{
800
777
struct exynos_eint_gpio_save *save = bank->soc_priv;
801
778
const void __iomem *regs = bank->eint_base;
802
779
803
-
if (clk_enable(bank->drvdata->pclk)) {
804
-
dev_err(bank->gpio_chip.parent,
805
-
"unable to enable clock for saving state\n");
806
-
return;
780
+
if (bank->eint_type == EINT_TYPE_GPIO) {
781
+
save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
782
+
+ bank->eint_offset);
783
+
save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
784
+
+ 2 * bank->eint_offset);
785
+
save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
786
+
+ 2 * bank->eint_offset + 4);
787
+
save->eint_mask = readl(regs + bank->irq_chip->eint_mask
788
+
+ bank->eint_offset);
789
+
790
+
pr_debug("%s: save con %#010x\n",
791
+
bank->name, save->eint_con);
792
+
pr_debug("%s: save fltcon0 %#010x\n",
793
+
bank->name, save->eint_fltcon0);
794
+
pr_debug("%s: save fltcon1 %#010x\n",
795
+
bank->name, save->eint_fltcon1);
796
+
pr_debug("%s: save mask %#010x\n",
797
+
bank->name, save->eint_mask);
798
+
} else if (bank->eint_type == EINT_TYPE_WKUP) {
799
+
exynos_set_wakeup(bank);
807
800
}
808
-
809
-
save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
810
-
+ bank->eint_offset);
811
-
save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
812
-
+ 2 * bank->eint_offset);
813
-
save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
814
-
+ 2 * bank->eint_offset + 4);
815
-
save->eint_mask = readl(regs + bank->irq_chip->eint_mask
816
-
+ bank->eint_offset);
817
-
818
-
clk_disable(bank->drvdata->pclk);
819
-
820
-
pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
821
-
pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
822
-
pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
823
-
pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
824
801
}
825
802
826
-
static void exynosauto_pinctrl_suspend_bank(struct samsung_pinctrl_drv_data *drvdata,
827
-
struct samsung_pin_bank *bank)
803
+
void gs101_pinctrl_suspend(struct samsung_pin_bank *bank)
828
804
{
829
805
struct exynos_eint_gpio_save *save = bank->soc_priv;
830
806
const void __iomem *regs = bank->eint_base;
831
807
832
-
if (clk_enable(bank->drvdata->pclk)) {
833
-
dev_err(bank->gpio_chip.parent,
834
-
"unable to enable clock for saving state\n");
835
-
return;
808
+
if (bank->eint_type == EINT_TYPE_GPIO) {
809
+
save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
810
+
+ bank->eint_offset);
811
+
812
+
save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
813
+
+ bank->eint_fltcon_offset);
814
+
815
+
/* fltcon1 register only exists for pins 4-7 */
816
+
if (bank->nr_pins > 4)
817
+
save->eint_fltcon1 = readl(regs +
818
+
EXYNOS_GPIO_EFLTCON_OFFSET
819
+
+ bank->eint_fltcon_offset + 4);
820
+
821
+
save->eint_mask = readl(regs + bank->irq_chip->eint_mask
822
+
+ bank->eint_offset);
823
+
824
+
pr_debug("%s: save con %#010x\n",
825
+
bank->name, save->eint_con);
826
+
pr_debug("%s: save fltcon0 %#010x\n",
827
+
bank->name, save->eint_fltcon0);
828
+
if (bank->nr_pins > 4)
829
+
pr_debug("%s: save fltcon1 %#010x\n",
830
+
bank->name, save->eint_fltcon1);
831
+
pr_debug("%s: save mask %#010x\n",
832
+
bank->name, save->eint_mask);
833
+
} else if (bank->eint_type == EINT_TYPE_WKUP) {
834
+
exynos_set_wakeup(bank);
835
+
exynos_eint_set_filter(bank, EXYNOS_FLTCON_ANALOG);
836
836
}
837
-
838
-
save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset);
839
-
save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset);
840
-
841
-
clk_disable(bank->drvdata->pclk);
842
-
843
-
pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
844
-
pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
845
837
}
846
838
847
-
void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
839
+
void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank)
848
840
{
849
-
struct samsung_pin_bank *bank = drvdata->pin_banks;
850
-
struct exynos_irq_chip *irq_chip = NULL;
851
-
int i;
841
+
struct exynos_eint_gpio_save *save = bank->soc_priv;
842
+
const void __iomem *regs = bank->eint_base;
852
843
853
-
for (i = 0; i < drvdata->nr_banks; ++i, ++bank) {
854
-
if (bank->eint_type == EINT_TYPE_GPIO) {
855
-
if (bank->eint_con_offset)
856
-
exynosauto_pinctrl_suspend_bank(drvdata, bank);
857
-
else
858
-
exynos_pinctrl_suspend_bank(drvdata, bank);
859
-
}
860
-
else if (bank->eint_type == EINT_TYPE_WKUP) {
861
-
if (!irq_chip) {
862
-
irq_chip = bank->irq_chip;
863
-
irq_chip->set_eint_wakeup_mask(drvdata,
864
-
irq_chip);
865
-
}
866
-
}
844
+
if (bank->eint_type == EINT_TYPE_GPIO) {
845
+
save->eint_con = readl(regs + bank->pctl_offset +
846
+
bank->eint_con_offset);
847
+
save->eint_mask = readl(regs + bank->pctl_offset +
848
+
bank->eint_mask_offset);
849
+
pr_debug("%s: save con %#010x\n",
850
+
bank->name, save->eint_con);
851
+
pr_debug("%s: save mask %#010x\n",
852
+
bank->name, save->eint_mask);
853
+
} else if (bank->eint_type == EINT_TYPE_WKUP) {
854
+
exynos_set_wakeup(bank);
867
855
}
868
856
}
869
857
870
-
static void exynos_pinctrl_resume_bank(
871
-
struct samsung_pinctrl_drv_data *drvdata,
872
-
struct samsung_pin_bank *bank)
858
+
void gs101_pinctrl_resume(struct samsung_pin_bank *bank)
859
+
{
860
+
struct exynos_eint_gpio_save *save = bank->soc_priv;
861
+
862
+
void __iomem *regs = bank->eint_base;
863
+
void __iomem *eint_fltcfg0 = regs + EXYNOS_GPIO_EFLTCON_OFFSET
864
+
+ bank->eint_fltcon_offset;
865
+
866
+
if (bank->eint_type == EINT_TYPE_GPIO) {
867
+
pr_debug("%s: con %#010x => %#010x\n", bank->name,
868
+
readl(regs + EXYNOS_GPIO_ECON_OFFSET
869
+
+ bank->eint_offset), save->eint_con);
870
+
871
+
pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
872
+
readl(eint_fltcfg0), save->eint_fltcon0);
873
+
874
+
/* fltcon1 register only exists for pins 4-7 */
875
+
if (bank->nr_pins > 4)
876
+
pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
877
+
readl(eint_fltcfg0 + 4), save->eint_fltcon1);
878
+
879
+
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
880
+
readl(regs + bank->irq_chip->eint_mask
881
+
+ bank->eint_offset), save->eint_mask);
882
+
883
+
writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
884
+
+ bank->eint_offset);
885
+
writel(save->eint_fltcon0, eint_fltcfg0);
886
+
887
+
if (bank->nr_pins > 4)
888
+
writel(save->eint_fltcon1, eint_fltcfg0 + 4);
889
+
writel(save->eint_mask, regs + bank->irq_chip->eint_mask
890
+
+ bank->eint_offset);
891
+
} else if (bank->eint_type == EINT_TYPE_WKUP) {
892
+
exynos_eint_set_filter(bank, EXYNOS_FLTCON_DIGITAL);
893
+
}
894
+
}
895
+
896
+
void exynos_pinctrl_resume(struct samsung_pin_bank *bank)
873
897
{
874
898
struct exynos_eint_gpio_save *save = bank->soc_priv;
875
899
void __iomem *regs = bank->eint_base;
876
900
877
-
if (clk_enable(bank->drvdata->pclk)) {
878
-
dev_err(bank->gpio_chip.parent,
879
-
"unable to enable clock for restoring state\n");
880
-
return;
901
+
if (bank->eint_type == EINT_TYPE_GPIO) {
902
+
pr_debug("%s: con %#010x => %#010x\n", bank->name,
903
+
readl(regs + EXYNOS_GPIO_ECON_OFFSET
904
+
+ bank->eint_offset), save->eint_con);
905
+
pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
906
+
readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
907
+
+ 2 * bank->eint_offset), save->eint_fltcon0);
908
+
pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
909
+
readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
910
+
+ 2 * bank->eint_offset + 4),
911
+
save->eint_fltcon1);
912
+
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
913
+
readl(regs + bank->irq_chip->eint_mask
914
+
+ bank->eint_offset), save->eint_mask);
915
+
916
+
writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
917
+
+ bank->eint_offset);
918
+
writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
919
+
+ 2 * bank->eint_offset);
920
+
writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
921
+
+ 2 * bank->eint_offset + 4);
922
+
writel(save->eint_mask, regs + bank->irq_chip->eint_mask
923
+
+ bank->eint_offset);
881
924
}
882
-
883
-
pr_debug("%s: con %#010x => %#010x\n", bank->name,
884
-
readl(regs + EXYNOS_GPIO_ECON_OFFSET
885
-
+ bank->eint_offset), save->eint_con);
886
-
pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
887
-
readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
888
-
+ 2 * bank->eint_offset), save->eint_fltcon0);
889
-
pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
890
-
readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
891
-
+ 2 * bank->eint_offset + 4), save->eint_fltcon1);
892
-
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
893
-
readl(regs + bank->irq_chip->eint_mask
894
-
+ bank->eint_offset), save->eint_mask);
895
-
896
-
writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
897
-
+ bank->eint_offset);
898
-
writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
899
-
+ 2 * bank->eint_offset);
900
-
writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
901
-
+ 2 * bank->eint_offset + 4);
902
-
writel(save->eint_mask, regs + bank->irq_chip->eint_mask
903
-
+ bank->eint_offset);
904
-
905
-
clk_disable(bank->drvdata->pclk);
906
925
}
907
926
908
-
static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvdata,
909
-
struct samsung_pin_bank *bank)
927
+
void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank)
910
928
{
911
929
struct exynos_eint_gpio_save *save = bank->soc_priv;
912
930
void __iomem *regs = bank->eint_base;
913
931
914
-
if (clk_enable(bank->drvdata->pclk)) {
915
-
dev_err(bank->gpio_chip.parent,
916
-
"unable to enable clock for restoring state\n");
917
-
return;
932
+
if (bank->eint_type == EINT_TYPE_GPIO) {
933
+
/* exynosautov920 has eint_con_offset for all but one bank */
934
+
if (!bank->eint_con_offset)
935
+
exynos_pinctrl_resume(bank);
936
+
937
+
pr_debug("%s: con %#010x => %#010x\n", bank->name,
938
+
readl(regs + bank->pctl_offset + bank->eint_con_offset),
939
+
save->eint_con);
940
+
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
941
+
readl(regs + bank->pctl_offset +
942
+
bank->eint_mask_offset), save->eint_mask);
943
+
944
+
writel(save->eint_con,
945
+
regs + bank->pctl_offset + bank->eint_con_offset);
946
+
writel(save->eint_mask,
947
+
regs + bank->pctl_offset + bank->eint_mask_offset);
918
948
}
919
-
920
-
pr_debug("%s: con %#010x => %#010x\n", bank->name,
921
-
readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con);
922
-
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
923
-
readl(regs + bank->pctl_offset + bank->eint_mask_offset), save->eint_mask);
924
-
925
-
writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset);
926
-
writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset);
927
-
928
-
clk_disable(bank->drvdata->pclk);
929
-
}
930
-
931
-
void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
932
-
{
933
-
struct samsung_pin_bank *bank = drvdata->pin_banks;
934
-
int i;
935
-
936
-
for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
937
-
if (bank->eint_type == EINT_TYPE_GPIO) {
938
-
if (bank->eint_con_offset)
939
-
exynosauto_pinctrl_resume_bank(drvdata, bank);
940
-
else
941
-
exynos_pinctrl_resume_bank(drvdata, bank);
942
-
}
943
949
}
944
950
945
951
static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata)
+26
-2
drivers/pinctrl/samsung/pinctrl-exynos.h
+26
-2
drivers/pinctrl/samsung/pinctrl-exynos.h
···
52
52
#define EXYNOS_EINT_MAX_PER_BANK 8
53
53
#define EXYNOS_EINT_NR_WKUP_EINT
54
54
55
+
/*
56
+
* EINT filter configuration register (on alive banks) has
57
+
* the following layout.
58
+
*
59
+
* BitfieldName[PinNum][Bit:Bit]
60
+
* FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24]
61
+
* FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16]
62
+
* FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8]
63
+
* FLT_EN[0][7] FLT_SEL[0][6] FLT_WIDTH[0][5:0]
64
+
*
65
+
* FLT_EN 0x0 = Disable, 0x1=Enable
66
+
* FLT_SEL 0x0 = Analog delay filter, 0x1 Digital filter (clock count)
67
+
* FLT_WIDTH Filtering width. Valid when FLT_SEL is 0x1
68
+
*/
69
+
70
+
#define EXYNOS_FLTCON_EN BIT(7)
71
+
#define EXYNOS_FLTCON_DIGITAL BIT(6)
72
+
#define EXYNOS_FLTCON_ANALOG (0 << 6)
73
+
#define EXYNOS_FLTCON_LEN 8
74
+
55
75
#define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \
56
76
{ \
57
77
.type = &bank_type_off, \
···
260
240
261
241
int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d);
262
242
int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d);
263
-
void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata);
264
-
void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata);
243
+
void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank);
244
+
void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank);
245
+
void exynos_pinctrl_suspend(struct samsung_pin_bank *bank);
246
+
void exynos_pinctrl_resume(struct samsung_pin_bank *bank);
247
+
void gs101_pinctrl_suspend(struct samsung_pin_bank *bank);
248
+
void gs101_pinctrl_resume(struct samsung_pin_bank *bank);
265
249
struct samsung_retention_ctrl *
266
250
exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata,
267
251
const struct samsung_retention_data *data);
+15
-6
drivers/pinctrl/samsung/pinctrl-samsung.c
+15
-6
drivers/pinctrl/samsung/pinctrl-samsung.c
···
1338
1338
static int __maybe_unused samsung_pinctrl_suspend(struct device *dev)
1339
1339
{
1340
1340
struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev);
1341
+
struct samsung_pin_bank *bank;
1341
1342
int i;
1342
1343
1343
1344
i = clk_enable(drvdata->pclk);
···
1349
1348
}
1350
1349
1351
1350
for (i = 0; i < drvdata->nr_banks; i++) {
1352
-
struct samsung_pin_bank *bank = &drvdata->pin_banks[i];
1351
+
bank = &drvdata->pin_banks[i];
1353
1352
const void __iomem *reg = bank->pctl_base + bank->pctl_offset;
1354
1353
const u8 *offs = bank->type->reg_offset;
1355
1354
const u8 *widths = bank->type->fld_width;
···
1377
1376
}
1378
1377
}
1379
1378
1379
+
for (i = 0; i < drvdata->nr_banks; i++) {
1380
+
bank = &drvdata->pin_banks[i];
1381
+
if (drvdata->suspend)
1382
+
drvdata->suspend(bank);
1383
+
}
1384
+
1380
1385
clk_disable(drvdata->pclk);
1381
1386
1382
-
if (drvdata->suspend)
1383
-
drvdata->suspend(drvdata);
1384
1387
if (drvdata->retention_ctrl && drvdata->retention_ctrl->enable)
1385
1388
drvdata->retention_ctrl->enable(drvdata);
1386
1389
···
1402
1397
static int __maybe_unused samsung_pinctrl_resume(struct device *dev)
1403
1398
{
1404
1399
struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev);
1400
+
struct samsung_pin_bank *bank;
1405
1401
int ret;
1406
1402
int i;
1407
1403
···
1417
1411
return ret;
1418
1412
}
1419
1413
1420
-
if (drvdata->resume)
1421
-
drvdata->resume(drvdata);
1414
+
for (i = 0; i < drvdata->nr_banks; i++) {
1415
+
bank = &drvdata->pin_banks[i];
1416
+
if (drvdata->resume)
1417
+
drvdata->resume(bank);
1418
+
}
1422
1419
1423
1420
for (i = 0; i < drvdata->nr_banks; i++) {
1424
-
struct samsung_pin_bank *bank = &drvdata->pin_banks[i];
1421
+
bank = &drvdata->pin_banks[i];
1425
1422
void __iomem *reg = bank->pctl_base + bank->pctl_offset;
1426
1423
const u8 *offs = bank->type->reg_offset;
1427
1424
const u8 *widths = bank->type->fld_width;
+4
-4
drivers/pinctrl/samsung/pinctrl-samsung.h
+4
-4
drivers/pinctrl/samsung/pinctrl-samsung.h
···
285
285
int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
286
286
int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
287
287
void (*pud_value_init)(struct samsung_pinctrl_drv_data *drvdata);
288
-
void (*suspend)(struct samsung_pinctrl_drv_data *);
289
-
void (*resume)(struct samsung_pinctrl_drv_data *);
288
+
void (*suspend)(struct samsung_pin_bank *bank);
289
+
void (*resume)(struct samsung_pin_bank *bank);
290
290
};
291
291
292
292
/**
···
335
335
336
336
struct samsung_retention_ctrl *retention_ctrl;
337
337
338
-
void (*suspend)(struct samsung_pinctrl_drv_data *);
339
-
void (*resume)(struct samsung_pinctrl_drv_data *);
338
+
void (*suspend)(struct samsung_pin_bank *bank);
339
+
void (*resume)(struct samsung_pin_bank *bank);
340
340
};
341
341
342
342
/**