Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
r8152: Add helper functions for SRAM2
Add the following helper functions for SRAM2 access to simplify the code
and improve readability:
- sram2_write() - write data to SRAM2 address
- sram2_read() - read data from SRAM2 address
- sram2_write_w0w1() - read-modify-write operation
Signed-off-by: Chih Kai Hsu <hsu.chih.kai@realtek.com>
Reviewed-by: Hayes Wang <hayeswang@realtek.com>
Link: https://patch.msgid.link/20260401115542.34601-1-nic_swsd@realtek.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
authored by
Chih Kai Hsu
and committed by
Jakub Kicinski
86f5dd4e
7eaff1ef
+74
-102
+74
-102
drivers/net/usb/r8152.c
+74
-102
drivers/net/usb/r8152.c
···
213
213
#define OCP_PHY_PATCH_STAT 0xb800
214
214
#define OCP_PHY_PATCH_CMD 0xb820
215
215
#define OCP_PHY_LOCK 0xb82e
216
+
#define OCP_SRAM2_ADDR 0xb87c
217
+
#define OCP_SRAM2_DATA 0xb87e
216
218
#define OCP_ADC_IOFFSET 0xbcfc
217
219
#define OCP_ADC_CFG 0xbc06
218
220
#define OCP_SYSCLK_CFG 0xc416
···
1764
1762
static void sram_set_bits(struct r8152 *tp, u16 addr, u16 set)
1765
1763
{
1766
1764
sram_write_w0w1(tp, addr, 0, set);
1765
+
}
1766
+
1767
+
static void sram2_write(struct r8152 *tp, u16 addr, u16 data)
1768
+
{
1769
+
ocp_reg_write(tp, OCP_SRAM2_ADDR, addr);
1770
+
ocp_reg_write(tp, OCP_SRAM2_DATA, data);
1771
+
}
1772
+
1773
+
static u16 sram2_read(struct r8152 *tp, u16 addr)
1774
+
{
1775
+
ocp_reg_write(tp, OCP_SRAM2_ADDR, addr);
1776
+
return ocp_reg_read(tp, OCP_SRAM2_DATA);
1777
+
}
1778
+
1779
+
static void sram2_write_w0w1(struct r8152 *tp, u16 addr, u16 clear, u16 set)
1780
+
{
1781
+
u16 data;
1782
+
1783
+
data = sram2_read(tp, addr);
1784
+
data = (data & ~clear) | set;
1785
+
ocp_reg_write(tp, OCP_SRAM2_DATA, data);
1767
1786
}
1768
1787
1769
1788
static void r8152_mdio_clr_bit(struct r8152 *tp, u16 addr, u16 clear)
···
7218
7195
ocp_reg_write(tp, 0xad4c, 0x00a8);
7219
7196
ocp_reg_write(tp, 0xac5c, 0x01ff);
7220
7197
ocp_reg_w0w1(tp, 0xac8a, 0xf0, BIT(4) | BIT(5));
7221
-
ocp_reg_write(tp, 0xb87c, 0x8157);
7222
-
ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0500);
7223
-
ocp_reg_write(tp, 0xb87c, 0x8159);
7224
-
ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0700);
7198
+
sram2_write_w0w1(tp, 0x8157, 0xff00, 0x0500);
7199
+
sram2_write_w0w1(tp, 0x8159, 0xff00, 0x0700);
7225
7200
7226
7201
/* AAGC */
7227
-
ocp_reg_write(tp, 0xb87c, 0x80a2);
7228
-
ocp_reg_write(tp, 0xb87e, 0x0153);
7229
-
ocp_reg_write(tp, 0xb87c, 0x809c);
7230
-
ocp_reg_write(tp, 0xb87e, 0x0153);
7202
+
sram2_write(tp, 0x80a2, 0x0153);
7203
+
sram2_write(tp, 0x809c, 0x0153);
7231
7204
7232
7205
/* EEE parameter */
7233
7206
ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);
···
7421
7402
ocp_reg_write(tp, 0xacc8, 0xa0d3);
7422
7403
ocp_reg_write(tp, 0xad08, 0x0007);
7423
7404
7424
-
ocp_reg_write(tp, 0xb87c, 0x8560);
7425
-
ocp_reg_write(tp, 0xb87e, 0x19cc);
7426
-
ocp_reg_write(tp, 0xb87c, 0x8562);
7427
-
ocp_reg_write(tp, 0xb87e, 0x19cc);
7428
-
ocp_reg_write(tp, 0xb87c, 0x8564);
7429
-
ocp_reg_write(tp, 0xb87e, 0x19cc);
7430
-
ocp_reg_write(tp, 0xb87c, 0x8566);
7431
-
ocp_reg_write(tp, 0xb87e, 0x147d);
7432
-
ocp_reg_write(tp, 0xb87c, 0x8568);
7433
-
ocp_reg_write(tp, 0xb87e, 0x147d);
7434
-
ocp_reg_write(tp, 0xb87c, 0x856a);
7435
-
ocp_reg_write(tp, 0xb87e, 0x147d);
7436
-
ocp_reg_write(tp, 0xb87c, 0x8ffe);
7437
-
ocp_reg_write(tp, 0xb87e, 0x0907);
7438
-
ocp_reg_write(tp, 0xb87c, 0x80d6);
7439
-
ocp_reg_write(tp, 0xb87e, 0x2801);
7440
-
ocp_reg_write(tp, 0xb87c, 0x80f2);
7441
-
ocp_reg_write(tp, 0xb87e, 0x2801);
7442
-
ocp_reg_write(tp, 0xb87c, 0x80f4);
7443
-
ocp_reg_write(tp, 0xb87e, 0x6077);
7405
+
sram2_write(tp, 0x8560, 0x19cc);
7406
+
sram2_write(tp, 0x8562, 0x19cc);
7407
+
sram2_write(tp, 0x8564, 0x19cc);
7408
+
sram2_write(tp, 0x8566, 0x147d);
7409
+
sram2_write(tp, 0x8568, 0x147d);
7410
+
sram2_write(tp, 0x856a, 0x147d);
7411
+
sram2_write(tp, 0x8ffe, 0x0907);
7412
+
sram2_write(tp, 0x80d6, 0x2801);
7413
+
sram2_write(tp, 0x80f2, 0x2801);
7414
+
sram2_write(tp, 0x80f4, 0x6077);
7444
7415
ocp_reg_write(tp, 0xb506, 0x01e7);
7445
7416
7446
-
ocp_reg_write(tp, 0xb87c, 0x8013);
7447
-
ocp_reg_write(tp, 0xb87e, 0x0700);
7448
-
ocp_reg_write(tp, 0xb87c, 0x8fb9);
7449
-
ocp_reg_write(tp, 0xb87e, 0x2801);
7450
-
ocp_reg_write(tp, 0xb87c, 0x8fba);
7451
-
ocp_reg_write(tp, 0xb87e, 0x0100);
7452
-
ocp_reg_write(tp, 0xb87c, 0x8fbc);
7453
-
ocp_reg_write(tp, 0xb87e, 0x1900);
7454
-
ocp_reg_write(tp, 0xb87c, 0x8fbe);
7455
-
ocp_reg_write(tp, 0xb87e, 0xe100);
7456
-
ocp_reg_write(tp, 0xb87c, 0x8fc0);
7457
-
ocp_reg_write(tp, 0xb87e, 0x0800);
7458
-
ocp_reg_write(tp, 0xb87c, 0x8fc2);
7459
-
ocp_reg_write(tp, 0xb87e, 0xe500);
7460
-
ocp_reg_write(tp, 0xb87c, 0x8fc4);
7461
-
ocp_reg_write(tp, 0xb87e, 0x0f00);
7462
-
ocp_reg_write(tp, 0xb87c, 0x8fc6);
7463
-
ocp_reg_write(tp, 0xb87e, 0xf100);
7464
-
ocp_reg_write(tp, 0xb87c, 0x8fc8);
7465
-
ocp_reg_write(tp, 0xb87e, 0x0400);
7466
-
ocp_reg_write(tp, 0xb87c, 0x8fca);
7467
-
ocp_reg_write(tp, 0xb87e, 0xf300);
7468
-
ocp_reg_write(tp, 0xb87c, 0x8fcc);
7469
-
ocp_reg_write(tp, 0xb87e, 0xfd00);
7470
-
ocp_reg_write(tp, 0xb87c, 0x8fce);
7471
-
ocp_reg_write(tp, 0xb87e, 0xff00);
7472
-
ocp_reg_write(tp, 0xb87c, 0x8fd0);
7473
-
ocp_reg_write(tp, 0xb87e, 0xfb00);
7474
-
ocp_reg_write(tp, 0xb87c, 0x8fd2);
7475
-
ocp_reg_write(tp, 0xb87e, 0x0100);
7476
-
ocp_reg_write(tp, 0xb87c, 0x8fd4);
7477
-
ocp_reg_write(tp, 0xb87e, 0xf400);
7478
-
ocp_reg_write(tp, 0xb87c, 0x8fd6);
7479
-
ocp_reg_write(tp, 0xb87e, 0xff00);
7480
-
ocp_reg_write(tp, 0xb87c, 0x8fd8);
7481
-
ocp_reg_write(tp, 0xb87e, 0xf600);
7417
+
sram2_write(tp, 0x8013, 0x0700);
7418
+
sram2_write(tp, 0x8fb9, 0x2801);
7419
+
sram2_write(tp, 0x8fba, 0x0100);
7420
+
sram2_write(tp, 0x8fbc, 0x1900);
7421
+
sram2_write(tp, 0x8fbe, 0xe100);
7422
+
sram2_write(tp, 0x8fc0, 0x0800);
7423
+
sram2_write(tp, 0x8fc2, 0xe500);
7424
+
sram2_write(tp, 0x8fc4, 0x0f00);
7425
+
sram2_write(tp, 0x8fc6, 0xf100);
7426
+
sram2_write(tp, 0x8fc8, 0x0400);
7427
+
sram2_write(tp, 0x8fca, 0xf300);
7428
+
sram2_write(tp, 0x8fcc, 0xfd00);
7429
+
sram2_write(tp, 0x8fce, 0xff00);
7430
+
sram2_write(tp, 0x8fd0, 0xfb00);
7431
+
sram2_write(tp, 0x8fd2, 0x0100);
7432
+
sram2_write(tp, 0x8fd4, 0xf400);
7433
+
sram2_write(tp, 0x8fd6, 0xff00);
7434
+
sram2_write(tp, 0x8fd8, 0xf600);
7482
7435
7483
7436
ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_USB_CFG,
7484
7437
EN_XG_LIP | EN_G_LIP);
7485
7438
7486
-
ocp_reg_write(tp, 0xb87c, 0x813d);
7487
-
ocp_reg_write(tp, 0xb87e, 0x390e);
7488
-
ocp_reg_write(tp, 0xb87c, 0x814f);
7489
-
ocp_reg_write(tp, 0xb87e, 0x790e);
7490
-
ocp_reg_write(tp, 0xb87c, 0x80b0);
7491
-
ocp_reg_write(tp, 0xb87e, 0x0f31);
7439
+
sram2_write(tp, 0x813d, 0x390e);
7440
+
sram2_write(tp, 0x814f, 0x790e);
7441
+
sram2_write(tp, 0x80b0, 0x0f31);
7492
7442
ocp_reg_set_bits(tp, 0xbf4c, BIT(1));
7493
7443
ocp_reg_set_bits(tp, 0xbcca, BIT(9) | BIT(8));
7494
-
ocp_reg_write(tp, 0xb87c, 0x8141);
7495
-
ocp_reg_write(tp, 0xb87e, 0x320e);
7496
-
ocp_reg_write(tp, 0xb87c, 0x8153);
7497
-
ocp_reg_write(tp, 0xb87e, 0x720e);
7498
-
ocp_reg_write(tp, 0xb87c, 0x8529);
7499
-
ocp_reg_write(tp, 0xb87e, 0x050e);
7444
+
sram2_write(tp, 0x8141, 0x320e);
7445
+
sram2_write(tp, 0x8153, 0x720e);
7446
+
sram2_write(tp, 0x8529, 0x050e);
7500
7447
ocp_reg_clr_bits(tp, OCP_EEE_CFG, CTAP_SHORT_EN);
7501
7448
7502
7449
sram_write(tp, 0x816c, 0xc4a0);
···
7474
7489
sram_write(tp, 0x8ff1, 0x0404);
7475
7490
7476
7491
ocp_reg_write(tp, 0xbf4a, 0x001b);
7477
-
ocp_reg_write(tp, 0xb87c, 0x8033);
7478
-
ocp_reg_write(tp, 0xb87e, 0x7c13);
7479
-
ocp_reg_write(tp, 0xb87c, 0x8037);
7480
-
ocp_reg_write(tp, 0xb87e, 0x7c13);
7481
-
ocp_reg_write(tp, 0xb87c, 0x803b);
7482
-
ocp_reg_write(tp, 0xb87e, 0xfc32);
7483
-
ocp_reg_write(tp, 0xb87c, 0x803f);
7484
-
ocp_reg_write(tp, 0xb87e, 0x7c13);
7485
-
ocp_reg_write(tp, 0xb87c, 0x8043);
7486
-
ocp_reg_write(tp, 0xb87e, 0x7c13);
7487
-
ocp_reg_write(tp, 0xb87c, 0x8047);
7488
-
ocp_reg_write(tp, 0xb87e, 0x7c13);
7492
+
sram2_write(tp, 0x8033, 0x7c13);
7493
+
sram2_write(tp, 0x8037, 0x7c13);
7494
+
sram2_write(tp, 0x803b, 0xfc32);
7495
+
sram2_write(tp, 0x803f, 0x7c13);
7496
+
sram2_write(tp, 0x8043, 0x7c13);
7497
+
sram2_write(tp, 0x8047, 0x7c13);
7489
7498
7490
-
ocp_reg_write(tp, 0xb87c, 0x8145);
7491
-
ocp_reg_write(tp, 0xb87e, 0x370e);
7492
-
ocp_reg_write(tp, 0xb87c, 0x8157);
7493
-
ocp_reg_write(tp, 0xb87e, 0x770e);
7494
-
ocp_reg_write(tp, 0xb87c, 0x8169);
7495
-
ocp_reg_write(tp, 0xb87e, 0x0d0a);
7496
-
ocp_reg_write(tp, 0xb87c, 0x817b);
7497
-
ocp_reg_write(tp, 0xb87e, 0x1d0a);
7499
+
sram2_write(tp, 0x8145, 0x370e);
7500
+
sram2_write(tp, 0x8157, 0x770e);
7501
+
sram2_write(tp, 0x8169, 0x0d0a);
7502
+
sram2_write(tp, 0x817b, 0x1d0a);
7498
7503
7499
7504
sram_write_w0w1(tp, 0x8217, 0xff00, 0x5000);
7500
7505
sram_write_w0w1(tp, 0x821a, 0xff00, 0x5000);
···
7549
7574
fallthrough;
7550
7575
case RTL_VER_15:
7551
7576
/* EEE parameter */
7552
-
ocp_reg_write(tp, 0xb87c, 0x80f5);
7553
-
ocp_reg_write(tp, 0xb87e, 0x760e);
7554
-
ocp_reg_write(tp, 0xb87c, 0x8107);
7555
-
ocp_reg_write(tp, 0xb87e, 0x360e);
7556
-
ocp_reg_write(tp, 0xb87c, 0x8551);
7557
-
ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0800);
7577
+
sram2_write(tp, 0x80f5, 0x760e);
7578
+
sram2_write(tp, 0x8107, 0x360e);
7579
+
sram2_write_w0w1(tp, 0x8551, 0xff00, 0x0800);
7558
7580
7559
7581
/* ADC_PGA parameter */
7560
7582
ocp_reg_w0w1(tp, 0xbf00, 0xe000, 0xa000);