tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/msm: drop A6xx GMU header

Now as the headers are generated during the build step, drop
pre-generated copies of the Adreno A6xx GMU header.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/585870/
Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-16-4bdb277a85a1@linaro.org

Dmitry Baryshkov 8723a9e6 502a9eee

-422
-422
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
··· 1 - #ifndef A6XX_GMU_XML 2 - #define A6XX_GMU_XML 3 - 4 - /* Autogenerated file, DO NOT EDIT manually! 5 - 6 - This file was generated by the rules-ng-ng gen_header.py tool in this git repository: 7 - http://gitlab.freedesktop.org/mesa/mesa/ 8 - git clone https://gitlab.freedesktop.org/mesa/mesa.git 9 - 10 - The rules-ng-ng source files this header was generated from are: 11 - 12 - - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11820 bytes, from Fri Jun 2 14:59:26 2023) 13 - - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023) 14 - - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023) 15 - 16 - Copyright (C) 2013-2024 by the following authors: 17 - - Rob Clark <robdclark@gmail.com> Rob Clark 18 - - Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin 19 - 20 - Permission is hereby granted, free of charge, to any person obtaining 21 - a copy of this software and associated documentation files (the 22 - "Software"), to deal in the Software without restriction, including 23 - without limitation the rights to use, copy, modify, merge, publish, 24 - distribute, sublicense, and/or sell copies of the Software, and to 25 - permit persons to whom the Software is furnished to do so, subject to 26 - the following conditions: 27 - 28 - The above copyright notice and this permission notice (including the 29 - next paragraph) shall be included in all copies or substantial 30 - portions of the Software. 31 - 32 - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 33 - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 34 - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 35 - IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 36 - LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 37 - OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 38 - WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 39 - 40 - */ 41 - 42 - #ifdef __KERNEL__ 43 - #include <linux/bug.h> 44 - #define assert(x) BUG_ON(!(x)) 45 - #else 46 - #include <assert.h> 47 - #endif 48 - 49 - #ifdef __cplusplus 50 - #define __struct_cast(X) 51 - #else 52 - #define __struct_cast(X) (struct X) 53 - #endif 54 - 55 - #define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB 0x00800000 56 - #define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB 0x40000000 57 - 58 - #define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK 0x00400000 59 - #define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK 0x40000000 60 - #define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK 0x40000000 61 - #define A6XX_GMU_OOB_DCVS_SET_MASK 0x00800000 62 - #define A6XX_GMU_OOB_DCVS_CHECK_MASK 0x80000000 63 - #define A6XX_GMU_OOB_DCVS_CLEAR_MASK 0x80000000 64 - #define A6XX_GMU_OOB_GPU_SET_MASK 0x00040000 65 - #define A6XX_GMU_OOB_GPU_CHECK_MASK 0x04000000 66 - #define A6XX_GMU_OOB_GPU_CLEAR_MASK 0x04000000 67 - #define A6XX_GMU_OOB_PERFCNTR_SET_MASK 0x00020000 68 - #define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK 0x02000000 69 - #define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK 0x02000000 70 - 71 - #define A6XX_HFI_IRQ_MSGQ_MASK 0x00000001 72 - #define A6XX_HFI_IRQ_DSGQ_MASK 0x00000002 73 - #define A6XX_HFI_IRQ_BLOCKED_MSG_MASK 0x00000004 74 - #define A6XX_HFI_IRQ_CM3_FAULT_MASK 0x00800000 75 - #define A6XX_HFI_IRQ_GMU_ERR_MASK__MASK 0x007f0000 76 - #define A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT 16 77 - static inline uint32_t A6XX_HFI_IRQ_GMU_ERR_MASK(uint32_t val) 78 - { 79 - return ((val) << A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT) & A6XX_HFI_IRQ_GMU_ERR_MASK__MASK; 80 - } 81 - #define A6XX_HFI_IRQ_OOB_MASK__MASK 0xff000000 82 - #define A6XX_HFI_IRQ_OOB_MASK__SHIFT 24 83 - static inline uint32_t A6XX_HFI_IRQ_OOB_MASK(uint32_t val) 84 - { 85 - return ((val) << A6XX_HFI_IRQ_OOB_MASK__SHIFT) & A6XX_HFI_IRQ_OOB_MASK__MASK; 86 - } 87 - 88 - #define A6XX_HFI_H2F_IRQ_MASK_BIT 0x00000001 89 - 90 - #define REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL 0x00000080 91 - 92 - #define REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL 0x00000081 93 - 94 - #define REG_A6XX_GMU_CM3_ITCM_START 0x00000c00 95 - 96 - #define REG_A6XX_GMU_CM3_DTCM_START 0x00001c00 97 - 98 - #define REG_A6XX_GMU_NMI_CONTROL_STATUS 0x000023f0 99 - 100 - #define REG_A6XX_GMU_BOOT_SLUMBER_OPTION 0x000023f8 101 - 102 - #define REG_A6XX_GMU_GX_VOTE_IDX 0x000023f9 103 - 104 - #define REG_A6XX_GMU_MX_VOTE_IDX 0x000023fa 105 - 106 - #define REG_A6XX_GMU_DCVS_ACK_OPTION 0x000023fc 107 - 108 - #define REG_A6XX_GMU_DCVS_PERF_SETTING 0x000023fd 109 - 110 - #define REG_A6XX_GMU_DCVS_BW_SETTING 0x000023fe 111 - 112 - #define REG_A6XX_GMU_DCVS_RETURN 0x000023ff 113 - 114 - #define REG_A6XX_GMU_ICACHE_CONFIG 0x00004c00 115 - 116 - #define REG_A6XX_GMU_DCACHE_CONFIG 0x00004c01 117 - 118 - #define REG_A6XX_GMU_SYS_BUS_CONFIG 0x00004c0f 119 - 120 - #define REG_A6XX_GMU_CM3_SYSRESET 0x00005000 121 - 122 - #define REG_A6XX_GMU_CM3_BOOT_CONFIG 0x00005001 123 - 124 - #define REG_A6XX_GMU_CM3_FW_BUSY 0x0000501a 125 - 126 - #define REG_A6XX_GMU_CM3_FW_INIT_RESULT 0x0000501c 127 - 128 - #define REG_A6XX_GMU_CM3_CFG 0x0000502d 129 - 130 - #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE 0x00005040 131 - 132 - #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0 0x00005041 133 - 134 - #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1 0x00005042 135 - 136 - #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L 0x00005044 137 - 138 - #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H 0x00005045 139 - 140 - #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L 0x00005046 141 - 142 - #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H 0x00005047 143 - 144 - #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L 0x00005048 145 - 146 - #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H 0x00005049 147 - 148 - #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L 0x0000504a 149 - 150 - #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H 0x0000504b 151 - 152 - #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L 0x0000504c 153 - 154 - #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H 0x0000504d 155 - 156 - #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L 0x0000504e 157 - 158 - #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H 0x0000504f 159 - 160 - #define REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL 0x000050c0 161 - #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE 0x00000001 162 - #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE 0x00000002 163 - #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE 0x00000004 164 - #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK 0x00003c00 165 - #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT 10 166 - static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS(uint32_t val) 167 - { 168 - return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK; 169 - } 170 - #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK 0xffffc000 171 - #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT 14 172 - static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH(uint32_t val) 173 - { 174 - return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK; 175 - } 176 - 177 - #define REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST 0x000050c1 178 - 179 - #define REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST 0x000050c2 180 - 181 - #define REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS 0x000050d0 182 - #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_OFF 0x00000001 183 - #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_ON 0x00000002 184 - #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF 0x00000004 185 - #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON 0x00000008 186 - #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF 0x00000010 187 - #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GMU_UP_POWER_STATE 0x00000020 188 - #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF 0x00000040 189 - #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF 0x00000080 190 - 191 - #define REG_A6XX_GMU_GPU_NAP_CTRL 0x000050e4 192 - #define A6XX_GMU_GPU_NAP_CTRL_HW_NAP_ENABLE 0x00000001 193 - #define A6XX_GMU_GPU_NAP_CTRL_SID__MASK 0x000001f0 194 - #define A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT 4 195 - static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) 196 - { 197 - return ((val) << A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT) & A6XX_GMU_GPU_NAP_CTRL_SID__MASK; 198 - } 199 - 200 - #define REG_A6XX_GMU_RPMH_CTRL 0x000050e8 201 - #define A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE 0x00000001 202 - #define A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE 0x00000010 203 - #define A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE 0x00000100 204 - #define A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE 0x00000200 205 - #define A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE 0x00000400 206 - #define A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE 0x00000800 207 - #define A6XX_GMU_RPMH_CTRL_DDR_MIN_VOTE_ENABLE 0x00001000 208 - #define A6XX_GMU_RPMH_CTRL_MX_MIN_VOTE_ENABLE 0x00002000 209 - #define A6XX_GMU_RPMH_CTRL_CX_MIN_VOTE_ENABLE 0x00004000 210 - #define A6XX_GMU_RPMH_CTRL_GFX_MIN_VOTE_ENABLE 0x00008000 211 - 212 - #define REG_A6XX_GMU_RPMH_HYST_CTRL 0x000050e9 213 - 214 - #define REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE 0x000050ec 215 - 216 - #define REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF 0x000050f0 217 - 218 - #define REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF 0x000050f1 219 - 220 - #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG 0x00005100 221 - 222 - #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP 0x00005101 223 - 224 - #define REG_A6XX_GMU_BOOT_KMD_LM_HANDSHAKE 0x000051f0 225 - 226 - #define REG_A6XX_GMU_LLM_GLM_SLEEP_CTRL 0x00005157 227 - 228 - #define REG_A6XX_GMU_LLM_GLM_SLEEP_STATUS 0x00005158 229 - 230 - #define REG_A6XX_GMU_ALWAYS_ON_COUNTER_L 0x00005088 231 - 232 - #define REG_A6XX_GMU_ALWAYS_ON_COUNTER_H 0x00005089 233 - 234 - #define REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE 0x000050c3 235 - 236 - #define REG_A6XX_GMU_HFI_CTRL_STATUS 0x00005180 237 - 238 - #define REG_A6XX_GMU_HFI_VERSION_INFO 0x00005181 239 - 240 - #define REG_A6XX_GMU_HFI_SFR_ADDR 0x00005182 241 - 242 - #define REG_A6XX_GMU_HFI_MMAP_ADDR 0x00005183 243 - 244 - #define REG_A6XX_GMU_HFI_QTBL_INFO 0x00005184 245 - 246 - #define REG_A6XX_GMU_HFI_QTBL_ADDR 0x00005185 247 - 248 - #define REG_A6XX_GMU_HFI_CTRL_INIT 0x00005186 249 - 250 - #define REG_A6XX_GMU_GMU2HOST_INTR_SET 0x00005190 251 - 252 - #define REG_A6XX_GMU_GMU2HOST_INTR_CLR 0x00005191 253 - 254 - #define REG_A6XX_GMU_GMU2HOST_INTR_INFO 0x00005192 255 - #define A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ 0x00000001 256 - #define A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT 0x00800000 257 - 258 - #define REG_A6XX_GMU_GMU2HOST_INTR_MASK 0x00005193 259 - 260 - #define REG_A6XX_GMU_HOST2GMU_INTR_SET 0x00005194 261 - 262 - #define REG_A6XX_GMU_HOST2GMU_INTR_CLR 0x00005195 263 - 264 - #define REG_A6XX_GMU_HOST2GMU_INTR_RAW_INFO 0x00005196 265 - 266 - #define REG_A6XX_GMU_HOST2GMU_INTR_EN_0 0x00005197 267 - 268 - #define REG_A6XX_GMU_HOST2GMU_INTR_EN_1 0x00005198 269 - 270 - #define REG_A6XX_GMU_HOST2GMU_INTR_EN_2 0x00005199 271 - 272 - #define REG_A6XX_GMU_HOST2GMU_INTR_EN_3 0x0000519a 273 - 274 - #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_0 0x0000519b 275 - 276 - #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_1 0x0000519c 277 - 278 - #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_2 0x0000519d 279 - 280 - #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_3 0x0000519e 281 - 282 - #define REG_A6XX_GMU_GENERAL_0 0x000051c5 283 - 284 - #define REG_A6XX_GMU_GENERAL_1 0x000051c6 285 - 286 - #define REG_A6XX_GMU_GENERAL_6 0x000051cb 287 - 288 - #define REG_A6XX_GMU_GENERAL_7 0x000051cc 289 - 290 - #define REG_A7XX_GMU_GENERAL_8 0x000051cd 291 - 292 - #define REG_A7XX_GMU_GENERAL_9 0x000051ce 293 - 294 - #define REG_A7XX_GMU_GENERAL_10 0x000051cf 295 - 296 - #define REG_A6XX_GMU_ISENSE_CTRL 0x0000515d 297 - 298 - #define REG_A6XX_GPU_CS_ENABLE_REG 0x00008920 299 - 300 - #define REG_A6XX_GPU_GMU_CX_GMU_ISENSE_CTRL 0x0000515d 301 - 302 - #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL3 0x00008578 303 - 304 - #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL2 0x00008558 305 - 306 - #define REG_A6XX_GPU_CS_A_SENSOR_CTRL_0 0x00008580 307 - 308 - #define REG_A6XX_GPU_CS_A_SENSOR_CTRL_2 0x00027ada 309 - 310 - #define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a 311 - 312 - #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x00008957 313 - 314 - #define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a 315 - 316 - #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000881d 317 - 318 - #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000881f 319 - 320 - #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x00008821 321 - 322 - #define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965 323 - 324 - #define REG_A6XX_GPU_CS_AMP_PERIOD_CTRL 0x0000896d 325 - 326 - #define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965 327 - 328 - #define REG_A6XX_GPU_GMU_CX_GMU_PWR_THRESHOLD 0x0000514d 329 - 330 - #define REG_A6XX_GMU_AO_INTERRUPT_EN 0x00009303 331 - 332 - #define REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR 0x00009304 333 - 334 - #define REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS 0x00009305 335 - #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE 0x00000001 336 - #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_RSCC_COMP 0x00000002 337 - #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_VDROOP 0x00000004 338 - #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR 0x00000008 339 - #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_DBD_WAKEUP 0x00000010 340 - #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR 0x00000020 341 - 342 - #define REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK 0x00009306 343 - 344 - #define REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL 0x00009309 345 - 346 - #define REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL 0x0000930a 347 - 348 - #define REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL 0x0000930b 349 - 350 - #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS 0x0000930c 351 - #define A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB 0x00800000 352 - 353 - #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2 0x0000930d 354 - 355 - #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK 0x0000930e 356 - 357 - #define REG_A6XX_GMU_AO_AHB_FENCE_CTRL 0x00009310 358 - 359 - #define REG_A6XX_GMU_AHB_FENCE_STATUS 0x00009313 360 - 361 - #define REG_A6XX_GMU_AHB_FENCE_STATUS_CLR 0x00009314 362 - 363 - #define REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS 0x00009315 364 - 365 - #define REG_A6XX_GMU_AO_SPARE_CNTL 0x00009316 366 - 367 - #define REG_A6XX_GMU_RSCC_CONTROL_REQ 0x00009307 368 - 369 - #define REG_A6XX_GMU_RSCC_CONTROL_ACK 0x00009308 370 - 371 - #define REG_A6XX_GMU_AHB_FENCE_RANGE_0 0x00009311 372 - 373 - #define REG_A6XX_GMU_AHB_FENCE_RANGE_1 0x00009312 374 - 375 - #define REG_A6XX_GPU_CC_GX_GDSCR 0x00009c03 376 - 377 - #define REG_A6XX_GPU_CC_GX_DOMAIN_MISC 0x00009d42 378 - 379 - #define REG_A6XX_GPU_CPR_FSM_CTL 0x0000c001 380 - 381 - #define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00000004 382 - 383 - #define REG_A6XX_RSCC_PDC_SEQ_START_ADDR 0x00000008 384 - 385 - #define REG_A6XX_RSCC_PDC_MATCH_VALUE_LO 0x00000009 386 - 387 - #define REG_A6XX_RSCC_PDC_MATCH_VALUE_HI 0x0000000a 388 - 389 - #define REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0 0x0000000b 390 - 391 - #define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR 0x0000000d 392 - 393 - #define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA 0x0000000e 394 - 395 - #define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0 0x00000082 396 - 397 - #define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0 0x00000083 398 - 399 - #define REG_A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0 0x00000089 400 - 401 - #define REG_A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0 0x0000008c 402 - 403 - #define REG_A6XX_RSCC_OVERRIDE_START_ADDR 0x00000100 404 - 405 - #define REG_A6XX_RSCC_SEQ_BUSY_DRV0 0x00000101 406 - 407 - #define REG_A7XX_RSCC_SEQ_MEM_0_DRV0_A740 0x00000154 408 - 409 - #define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x00000180 410 - 411 - #define REG_A6XX_RSCC_TCS0_DRV0_STATUS 0x00000346 412 - 413 - #define REG_A6XX_RSCC_TCS1_DRV0_STATUS 0x000003ee 414 - 415 - #define REG_A6XX_RSCC_TCS2_DRV0_STATUS 0x00000496 416 - 417 - #define REG_A6XX_RSCC_TCS3_DRV0_STATUS 0x0000053e 418 - 419 - #ifdef __cplusplus 420 - #endif 421 - 422 - #endif /* A6XX_GMU_XML */