Merge branch 'for-usb-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sarah/xhci

+39

drivers/usb/host/ehci-pci.c

··· 348 348 return rc; 349 349 } 350 350 351 + static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev) 352 + { 353 + return pdev->class == PCI_CLASS_SERIAL_USB_EHCI && 354 + pdev->vendor == PCI_VENDOR_ID_INTEL && 355 + pdev->device == 0x1E26; 356 + } 357 + 358 + static void ehci_enable_xhci_companion(void) 359 + { 360 + struct pci_dev *companion = NULL; 361 + 362 + /* The xHCI and EHCI controllers are not on the same PCI slot */ 363 + for_each_pci_dev(companion) { 364 + if (!usb_is_intel_switchable_xhci(companion)) 365 + continue; 366 + usb_enable_xhci_ports(companion); 367 + return; 368 + } 369 + } 370 + 351 371 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated) 352 372 { 353 373 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 354 374 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 375 + 376 + /* The BIOS on systems with the Intel Panther Point chipset may or may 377 + * not support xHCI natively. That means that during system resume, it 378 + * may switch the ports back to EHCI so that users can use their 379 + * keyboard to select a kernel from GRUB after resume from hibernate. 380 + * 381 + * The BIOS is supposed to remember whether the OS had xHCI ports 382 + * enabled before resume, and switch the ports back to xHCI when the 383 + * BIOS/OS semaphore is written, but we all know we can't trust BIOS 384 + * writers. 385 + * 386 + * Unconditionally switch the ports back to xHCI after a system resume. 387 + * We can't tell whether the EHCI or xHCI controller will be resumed 388 + * first, so we have to do the port switchover in both drivers. Writing 389 + * a '1' to the port switchover registers should have no effect if the 390 + * port was already switched over. 391 + */ 392 + if (usb_is_intel_switchable_ehci(pdev)) 393 + ehci_enable_xhci_companion(); 355 394 356 395 // maybe restore FLADJ 357 396

+63

drivers/usb/host/pci-quirks.c

··· 69 69 #define NB_PIF0_PWRDOWN_0 0x01100012 70 70 #define NB_PIF0_PWRDOWN_1 0x01100013 71 71 72 + #define USB_INTEL_XUSB2PR 0xD0 73 + #define USB_INTEL_USB3_PSSEN 0xD8 74 + 72 75 static struct amd_chipset_info { 73 76 struct pci_dev *nb_dev; 74 77 struct pci_dev *smbus_dev; ··· 676 673 return -ETIMEDOUT; 677 674 } 678 675 676 + bool usb_is_intel_switchable_xhci(struct pci_dev *pdev) 677 + { 678 + return pdev->class == PCI_CLASS_SERIAL_USB_XHCI && 679 + pdev->vendor == PCI_VENDOR_ID_INTEL && 680 + pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI; 681 + } 682 + EXPORT_SYMBOL_GPL(usb_is_intel_switchable_xhci); 683 + 684 + /* 685 + * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that 686 + * share some number of ports. These ports can be switched between either 687 + * controller. Not all of the ports under the EHCI host controller may be 688 + * switchable. 689 + * 690 + * The ports should be switched over to xHCI before PCI probes for any device 691 + * start. This avoids active devices under EHCI being disconnected during the 692 + * port switchover, which could cause loss of data on USB storage devices, or 693 + * failed boot when the root file system is on a USB mass storage device and is 694 + * enumerated under EHCI first. 695 + * 696 + * We write into the xHC's PCI configuration space in some Intel-specific 697 + * registers to switch the ports over. The USB 3.0 terminations and the USB 698 + * 2.0 data wires are switched separately. We want to enable the SuperSpeed 699 + * terminations before switching the USB 2.0 wires over, so that USB 3.0 700 + * devices connect at SuperSpeed, rather than at USB 2.0 speeds. 701 + */ 702 + void usb_enable_xhci_ports(struct pci_dev *xhci_pdev) 703 + { 704 + u32 ports_available; 705 + 706 + ports_available = 0xffffffff; 707 + /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable 708 + * Register, to turn on SuperSpeed terminations for all 709 + * available ports. 710 + */ 711 + pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 712 + cpu_to_le32(ports_available)); 713 + 714 + pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 715 + &ports_available); 716 + dev_dbg(&xhci_pdev->dev, "USB 3.0 ports that are now enabled " 717 + "under xHCI: 0x%x\n", ports_available); 718 + 719 + ports_available = 0xffffffff; 720 + /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to 721 + * switch the USB 2.0 power and data lines over to the xHCI 722 + * host. 723 + */ 724 + pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 725 + cpu_to_le32(ports_available)); 726 + 727 + pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 728 + &ports_available); 729 + dev_dbg(&xhci_pdev->dev, "USB 2.0 ports that are now switched over " 730 + "to xHCI: 0x%x\n", ports_available); 731 + } 732 + EXPORT_SYMBOL_GPL(usb_enable_xhci_ports); 733 + 679 734 /** 680 735 * PCI Quirks for xHCI. 681 736 * ··· 793 732 writel(XHCI_LEGACY_DISABLE_SMI, 794 733 base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); 795 734 735 + if (usb_is_intel_switchable_xhci(pdev)) 736 + usb_enable_xhci_ports(pdev); 796 737 hc_init: 797 738 op_reg_base = base + XHCI_HC_LENGTH(readl(base)); 798 739

+2

drivers/usb/host/pci-quirks.h

··· 8 8 void usb_amd_dev_put(void); 9 9 void usb_amd_quirk_pll_disable(void); 10 10 void usb_amd_quirk_pll_enable(void); 11 + bool usb_is_intel_switchable_xhci(struct pci_dev *pdev); 12 + void usb_enable_xhci_ports(struct pci_dev *xhci_pdev); 11 13 #else 12 14 static inline void usb_amd_quirk_pll_disable(void) {} 13 15 static inline void usb_amd_quirk_pll_enable(void) {}

+26

drivers/usb/host/xhci-pci.c

··· 118 118 /* AMD PLL quirk */ 119 119 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) 120 120 xhci->quirks |= XHCI_AMD_PLL_FIX; 121 + if (pdev->vendor == PCI_VENDOR_ID_INTEL && 122 + pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { 123 + xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 124 + xhci->quirks |= XHCI_EP_LIMIT_QUIRK; 125 + xhci->limit_active_eps = 64; 126 + } 121 127 122 128 /* Make sure the HC is halted. */ 123 129 retval = xhci_halt(xhci); ··· 248 242 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) 249 243 { 250 244 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 245 + struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 251 246 int retval = 0; 247 + 248 + /* The BIOS on systems with the Intel Panther Point chipset may or may 249 + * not support xHCI natively. That means that during system resume, it 250 + * may switch the ports back to EHCI so that users can use their 251 + * keyboard to select a kernel from GRUB after resume from hibernate. 252 + * 253 + * The BIOS is supposed to remember whether the OS had xHCI ports 254 + * enabled before resume, and switch the ports back to xHCI when the 255 + * BIOS/OS semaphore is written, but we all know we can't trust BIOS 256 + * writers. 257 + * 258 + * Unconditionally switch the ports back to xHCI after a system resume. 259 + * We can't tell whether the EHCI or xHCI controller will be resumed 260 + * first, so we have to do the port switchover in both drivers. Writing 261 + * a '1' to the port switchover registers should have no effect if the 262 + * port was already switched over. 263 + */ 264 + if (usb_is_intel_switchable_xhci(pdev)) 265 + usb_enable_xhci_ports(pdev); 252 266 253 267 retval = xhci_resume(xhci, hibernated); 254 268 return retval;

+37 -52

drivers/usb/host/xhci-ring.c

··· 167 167 next = ring->dequeue; 168 168 } 169 169 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue); 170 - if (ring == xhci->event_ring) 171 - xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr); 172 - else if (ring == xhci->cmd_ring) 173 - xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr); 174 - else 175 - xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr); 176 170 } 177 171 178 172 /* ··· 242 248 next = ring->enqueue; 243 249 } 244 250 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue); 245 - if (ring == xhci->event_ring) 246 - xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr); 247 - else if (ring == xhci->cmd_ring) 248 - xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr); 249 - else 250 - xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr); 251 251 } 252 252 253 253 /* ··· 624 636 } 625 637 } 626 638 usb_hcd_unlink_urb_from_ep(hcd, urb); 627 - xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, urb); 628 639 629 640 spin_unlock(&xhci->lock); 630 641 usb_hcd_giveback_urb(hcd, urb, status); 631 642 xhci_urb_free_priv(xhci, urb_priv); 632 643 spin_lock(&xhci->lock); 633 - xhci_dbg(xhci, "%s URB given back\n", adjective); 634 644 } 635 645 } 636 646 ··· 678 692 679 693 if (list_empty(&ep->cancelled_td_list)) { 680 694 xhci_stop_watchdog_timer_in_irq(xhci, ep); 695 + ep->stopped_td = NULL; 696 + ep->stopped_trb = NULL; 681 697 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 682 698 return; 683 699 } ··· 1081 1093 complete(&xhci->addr_dev); 1082 1094 break; 1083 1095 case TRB_TYPE(TRB_DISABLE_SLOT): 1084 - if (xhci->devs[slot_id]) 1096 + if (xhci->devs[slot_id]) { 1097 + if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) 1098 + /* Delete default control endpoint resources */ 1099 + xhci_free_device_endpoint_resources(xhci, 1100 + xhci->devs[slot_id], true); 1085 1101 xhci_free_virt_device(xhci, slot_id); 1102 + } 1086 1103 break; 1087 1104 case TRB_TYPE(TRB_CONFIG_EP): 1088 1105 virt_dev = xhci->devs[slot_id]; ··· 1623 1630 "without IOC set??\n"); 1624 1631 *status = -ESHUTDOWN; 1625 1632 } else { 1626 - xhci_dbg(xhci, "Successful control transfer!\n"); 1627 1633 *status = 0; 1628 1634 } 1629 1635 break; ··· 1719 1727 switch (trb_comp_code) { 1720 1728 case COMP_SUCCESS: 1721 1729 frame->status = 0; 1722 - xhci_dbg(xhci, "Successful isoc transfer!\n"); 1723 1730 break; 1724 1731 case COMP_SHORT_TX: 1725 1732 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ? ··· 1828 1837 else 1829 1838 *status = 0; 1830 1839 } else { 1831 - if (usb_endpoint_xfer_bulk(&td->urb->ep->desc)) 1832 - xhci_dbg(xhci, "Successful bulk " 1833 - "transfer!\n"); 1834 - else 1835 - xhci_dbg(xhci, "Successful interrupt " 1836 - "transfer!\n"); 1837 1840 *status = 0; 1838 1841 } 1839 1842 break; ··· 1841 1856 /* Others already handled above */ 1842 1857 break; 1843 1858 } 1844 - xhci_dbg(xhci, "ep %#x - asked for %d bytes, " 1845 - "%d bytes untransferred\n", 1846 - td->urb->ep->desc.bEndpointAddress, 1847 - td->urb->transfer_buffer_length, 1848 - TRB_LEN(le32_to_cpu(event->transfer_len))); 1859 + if (trb_comp_code == COMP_SHORT_TX) 1860 + xhci_dbg(xhci, "ep %#x - asked for %d bytes, " 1861 + "%d bytes untransferred\n", 1862 + td->urb->ep->desc.bEndpointAddress, 1863 + td->urb->transfer_buffer_length, 1864 + TRB_LEN(le32_to_cpu(event->transfer_len))); 1849 1865 /* Fast path - was this the last TRB in the TD for this URB? */ 1850 1866 if (event_trb == td->last_trb) { 1851 1867 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { ··· 1940 1954 1941 1955 /* Endpoint ID is 1 based, our index is zero based */ 1942 1956 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; 1943 - xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index); 1944 1957 ep = &xdev->eps[ep_index]; 1945 1958 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 1946 1959 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); ··· 2066 2081 if (!event_seg) { 2067 2082 if (!ep->skip || 2068 2083 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { 2084 + /* Some host controllers give a spurious 2085 + * successful event after a short transfer. 2086 + * Ignore it. 2087 + */ 2088 + if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && 2089 + ep_ring->last_td_was_short) { 2090 + ep_ring->last_td_was_short = false; 2091 + ret = 0; 2092 + goto cleanup; 2093 + } 2069 2094 /* HC is busted, give up! */ 2070 2095 xhci_err(xhci, 2071 2096 "ERROR Transfer event TRB DMA ptr not " ··· 2086 2091 ret = skip_isoc_td(xhci, td, event, ep, &status); 2087 2092 goto cleanup; 2088 2093 } 2094 + if (trb_comp_code == COMP_SHORT_TX) 2095 + ep_ring->last_td_was_short = true; 2096 + else 2097 + ep_ring->last_td_was_short = false; 2089 2098 2090 2099 if (ep->skip) { 2091 2100 xhci_dbg(xhci, "Found td. Clear skip flag.\n"); ··· 2148 2149 xhci_urb_free_priv(xhci, urb_priv); 2149 2150 2150 2151 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); 2151 - xhci_dbg(xhci, "Giveback URB %p, len = %d, " 2152 - "status = %d\n", 2153 - urb, urb->actual_length, status); 2152 + if ((urb->actual_length != urb->transfer_buffer_length && 2153 + (urb->transfer_flags & 2154 + URB_SHORT_NOT_OK)) || 2155 + status != 0) 2156 + xhci_dbg(xhci, "Giveback URB %p, len = %d, " 2157 + "expected = %x, status = %d\n", 2158 + urb, urb->actual_length, 2159 + urb->transfer_buffer_length, 2160 + status); 2154 2161 spin_unlock(&xhci->lock); 2155 2162 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status); 2156 2163 spin_lock(&xhci->lock); ··· 2185 2180 int update_ptrs = 1; 2186 2181 int ret; 2187 2182 2188 - xhci_dbg(xhci, "In %s\n", __func__); 2189 2183 if (!xhci->event_ring || !xhci->event_ring->dequeue) { 2190 2184 xhci->error_bitmask |= 1 << 1; 2191 2185 return 0; ··· 2197 2193 xhci->error_bitmask |= 1 << 2; 2198 2194 return 0; 2199 2195 } 2200 - xhci_dbg(xhci, "%s - OS owns TRB\n", __func__); 2201 2196 2202 2197 /* 2203 2198 * Barrier between reading the TRB_CYCLE (valid) flag above and any ··· 2206 2203 /* FIXME: Handle more event types. */ 2207 2204 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) { 2208 2205 case TRB_TYPE(TRB_COMPLETION): 2209 - xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__); 2210 2206 handle_cmd_completion(xhci, &event->event_cmd); 2211 - xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__); 2212 2207 break; 2213 2208 case TRB_TYPE(TRB_PORT_STATUS): 2214 - xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__); 2215 2209 handle_port_status(xhci, event); 2216 - xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__); 2217 2210 update_ptrs = 0; 2218 2211 break; 2219 2212 case TRB_TYPE(TRB_TRANSFER): 2220 - xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__); 2221 2213 ret = handle_tx_event(xhci, &event->trans_event); 2222 - xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__); 2223 2214 if (ret < 0) 2224 2215 xhci->error_bitmask |= 1 << 9; 2225 2216 else ··· 2270 2273 spin_unlock(&xhci->lock); 2271 2274 return IRQ_NONE; 2272 2275 } 2273 - xhci_dbg(xhci, "op reg status = %08x\n", status); 2274 - xhci_dbg(xhci, "Event ring dequeue ptr:\n"); 2275 - xhci_dbg(xhci, "@%llx %08x %08x %08x %08x\n", 2276 - (unsigned long long) 2277 - xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, trb), 2278 - lower_32_bits(le64_to_cpu(trb->link.segment_ptr)), 2279 - upper_32_bits(le64_to_cpu(trb->link.segment_ptr)), 2280 - (unsigned int) le32_to_cpu(trb->link.intr_target), 2281 - (unsigned int) le32_to_cpu(trb->link.control)); 2282 - 2283 2276 if (status & STS_FATAL) { 2284 2277 xhci_warn(xhci, "WARNING: Host System Error\n"); 2285 2278 xhci_halt(xhci); ··· 2384 2397 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) 2385 2398 { 2386 2399 /* Make sure the endpoint has been added to xHC schedule */ 2387 - xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state); 2388 2400 switch (ep_state) { 2389 2401 case EP_STATE_DISABLED: 2390 2402 /* ··· 2420 2434 struct xhci_ring *ring = ep_ring; 2421 2435 union xhci_trb *next; 2422 2436 2423 - xhci_dbg(xhci, "prepare_ring: pointing to link trb\n"); 2424 2437 next = ring->enqueue; 2425 2438 2426 2439 while (last_trb(xhci, ring, ring->enq_seg, next)) {

+229 -11

drivers/usb/host/xhci.c

··· 1314 1314 if (ret <= 0) 1315 1315 return ret; 1316 1316 xhci = hcd_to_xhci(hcd); 1317 - xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); 1317 + if (xhci->xhc_state & XHCI_STATE_DYING) 1318 + return -ENODEV; 1318 1319 1320 + xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); 1319 1321 drop_flag = xhci_get_endpoint_flag(&ep->desc); 1320 1322 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) { 1321 1323 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n", ··· 1403 1401 return ret; 1404 1402 } 1405 1403 xhci = hcd_to_xhci(hcd); 1404 + if (xhci->xhc_state & XHCI_STATE_DYING) 1405 + return -ENODEV; 1406 1406 1407 1407 added_ctxs = xhci_get_endpoint_flag(&ep->desc); 1408 1408 last_ctx = xhci_last_valid_endpoint(added_ctxs); ··· 1582 1578 return ret; 1583 1579 } 1584 1580 1581 + static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci, 1582 + struct xhci_container_ctx *in_ctx) 1583 + { 1584 + struct xhci_input_control_ctx *ctrl_ctx; 1585 + u32 valid_add_flags; 1586 + u32 valid_drop_flags; 1587 + 1588 + ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); 1589 + /* Ignore the slot flag (bit 0), and the default control endpoint flag 1590 + * (bit 1). The default control endpoint is added during the Address 1591 + * Device command and is never removed until the slot is disabled. 1592 + */ 1593 + valid_add_flags = ctrl_ctx->add_flags >> 2; 1594 + valid_drop_flags = ctrl_ctx->drop_flags >> 2; 1595 + 1596 + /* Use hweight32 to count the number of ones in the add flags, or 1597 + * number of endpoints added. Don't count endpoints that are changed 1598 + * (both added and dropped). 1599 + */ 1600 + return hweight32(valid_add_flags) - 1601 + hweight32(valid_add_flags & valid_drop_flags); 1602 + } 1603 + 1604 + static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci, 1605 + struct xhci_container_ctx *in_ctx) 1606 + { 1607 + struct xhci_input_control_ctx *ctrl_ctx; 1608 + u32 valid_add_flags; 1609 + u32 valid_drop_flags; 1610 + 1611 + ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); 1612 + valid_add_flags = ctrl_ctx->add_flags >> 2; 1613 + valid_drop_flags = ctrl_ctx->drop_flags >> 2; 1614 + 1615 + return hweight32(valid_drop_flags) - 1616 + hweight32(valid_add_flags & valid_drop_flags); 1617 + } 1618 + 1619 + /* 1620 + * We need to reserve the new number of endpoints before the configure endpoint 1621 + * command completes. We can't subtract the dropped endpoints from the number 1622 + * of active endpoints until the command completes because we can oversubscribe 1623 + * the host in this case: 1624 + * 1625 + * - the first configure endpoint command drops more endpoints than it adds 1626 + * - a second configure endpoint command that adds more endpoints is queued 1627 + * - the first configure endpoint command fails, so the config is unchanged 1628 + * - the second command may succeed, even though there isn't enough resources 1629 + * 1630 + * Must be called with xhci->lock held. 1631 + */ 1632 + static int xhci_reserve_host_resources(struct xhci_hcd *xhci, 1633 + struct xhci_container_ctx *in_ctx) 1634 + { 1635 + u32 added_eps; 1636 + 1637 + added_eps = xhci_count_num_new_endpoints(xhci, in_ctx); 1638 + if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) { 1639 + xhci_dbg(xhci, "Not enough ep ctxs: " 1640 + "%u active, need to add %u, limit is %u.\n", 1641 + xhci->num_active_eps, added_eps, 1642 + xhci->limit_active_eps); 1643 + return -ENOMEM; 1644 + } 1645 + xhci->num_active_eps += added_eps; 1646 + xhci_dbg(xhci, "Adding %u ep ctxs, %u now active.\n", added_eps, 1647 + xhci->num_active_eps); 1648 + return 0; 1649 + } 1650 + 1651 + /* 1652 + * The configure endpoint was failed by the xHC for some other reason, so we 1653 + * need to revert the resources that failed configuration would have used. 1654 + * 1655 + * Must be called with xhci->lock held. 1656 + */ 1657 + static void xhci_free_host_resources(struct xhci_hcd *xhci, 1658 + struct xhci_container_ctx *in_ctx) 1659 + { 1660 + u32 num_failed_eps; 1661 + 1662 + num_failed_eps = xhci_count_num_new_endpoints(xhci, in_ctx); 1663 + xhci->num_active_eps -= num_failed_eps; 1664 + xhci_dbg(xhci, "Removing %u failed ep ctxs, %u now active.\n", 1665 + num_failed_eps, 1666 + xhci->num_active_eps); 1667 + } 1668 + 1669 + /* 1670 + * Now that the command has completed, clean up the active endpoint count by 1671 + * subtracting out the endpoints that were dropped (but not changed). 1672 + * 1673 + * Must be called with xhci->lock held. 1674 + */ 1675 + static void xhci_finish_resource_reservation(struct xhci_hcd *xhci, 1676 + struct xhci_container_ctx *in_ctx) 1677 + { 1678 + u32 num_dropped_eps; 1679 + 1680 + num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, in_ctx); 1681 + xhci->num_active_eps -= num_dropped_eps; 1682 + if (num_dropped_eps) 1683 + xhci_dbg(xhci, "Removing %u dropped ep ctxs, %u now active.\n", 1684 + num_dropped_eps, 1685 + xhci->num_active_eps); 1686 + } 1687 + 1585 1688 /* Issue a configure endpoint command or evaluate context command 1586 1689 * and wait for it to finish. 1587 1690 */ ··· 1709 1598 virt_dev = xhci->devs[udev->slot_id]; 1710 1599 if (command) { 1711 1600 in_ctx = command->in_ctx; 1601 + if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) && 1602 + xhci_reserve_host_resources(xhci, in_ctx)) { 1603 + spin_unlock_irqrestore(&xhci->lock, flags); 1604 + xhci_warn(xhci, "Not enough host resources, " 1605 + "active endpoint contexts = %u\n", 1606 + xhci->num_active_eps); 1607 + return -ENOMEM; 1608 + } 1609 + 1712 1610 cmd_completion = command->completion; 1713 1611 cmd_status = &command->status; 1714 1612 command->command_trb = xhci->cmd_ring->enqueue; ··· 1733 1613 list_add_tail(&command->cmd_list, &virt_dev->cmd_list); 1734 1614 } else { 1735 1615 in_ctx = virt_dev->in_ctx; 1616 + if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) && 1617 + xhci_reserve_host_resources(xhci, in_ctx)) { 1618 + spin_unlock_irqrestore(&xhci->lock, flags); 1619 + xhci_warn(xhci, "Not enough host resources, " 1620 + "active endpoint contexts = %u\n", 1621 + xhci->num_active_eps); 1622 + return -ENOMEM; 1623 + } 1736 1624 cmd_completion = &virt_dev->cmd_completion; 1737 1625 cmd_status = &virt_dev->cmd_status; 1738 1626 } ··· 1755 1627 if (ret < 0) { 1756 1628 if (command) 1757 1629 list_del(&command->cmd_list); 1630 + if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) 1631 + xhci_free_host_resources(xhci, in_ctx); 1758 1632 spin_unlock_irqrestore(&xhci->lock, flags); 1759 1633 xhci_dbg(xhci, "FIXME allocate a new ring segment\n"); 1760 1634 return -ENOMEM; ··· 1779 1649 } 1780 1650 1781 1651 if (!ctx_change) 1782 - return xhci_configure_endpoint_result(xhci, udev, cmd_status); 1783 - return xhci_evaluate_context_result(xhci, udev, cmd_status); 1652 + ret = xhci_configure_endpoint_result(xhci, udev, cmd_status); 1653 + else 1654 + ret = xhci_evaluate_context_result(xhci, udev, cmd_status); 1655 + 1656 + if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { 1657 + spin_lock_irqsave(&xhci->lock, flags); 1658 + /* If the command failed, remove the reserved resources. 1659 + * Otherwise, clean up the estimate to include dropped eps. 1660 + */ 1661 + if (ret) 1662 + xhci_free_host_resources(xhci, in_ctx); 1663 + else 1664 + xhci_finish_resource_reservation(xhci, in_ctx); 1665 + spin_unlock_irqrestore(&xhci->lock, flags); 1666 + } 1667 + return ret; 1784 1668 } 1785 1669 1786 1670 /* Called after one or more calls to xhci_add_endpoint() or ··· 1820 1676 if (ret <= 0) 1821 1677 return ret; 1822 1678 xhci = hcd_to_xhci(hcd); 1679 + if (xhci->xhc_state & XHCI_STATE_DYING) 1680 + return -ENODEV; 1823 1681 1824 1682 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); 1825 1683 virt_dev = xhci->devs[udev->slot_id]; ··· 2412 2266 } 2413 2267 2414 2268 /* 2269 + * Deletes endpoint resources for endpoints that were active before a Reset 2270 + * Device command, or a Disable Slot command. The Reset Device command leaves 2271 + * the control endpoint intact, whereas the Disable Slot command deletes it. 2272 + * 2273 + * Must be called with xhci->lock held. 2274 + */ 2275 + void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 2276 + struct xhci_virt_device *virt_dev, bool drop_control_ep) 2277 + { 2278 + int i; 2279 + unsigned int num_dropped_eps = 0; 2280 + unsigned int drop_flags = 0; 2281 + 2282 + for (i = (drop_control_ep ? 0 : 1); i < 31; i++) { 2283 + if (virt_dev->eps[i].ring) { 2284 + drop_flags |= 1 << i; 2285 + num_dropped_eps++; 2286 + } 2287 + } 2288 + xhci->num_active_eps -= num_dropped_eps; 2289 + if (num_dropped_eps) 2290 + xhci_dbg(xhci, "Dropped %u ep ctxs, flags = 0x%x, " 2291 + "%u now active.\n", 2292 + num_dropped_eps, drop_flags, 2293 + xhci->num_active_eps); 2294 + } 2295 + 2296 + /* 2415 2297 * This submits a Reset Device Command, which will set the device state to 0, 2416 2298 * set the device address to 0, and disable all the endpoints except the default 2417 2299 * control endpoint. The USB core should come back and call ··· 2580 2406 goto command_cleanup; 2581 2407 } 2582 2408 2409 + /* Free up host controller endpoint resources */ 2410 + if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { 2411 + spin_lock_irqsave(&xhci->lock, flags); 2412 + /* Don't delete the default control endpoint resources */ 2413 + xhci_free_device_endpoint_resources(xhci, virt_dev, false); 2414 + spin_unlock_irqrestore(&xhci->lock, flags); 2415 + } 2416 + 2583 2417 /* Everything but endpoint 0 is disabled, so free or cache the rings. */ 2584 2418 last_freed_endpoint = 1; 2585 2419 for (i = 1; i < 31; ++i) { ··· 2661 2479 } 2662 2480 2663 2481 /* 2482 + * Checks if we have enough host controller resources for the default control 2483 + * endpoint. 2484 + * 2485 + * Must be called with xhci->lock held. 2486 + */ 2487 + static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci) 2488 + { 2489 + if (xhci->num_active_eps + 1 > xhci->limit_active_eps) { 2490 + xhci_dbg(xhci, "Not enough ep ctxs: " 2491 + "%u active, need to add 1, limit is %u.\n", 2492 + xhci->num_active_eps, xhci->limit_active_eps); 2493 + return -ENOMEM; 2494 + } 2495 + xhci->num_active_eps += 1; 2496 + xhci_dbg(xhci, "Adding 1 ep ctx, %u now active.\n", 2497 + xhci->num_active_eps); 2498 + return 0; 2499 + } 2500 + 2501 + 2502 + /* 2664 2503 * Returns 0 if the xHC ran out of device slots, the Enable Slot command 2665 2504 * timed out, or allocating memory failed. Returns 1 on success. 2666 2505 */ ··· 2716 2513 xhci_err(xhci, "Error while assigning device slot ID\n"); 2717 2514 return 0; 2718 2515 } 2719 - /* xhci_alloc_virt_device() does not touch rings; no need to lock. 2720 - * Use GFP_NOIO, since this function can be called from 2516 + 2517 + if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { 2518 + spin_lock_irqsave(&xhci->lock, flags); 2519 + ret = xhci_reserve_host_control_ep_resources(xhci); 2520 + if (ret) { 2521 + spin_unlock_irqrestore(&xhci->lock, flags); 2522 + xhci_warn(xhci, "Not enough host resources, " 2523 + "active endpoint contexts = %u\n", 2524 + xhci->num_active_eps); 2525 + goto disable_slot; 2526 + } 2527 + spin_unlock_irqrestore(&xhci->lock, flags); 2528 + } 2529 + /* Use GFP_NOIO, since this function can be called from 2721 2530 * xhci_discover_or_reset_device(), which may be called as part of 2722 2531 * mass storage driver error handling. 2723 2532 */ 2724 2533 if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_NOIO)) { 2725 - /* Disable slot, if we can do it without mem alloc */ 2726 2534 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n"); 2727 - spin_lock_irqsave(&xhci->lock, flags); 2728 - if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) 2729 - xhci_ring_cmd_db(xhci); 2730 - spin_unlock_irqrestore(&xhci->lock, flags); 2731 - return 0; 2535 + goto disable_slot; 2732 2536 } 2733 2537 udev->slot_id = xhci->slot_id; 2734 2538 /* Is this a LS or FS device under a HS hub? */ 2735 2539 /* Hub or peripherial? */ 2736 2540 return 1; 2541 + 2542 + disable_slot: 2543 + /* Disable slot, if we can do it without mem alloc */ 2544 + spin_lock_irqsave(&xhci->lock, flags); 2545 + if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) 2546 + xhci_ring_cmd_db(xhci); 2547 + spin_unlock_irqrestore(&xhci->lock, flags); 2548 + return 0; 2737 2549 } 2738 2550 2739 2551 /*

+16 -6

drivers/usb/host/xhci.h

··· 1123 1123 */ 1124 1124 u32 cycle_state; 1125 1125 unsigned int stream_id; 1126 + bool last_td_was_short; 1126 1127 }; 1127 1128 1128 1129 struct xhci_erst_entry { ··· 1291 1290 #define XHCI_RESET_EP_QUIRK (1 << 1) 1292 1291 #define XHCI_NEC_HOST (1 << 2) 1293 1292 #define XHCI_AMD_PLL_FIX (1 << 3) 1293 + #define XHCI_SPURIOUS_SUCCESS (1 << 4) 1294 + /* 1295 + * Certain Intel host controllers have a limit to the number of endpoint 1296 + * contexts they can handle. Ideally, they would signal that they can't handle 1297 + * anymore endpoint contexts by returning a Resource Error for the Configure 1298 + * Endpoint command, but they don't. Instead they expect software to keep track 1299 + * of the number of active endpoints for them, across configure endpoint 1300 + * commands, reset device commands, disable slot commands, and address device 1301 + * commands. 1302 + */ 1303 + #define XHCI_EP_LIMIT_QUIRK (1 << 5) 1304 + unsigned int num_active_eps; 1305 + unsigned int limit_active_eps; 1294 1306 /* There are two roothubs to keep track of bus suspend info for */ 1295 1307 struct xhci_bus_state bus_state[2]; 1296 1308 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */ ··· 1352 1338 static inline void xhci_writel(struct xhci_hcd *xhci, 1353 1339 const unsigned int val, __le32 __iomem *regs) 1354 1340 { 1355 - xhci_dbg(xhci, 1356 - "`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n", 1357 - regs, val); 1358 1341 writel(val, regs); 1359 1342 } 1360 1343 ··· 1379 1368 u32 val_lo = lower_32_bits(val); 1380 1369 u32 val_hi = upper_32_bits(val); 1381 1370 1382 - xhci_dbg(xhci, 1383 - "`MEM_WRITE_DWORD(3'b000, 64'h%p, 64'h%0lx, 4'hf);\n", 1384 - regs, (long unsigned int) val); 1385 1371 writel(val_lo, ptr); 1386 1372 writel(val_hi, ptr + 1); 1387 1373 } ··· 1447 1439 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci, 1448 1440 struct xhci_ep_ctx *ep_ctx, 1449 1441 struct xhci_virt_ep *ep); 1442 + void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1443 + struct xhci_virt_device *virt_dev, bool drop_control_ep); 1450 1444 struct xhci_ring *xhci_dma_to_transfer_ring( 1451 1445 struct xhci_virt_ep *ep, 1452 1446 u64 address);

+1

include/linux/pci_ids.h

··· 2483 2483 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f 2484 2484 #define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0 0x1d40 2485 2485 #define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1 0x1d41 2486 + #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI 0x1e31 2486 2487 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e40 2487 2488 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f 2488 2489 #define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN 0x2310

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