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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge patch series "scsi: hisi_sas: Some misc changes"
Xiang Chen <chenxiang66@hisilicon.com> says:
This series contains some fixes including:
- Configure initial value of some registers according to HBA model
- Change DMA setup lock timeout from 100ms to 2.5s
- Fix warnings detected by sparse
Link: https://lore.kernel.org/r/1684118481-95908-1-git-send-email-chenxiang66@hisilicon.com
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+20
-8
+20
-8
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+20
-8
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
···
30
30
#define SATA_INITI_D2H_STORE_ADDR_LO 0x60
31
31
#define SATA_INITI_D2H_STORE_ADDR_HI 0x64
32
32
#define CFG_MAX_TAG 0x68
33
+
#define TRANS_LOCK_ICT_TIME 0X70
33
34
#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
34
35
#define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
35
36
#define HGC_GET_ITV_TIME 0x90
···
628
627
629
628
static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
630
629
{
630
+
struct pci_dev *pdev = hisi_hba->pci_dev;
631
631
int i, j;
632
632
633
633
/* Global registers init */
634
634
hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
635
635
(u32)((1ULL << hisi_hba->queue_count) - 1));
636
-
hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0);
637
636
hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
637
+
/* time / CLK_AHB = 2.5s / 2ns = 0x4A817C80 */
638
+
hisi_sas_write32(hisi_hba, TRANS_LOCK_ICT_TIME, 0x4A817C80);
638
639
hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
639
640
hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
640
641
hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
···
655
652
hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
656
653
hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
657
654
655
+
if (pdev->revision < 0x30)
656
+
hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0);
657
+
658
658
interrupt_enable_v3_hw(hisi_hba);
659
659
for (i = 0; i < hisi_hba->n_phy; i++) {
660
660
enum sas_linkrate max;
···
675
669
prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
676
670
hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
677
671
prog_phy_link_rate);
678
-
hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00);
679
672
hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
680
673
hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
681
674
hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
···
685
680
hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
686
681
hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
687
682
hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01);
688
-
hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);
689
683
hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME,
690
684
0x30f4240);
691
-
/* used for 12G negotiate */
692
-
hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
693
685
hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);
686
+
687
+
/* set value through firmware for 920B and later version */
688
+
if (pdev->revision < 0x30) {
689
+
hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);
690
+
hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00);
691
+
/* used for 12G negotiate */
692
+
hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
693
+
}
694
694
695
695
/* get default FFE configuration for BIST */
696
696
for (j = 0; j < FFE_CFG_MAX; j++) {
···
2216
2206
u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type);
2217
2207
u16 sipc_rx_err_type = le16_to_cpu(record->sipc_rx_err_type);
2218
2208
u32 dw3 = le32_to_cpu(complete_hdr->dw3);
2209
+
u32 dw0 = le32_to_cpu(complete_hdr->dw0);
2219
2210
2220
2211
switch (task->task_proto) {
2221
2212
case SAS_PROTOCOL_SSP:
···
2226
2215
* but I/O information has been written to the host memory, we examine
2227
2216
* response IU.
2228
2217
*/
2229
-
if (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_GOOD_MSK) &&
2230
-
(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))
2218
+
if (!(dw0 & CMPLT_HDR_RSPNS_GOOD_MSK) &&
2219
+
(dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))
2231
2220
return false;
2232
2221
2233
2222
ts->residual = trans_tx_fail_type;
···
2243
2232
case SAS_PROTOCOL_SATA:
2244
2233
case SAS_PROTOCOL_STP:
2245
2234
case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2246
-
if ((complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK) &&
2235
+
if ((dw0 & CMPLT_HDR_RSPNS_XFRD_MSK) &&
2247
2236
(sipc_rx_err_type & RX_FIS_STATUS_ERR_MSK)) {
2248
2237
ts->stat = SAS_PROTO_RESPONSE;
2249
2238
} else if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
···
3010
2999
HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO),
3011
3000
HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI),
3012
3001
HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG),
3002
+
HISI_SAS_DEBUGFS_REG(TRANS_LOCK_ICT_TIME),
3013
3003
HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL),
3014
3004
HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL),
3015
3005
HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME),