Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-for-v4.12-rc3' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Not a whole lot happening here, a set of amdgpu fixes and one core
deadlock fix, and some misc drivers fixes"
* tag 'drm-fixes-for-v4.12-rc3' of git://people.freedesktop.org/~airlied/linux:
drm/amdgpu: fix null point error when rmmod amdgpu.
drm/amd/powerplay: fix a signedness bugs
drm/amdgpu: fix NULL pointer panic of emit_gds_switch
drm/radeon: Unbreak HPD handling for r600+
drm/amd/powerplay/smu7: disable mclk switching for high refresh rates
drm/amd/powerplay/smu7: add vblank check for mclk switching (v2)
drm/radeon/ci: disable mclk switching for high refresh rates (v2)
drm/amdgpu/ci: disable mclk switching for high refresh rates (v2)
drm/amdgpu: fix fundamental suspend/resume issue
drm/gma500/psb: Actually use VBT mode when it is found
drm: Fix deadlock retry loop in page_flip_ioctl
drm: qxl: Delay entering atomic context during cursor update
drm/radeon: Fix oops upon driver load on PowerXpress laptops
+102
-80
+6
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+6
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
···
425
425
426
426
void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev)
427
427
{
428
-
struct amdgpu_fbdev *afbdev = adev->mode_info.rfbdev;
428
+
struct amdgpu_fbdev *afbdev;
429
429
struct drm_fb_helper *fb_helper;
430
430
int ret;
431
+
432
+
if (!adev)
433
+
return;
434
+
435
+
afbdev = adev->mode_info.rfbdev;
431
436
432
437
if (!afbdev)
433
438
return;
+22
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+22
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
···
634
634
mutex_unlock(&id_mgr->lock);
635
635
}
636
636
637
-
if (gds_switch_needed) {
637
+
if (ring->funcs->emit_gds_switch && gds_switch_needed) {
638
638
id->gds_base = job->gds_base;
639
639
id->gds_size = job->gds_size;
640
640
id->gws_base = job->gws_base;
···
672
672
struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
673
673
struct amdgpu_vm_id *id = &id_mgr->ids[vmid];
674
674
675
+
atomic64_set(&id->owner, 0);
675
676
id->gds_base = 0;
676
677
id->gds_size = 0;
677
678
id->gws_base = 0;
678
679
id->gws_size = 0;
679
680
id->oa_base = 0;
680
681
id->oa_size = 0;
682
+
}
683
+
684
+
/**
685
+
* amdgpu_vm_reset_all_id - reset VMID to zero
686
+
*
687
+
* @adev: amdgpu device structure
688
+
*
689
+
* Reset VMID to force flush on next use
690
+
*/
691
+
void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev)
692
+
{
693
+
unsigned i, j;
694
+
695
+
for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
696
+
struct amdgpu_vm_id_manager *id_mgr =
697
+
&adev->vm_manager.id_mgr[i];
698
+
699
+
for (j = 1; j < id_mgr->num_ids; ++j)
700
+
amdgpu_vm_reset_id(adev, i, j);
701
+
}
681
702
}
682
703
683
704
/**
···
2290
2269
dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2291
2270
for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2292
2271
adev->vm_manager.seqno[i] = 0;
2293
-
2294
2272
2295
2273
atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
2296
2274
atomic64_set(&adev->vm_manager.client_counter, 0);
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
···
204
204
int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job);
205
205
void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub,
206
206
unsigned vmid);
207
+
void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev);
207
208
int amdgpu_vm_update_directories(struct amdgpu_device *adev,
208
209
struct amdgpu_vm *vm);
209
210
int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
+6
drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+6
drivers/gpu/drm/amd/amdgpu/ci_dpm.c
···
906
906
u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
907
907
u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;
908
908
909
+
/* disable mclk switching if the refresh is >120Hz, even if the
910
+
* blanking period would allow it
911
+
*/
912
+
if (amdgpu_dpm_get_vrefresh(adev) > 120)
913
+
return true;
914
+
909
915
if (vblank_time < switch_limit)
910
916
return true;
911
917
else
+2
-13
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+2
-13
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
···
950
950
{
951
951
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
952
952
953
-
if (adev->vm_manager.enabled) {
954
-
gmc_v6_0_vm_fini(adev);
955
-
adev->vm_manager.enabled = false;
956
-
}
957
953
gmc_v6_0_hw_fini(adev);
958
954
959
955
return 0;
···
964
968
if (r)
965
969
return r;
966
970
967
-
if (!adev->vm_manager.enabled) {
968
-
r = gmc_v6_0_vm_init(adev);
969
-
if (r) {
970
-
dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
971
-
return r;
972
-
}
973
-
adev->vm_manager.enabled = true;
974
-
}
971
+
amdgpu_vm_reset_all_ids(adev);
975
972
976
-
return r;
973
+
return 0;
977
974
}
978
975
979
976
static bool gmc_v6_0_is_idle(void *handle)
+2
-13
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+2
-13
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
···
1117
1117
{
1118
1118
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1119
1119
1120
-
if (adev->vm_manager.enabled) {
1121
-
gmc_v7_0_vm_fini(adev);
1122
-
adev->vm_manager.enabled = false;
1123
-
}
1124
1120
gmc_v7_0_hw_fini(adev);
1125
1121
1126
1122
return 0;
···
1131
1135
if (r)
1132
1136
return r;
1133
1137
1134
-
if (!adev->vm_manager.enabled) {
1135
-
r = gmc_v7_0_vm_init(adev);
1136
-
if (r) {
1137
-
dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1138
-
return r;
1139
-
}
1140
-
adev->vm_manager.enabled = true;
1141
-
}
1138
+
amdgpu_vm_reset_all_ids(adev);
1142
1139
1143
-
return r;
1140
+
return 0;
1144
1141
}
1145
1142
1146
1143
static bool gmc_v7_0_is_idle(void *handle)
+2
-13
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+2
-13
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
···
1209
1209
{
1210
1210
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1211
1211
1212
-
if (adev->vm_manager.enabled) {
1213
-
gmc_v8_0_vm_fini(adev);
1214
-
adev->vm_manager.enabled = false;
1215
-
}
1216
1212
gmc_v8_0_hw_fini(adev);
1217
1213
1218
1214
return 0;
···
1223
1227
if (r)
1224
1228
return r;
1225
1229
1226
-
if (!adev->vm_manager.enabled) {
1227
-
r = gmc_v8_0_vm_init(adev);
1228
-
if (r) {
1229
-
dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1230
-
return r;
1231
-
}
1232
-
adev->vm_manager.enabled = true;
1233
-
}
1230
+
amdgpu_vm_reset_all_ids(adev);
1234
1231
1235
-
return r;
1232
+
return 0;
1236
1233
}
1237
1234
1238
1235
static bool gmc_v8_0_is_idle(void *handle)
+2
-14
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+2
-14
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
···
791
791
{
792
792
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
793
793
794
-
if (adev->vm_manager.enabled) {
795
-
gmc_v9_0_vm_fini(adev);
796
-
adev->vm_manager.enabled = false;
797
-
}
798
794
gmc_v9_0_hw_fini(adev);
799
795
800
796
return 0;
···
805
809
if (r)
806
810
return r;
807
811
808
-
if (!adev->vm_manager.enabled) {
809
-
r = gmc_v9_0_vm_init(adev);
810
-
if (r) {
811
-
dev_err(adev->dev,
812
-
"vm manager initialization failed (%d).\n", r);
813
-
return r;
814
-
}
815
-
adev->vm_manager.enabled = true;
816
-
}
812
+
amdgpu_vm_reset_all_ids(adev);
817
813
818
-
return r;
814
+
return 0;
819
815
}
820
816
821
817
static bool gmc_v9_0_is_idle(void *handle)
+28
-4
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+28
-4
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
···
2655
2655
return sizeof(struct smu7_power_state);
2656
2656
}
2657
2657
2658
+
static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr,
2659
+
uint32_t vblank_time_us)
2660
+
{
2661
+
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2662
+
uint32_t switch_limit_us;
2663
+
2664
+
switch (hwmgr->chip_id) {
2665
+
case CHIP_POLARIS10:
2666
+
case CHIP_POLARIS11:
2667
+
case CHIP_POLARIS12:
2668
+
switch_limit_us = data->is_memory_gddr5 ? 190 : 150;
2669
+
break;
2670
+
default:
2671
+
switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
2672
+
break;
2673
+
}
2674
+
2675
+
if (vblank_time_us < switch_limit_us)
2676
+
return true;
2677
+
else
2678
+
return false;
2679
+
}
2658
2680
2659
2681
static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
2660
2682
struct pp_power_state *request_ps,
···
2691
2669
bool disable_mclk_switching;
2692
2670
bool disable_mclk_switching_for_frame_lock;
2693
2671
struct cgs_display_info info = {0};
2672
+
struct cgs_mode_info mode_info = {0};
2694
2673
const struct phm_clock_and_voltage_limits *max_limits;
2695
2674
uint32_t i;
2696
2675
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
···
2700
2677
int32_t count;
2701
2678
int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
2702
2679
2680
+
info.mode_info = &mode_info;
2703
2681
data->battery_state = (PP_StateUILabel_Battery ==
2704
2682
request_ps->classification.ui_label);
2705
2683
···
2726
2702
smu7_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
2727
2703
2728
2704
cgs_get_active_displays_info(hwmgr->device, &info);
2729
-
2730
-
/*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
2731
2705
2732
2706
minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
2733
2707
minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
···
2791
2769
PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
2792
2770
2793
2771
2794
-
disable_mclk_switching = (1 < info.display_count) ||
2795
-
disable_mclk_switching_for_frame_lock;
2772
+
disable_mclk_switching = ((1 < info.display_count) ||
2773
+
disable_mclk_switching_for_frame_lock ||
2774
+
smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) ||
2775
+
(mode_info.refresh_rate > 120));
2796
2776
2797
2777
sclk = smu7_ps->performance_levels[0].engine_clock;
2798
2778
mclk = smu7_ps->performance_levels[0].memory_clock;
+1
-1
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+1
-1
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+3
-2
drivers/gpu/drm/drm_plane.c
+3
-2
drivers/gpu/drm/drm_plane.c
···
948
948
}
949
949
950
950
out:
951
-
if (ret && crtc->funcs->page_flip_target)
952
-
drm_crtc_vblank_put(crtc);
953
951
if (fb)
954
952
drm_framebuffer_put(fb);
955
953
if (crtc->primary->old_fb)
···
961
963
962
964
drm_modeset_drop_locks(&ctx);
963
965
drm_modeset_acquire_fini(&ctx);
966
+
967
+
if (ret && crtc->funcs->page_flip_target)
968
+
drm_crtc_vblank_put(crtc);
964
969
965
970
return ret;
966
971
}
+11
-7
drivers/gpu/drm/gma500/psb_intel_lvds.c
+11
-7
drivers/gpu/drm/gma500/psb_intel_lvds.c
···
759
759
if (scan->type & DRM_MODE_TYPE_PREFERRED) {
760
760
mode_dev->panel_fixed_mode =
761
761
drm_mode_duplicate(dev, scan);
762
+
DRM_DEBUG_KMS("Using mode from DDC\n");
762
763
goto out; /* FIXME: check for quirks */
763
764
}
764
765
}
765
766
766
767
/* Failed to get EDID, what about VBT? do we need this? */
767
-
if (mode_dev->vbt_mode)
768
+
if (dev_priv->lfp_lvds_vbt_mode) {
768
769
mode_dev->panel_fixed_mode =
769
-
drm_mode_duplicate(dev, mode_dev->vbt_mode);
770
+
drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
770
771
771
-
if (!mode_dev->panel_fixed_mode)
772
-
if (dev_priv->lfp_lvds_vbt_mode)
773
-
mode_dev->panel_fixed_mode =
774
-
drm_mode_duplicate(dev,
775
-
dev_priv->lfp_lvds_vbt_mode);
772
+
if (mode_dev->panel_fixed_mode) {
773
+
mode_dev->panel_fixed_mode->type |=
774
+
DRM_MODE_TYPE_PREFERRED;
775
+
DRM_DEBUG_KMS("Using mode from VBT\n");
776
+
goto out;
777
+
}
778
+
}
776
779
777
780
/*
778
781
* If we didn't get EDID, try checking if the panel is already turned
···
792
789
if (mode_dev->panel_fixed_mode) {
793
790
mode_dev->panel_fixed_mode->type |=
794
791
DRM_MODE_TYPE_PREFERRED;
792
+
DRM_DEBUG_KMS("Using pre-programmed mode\n");
795
793
goto out; /* FIXME: check for quirks */
796
794
}
797
795
}
+2
-2
drivers/gpu/drm/qxl/qxl_display.c
+2
-2
drivers/gpu/drm/qxl/qxl_display.c
···
575
575
if (ret)
576
576
return;
577
577
578
-
cmd = (struct qxl_cursor_cmd *) qxl_release_map(qdev, release);
579
-
580
578
if (fb != old_state->fb) {
581
579
obj = to_qxl_framebuffer(fb)->obj;
582
580
user_bo = gem_to_qxl_bo(obj);
···
612
614
qxl_bo_kunmap(cursor_bo);
613
615
qxl_bo_kunmap(user_bo);
614
616
617
+
cmd = (struct qxl_cursor_cmd *) qxl_release_map(qdev, release);
615
618
cmd->u.set.visible = 1;
616
619
cmd->u.set.shape = qxl_bo_physical_address(qdev,
617
620
cursor_bo, 0);
···
623
624
if (ret)
624
625
goto out_free_release;
625
626
627
+
cmd = (struct qxl_cursor_cmd *) qxl_release_map(qdev, release);
626
628
cmd->type = QXL_CURSOR_MOVE;
627
629
}
628
630
+6
drivers/gpu/drm/radeon/ci_dpm.c
+6
drivers/gpu/drm/radeon/ci_dpm.c
···
776
776
u32 vblank_time = r600_dpm_get_vblank_time(rdev);
777
777
u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
778
778
779
+
/* disable mclk switching if the refresh is >120Hz, even if the
780
+
* blanking period would allow it
781
+
*/
782
+
if (r600_dpm_get_vrefresh(rdev) > 120)
783
+
return true;
784
+
779
785
if (vblank_time < switch_limit)
780
786
return true;
781
787
else
+2
-2
drivers/gpu/drm/radeon/cik.c
+2
-2
drivers/gpu/drm/radeon/cik.c
···
7401
7401
WREG32(DC_HPD5_INT_CONTROL, tmp);
7402
7402
}
7403
7403
if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) {
7404
-
tmp = RREG32(DC_HPD5_INT_CONTROL);
7404
+
tmp = RREG32(DC_HPD6_INT_CONTROL);
7405
7405
tmp |= DC_HPDx_INT_ACK;
7406
7406
WREG32(DC_HPD6_INT_CONTROL, tmp);
7407
7407
}
···
7431
7431
WREG32(DC_HPD5_INT_CONTROL, tmp);
7432
7432
}
7433
7433
if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {
7434
-
tmp = RREG32(DC_HPD5_INT_CONTROL);
7434
+
tmp = RREG32(DC_HPD6_INT_CONTROL);
7435
7435
tmp |= DC_HPDx_RX_INT_ACK;
7436
7436
WREG32(DC_HPD6_INT_CONTROL, tmp);
7437
7437
}
+2
-2
drivers/gpu/drm/radeon/evergreen.c
+2
-2
drivers/gpu/drm/radeon/evergreen.c
···
4927
4927
WREG32(DC_HPD5_INT_CONTROL, tmp);
4928
4928
}
4929
4929
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
4930
-
tmp = RREG32(DC_HPD5_INT_CONTROL);
4930
+
tmp = RREG32(DC_HPD6_INT_CONTROL);
4931
4931
tmp |= DC_HPDx_INT_ACK;
4932
4932
WREG32(DC_HPD6_INT_CONTROL, tmp);
4933
4933
}
···
4958
4958
WREG32(DC_HPD5_INT_CONTROL, tmp);
4959
4959
}
4960
4960
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {
4961
-
tmp = RREG32(DC_HPD5_INT_CONTROL);
4961
+
tmp = RREG32(DC_HPD6_INT_CONTROL);
4962
4962
tmp |= DC_HPDx_RX_INT_ACK;
4963
4963
WREG32(DC_HPD6_INT_CONTROL, tmp);
4964
4964
}
+1
-1
drivers/gpu/drm/radeon/r600.c
+1
-1
drivers/gpu/drm/radeon/r600.c
···
3988
3988
WREG32(DC_HPD5_INT_CONTROL, tmp);
3989
3989
}
3990
3990
if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3991
-
tmp = RREG32(DC_HPD5_INT_CONTROL);
3991
+
tmp = RREG32(DC_HPD6_INT_CONTROL);
3992
3992
tmp |= DC_HPDx_INT_ACK;
3993
3993
WREG32(DC_HPD6_INT_CONTROL, tmp);
3994
3994
}
+1
-1
drivers/gpu/drm/radeon/radeon_kms.c
+1
-1
drivers/gpu/drm/radeon/radeon_kms.c
···
116
116
if ((radeon_runtime_pm != 0) &&
117
117
radeon_has_atpx() &&
118
118
((flags & RADEON_IS_IGP) == 0) &&
119
-
!pci_is_thunderbolt_attached(rdev->pdev))
119
+
!pci_is_thunderbolt_attached(dev->pdev))
120
120
flags |= RADEON_IS_PX;
121
121
122
122
/* radeon_device_init should report only fatal error
+2
-2
drivers/gpu/drm/radeon/si.c
+2
-2
drivers/gpu/drm/radeon/si.c
···
6317
6317
WREG32(DC_HPD5_INT_CONTROL, tmp);
6318
6318
}
6319
6319
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
6320
-
tmp = RREG32(DC_HPD5_INT_CONTROL);
6320
+
tmp = RREG32(DC_HPD6_INT_CONTROL);
6321
6321
tmp |= DC_HPDx_INT_ACK;
6322
6322
WREG32(DC_HPD6_INT_CONTROL, tmp);
6323
6323
}
···
6348
6348
WREG32(DC_HPD5_INT_CONTROL, tmp);
6349
6349
}
6350
6350
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {
6351
-
tmp = RREG32(DC_HPD5_INT_CONTROL);
6351
+
tmp = RREG32(DC_HPD6_INT_CONTROL);
6352
6352
tmp |= DC_HPDx_RX_INT_ACK;
6353
6353
WREG32(DC_HPD6_INT_CONTROL, tmp);
6354
6354
}