Merge tag 'edac_urgent_for_v6.18_rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras

Pull EDAC fixes from Borislav Petkov:

- In Versalnet, handle the reporting of non-standard hw errors whose
information can come in more than one remote processor message.

- Explicitly reenable ECC checking after a warm reset in Altera OCRAM
as those registers are reset to default otherwise

- Fix single-bit error injection in Altera EDAC to not inject errors
directly in ECC RAM and thus lead to false double-bit errors due to
same ECC RAM being in concurrent use

* tag 'edac_urgent_for_v6.18_rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras:
EDAC/altera: Use INTTEST register for Ethernet and USB SBE injection
EDAC/altera: Handle OCRAM ECC enable after warm reset
EDAC/versalnet: Handle split messages for non-standard errors

Linus Torvalds 7 months ago 87751e71 f824272b

+30 -16

2 changed files

expand all

drivers

edac

altera_edac.c

versalnet_edac.c

+17 -5

drivers/edac/altera_edac.c

··· 1184 1184 if (ret) 1185 1185 return ret; 1186 1186 1187 - /* Verify OCRAM has been initialized */ 1187 + /* 1188 + * Verify that OCRAM has been initialized. 1189 + * During a warm reset, OCRAM contents are retained, but the control 1190 + * and status registers are reset to their default values. Therefore, 1191 + * ECC must be explicitly re-enabled in the control register. 1192 + * Error condition: if INITCOMPLETEA is clear and ECC_EN is already set. 1193 + */ 1188 1194 if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA, 1189 - (base + ALTR_A10_ECC_INITSTAT_OFST))) 1190 - return -ENODEV; 1195 + (base + ALTR_A10_ECC_INITSTAT_OFST))) { 1196 + if (!ecc_test_bits(ALTR_A10_ECC_EN, 1197 + (base + ALTR_A10_ECC_CTRL_OFST))) 1198 + ecc_set_bits(ALTR_A10_ECC_EN, 1199 + (base + ALTR_A10_ECC_CTRL_OFST)); 1200 + else 1201 + return -ENODEV; 1202 + } 1191 1203 1192 1204 /* Enable IRQ on Single Bit Error */ 1193 1205 writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST)); ··· 1369 1357 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1370 1358 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1371 1359 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1372 - .inject_fops = &altr_edac_a10_device_inject2_fops, 1360 + .inject_fops = &altr_edac_a10_device_inject_fops, 1373 1361 }; 1374 1362 1375 1363 #endif /* CONFIG_EDAC_ALTERA_ETHERNET */ ··· 1459 1447 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1460 1448 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1461 1449 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1462 - .inject_fops = &altr_edac_a10_device_inject2_fops, 1450 + .inject_fops = &altr_edac_a10_device_inject_fops, 1463 1451 }; 1464 1452 1465 1453 #endif /* CONFIG_EDAC_ALTERA_USB */

+13 -11

drivers/edac/versalnet_edac.c

··· 605 605 length = result[MSG_ERR_LENGTH]; 606 606 offset = result[MSG_ERR_OFFSET]; 607 607 608 + /* 609 + * The data can come in two stretches. Construct the regs from two 610 + * messages. The offset indicates the offset from which the data is to 611 + * be taken. 612 + */ 613 + for (i = 0 ; i < length; i++) { 614 + k = offset + i; 615 + j = ERROR_DATA + i; 616 + mc_priv->regs[k] = result[j]; 617 + } 618 + 608 619 if (result[TOTAL_ERR_LENGTH] > length) { 609 620 if (!mc_priv->part_len) 610 621 mc_priv->part_len = length; 611 622 else 612 623 mc_priv->part_len += length; 613 - /* 614 - * The data can come in 2 stretches. Construct the regs from 2 615 - * messages the offset indicates the offset from which the data is to 616 - * be taken 617 - */ 618 - for (i = 0 ; i < length; i++) { 619 - k = offset + i; 620 - j = ERROR_DATA + i; 621 - mc_priv->regs[k] = result[j]; 622 - } 624 + 623 625 if (mc_priv->part_len < result[TOTAL_ERR_LENGTH]) 624 626 return 0; 625 627 mc_priv->part_len = 0; ··· 707 705 /* Convert to bytes */ 708 706 length = result[TOTAL_ERR_LENGTH] * 4; 709 707 log_non_standard_event(sec_type, &amd_versalnet_guid, mc_priv->message, 710 - sec_sev, (void *)&result[ERROR_DATA], length); 708 + sec_sev, (void *)&mc_priv->regs, length); 711 709 712 710 return 0; 713 711 }

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