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iio: imu: st_lsm6dsx: move wakeup event enable mask to event_src

The mask value being assigned to the irq1_func and irq2_func fields of the
irq_config struct is specific to a single event source (i.e. the wakeup
event), and as such it should be separate from the definition of the
interrupt function registers, which cover multiple event sources.
In preparation for adding support for more event types, change the
irq1_func and irq2_func type from an {address, mask} pair to an address,
and move the mask value to a new field of struct st_lsm6dsx_event_src. No
functional changes.

Signed-off-by: Francesco Lavra <flavra@baylibre.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

authored by

Francesco Lavra and committed by
Jonathan Cameron 87c3e0c1 212234f7

+30 -57
+4 -3
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
··· 267 267 268 268 struct st_lsm6dsx_event_src { 269 269 struct st_lsm6dsx_reg value; 270 + u8 enable_mask; 270 271 struct st_lsm6dsx_reg status; 271 272 u8 status_x_mask; 272 273 u8 status_y_mask; ··· 362 361 struct { 363 362 struct st_lsm6dsx_reg irq1; 364 363 struct st_lsm6dsx_reg irq2; 365 - struct st_lsm6dsx_reg irq1_func; 366 - struct st_lsm6dsx_reg irq2_func; 364 + u8 irq1_func; 365 + u8 irq2_func; 367 366 struct st_lsm6dsx_reg lir; 368 367 struct st_lsm6dsx_reg clear_on_read; 369 368 struct st_lsm6dsx_reg hla; ··· 462 461 u8 ts_sip; 463 462 u8 sip; 464 463 465 - const struct st_lsm6dsx_reg *irq_routing; 464 + u8 irq_routing; 466 465 u8 event_threshold; 467 466 u8 enable_event; 468 467
+26 -54
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
··· 319 319 .addr = 0x58, 320 320 .mask = BIT(0), 321 321 }, 322 - .irq1_func = { 323 - .addr = 0x5e, 324 - .mask = BIT(5), 325 - }, 326 - .irq2_func = { 327 - .addr = 0x5f, 328 - .mask = BIT(5), 329 - }, 322 + .irq1_func = 0x5e, 323 + .irq2_func = 0x5f, 330 324 .hla = { 331 325 .addr = 0x12, 332 326 .mask = BIT(5), ··· 379 385 .addr = 0x5b, 380 386 .mask = GENMASK(5, 0), 381 387 }, 388 + .enable_mask = BIT(5), 382 389 .status = { 383 390 .addr = 0x1b, 384 391 .mask = BIT(3), ··· 486 491 .addr = 0x58, 487 492 .mask = BIT(0), 488 493 }, 489 - .irq1_func = { 490 - .addr = 0x5e, 491 - .mask = BIT(5), 492 - }, 493 - .irq2_func = { 494 - .addr = 0x5f, 495 - .mask = BIT(5), 496 - }, 494 + .irq1_func = 0x5e, 495 + .irq2_func = 0x5f, 497 496 .hla = { 498 497 .addr = 0x12, 499 498 .mask = BIT(5), ··· 546 557 .addr = 0x5b, 547 558 .mask = GENMASK(5, 0), 548 559 }, 560 + .enable_mask = BIT(5), 549 561 .status = { 550 562 .addr = 0x1b, 551 563 .mask = BIT(3), ··· 683 693 .addr = 0x58, 684 694 .mask = BIT(0), 685 695 }, 686 - .irq1_func = { 687 - .addr = 0x5e, 688 - .mask = BIT(5), 689 - }, 690 - .irq2_func = { 691 - .addr = 0x5f, 692 - .mask = BIT(5), 693 - }, 696 + .irq1_func = 0x5e, 697 + .irq2_func = 0x5f, 694 698 .hla = { 695 699 .addr = 0x12, 696 700 .mask = BIT(5), ··· 784 800 .addr = 0x5b, 785 801 .mask = GENMASK(5, 0), 786 802 }, 803 + .enable_mask = BIT(5), 787 804 .status = { 788 805 .addr = 0x1b, 789 806 .mask = BIT(3), ··· 933 948 .addr = 0x56, 934 949 .mask = BIT(6), 935 950 }, 936 - .irq1_func = { 937 - .addr = 0x5e, 938 - .mask = BIT(5), 939 - }, 940 - .irq2_func = { 941 - .addr = 0x5f, 942 - .mask = BIT(5), 943 - }, 951 + .irq1_func = 0x5e, 952 + .irq2_func = 0x5f, 944 953 .hla = { 945 954 .addr = 0x12, 946 955 .mask = BIT(5), ··· 1024 1045 .addr = 0x5b, 1025 1046 .mask = GENMASK(5, 0), 1026 1047 }, 1048 + .enable_mask = BIT(5), 1027 1049 .status = { 1028 1050 .addr = 0x1b, 1029 1051 .mask = BIT(3), ··· 1149 1169 .addr = 0x56, 1150 1170 .mask = BIT(6), 1151 1171 }, 1152 - .irq1_func = { 1153 - .addr = 0x5e, 1154 - .mask = BIT(5), 1155 - }, 1156 - .irq2_func = { 1157 - .addr = 0x5f, 1158 - .mask = BIT(5), 1159 - }, 1172 + .irq1_func = 0x5e, 1173 + .irq2_func = 0x5f, 1160 1174 .hla = { 1161 1175 .addr = 0x12, 1162 1176 .mask = BIT(5), ··· 1208 1234 .addr = 0x5b, 1209 1235 .mask = GENMASK(5, 0), 1210 1236 }, 1237 + .enable_mask = BIT(5), 1211 1238 .status = { 1212 1239 .addr = 0x1b, 1213 1240 .mask = BIT(3), ··· 1327 1352 .addr = 0x56, 1328 1353 .mask = BIT(0), 1329 1354 }, 1330 - .irq1_func = { 1331 - .addr = 0x5e, 1332 - .mask = BIT(5), 1333 - }, 1334 - .irq2_func = { 1335 - .addr = 0x5f, 1336 - .mask = BIT(5), 1337 - }, 1355 + .irq1_func = 0x5e, 1356 + .irq2_func = 0x5f, 1338 1357 .hla = { 1339 1358 .addr = 0x03, 1340 1359 .mask = BIT(4), ··· 1417 1448 .addr = 0x5b, 1418 1449 .mask = GENMASK(5, 0), 1419 1450 }, 1451 + .enable_mask = BIT(5), 1420 1452 .status = { 1421 1453 .addr = 0x45, 1422 1454 .mask = BIT(3), ··· 1878 1908 static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw, bool state) 1879 1909 { 1880 1910 const struct st_lsm6dsx_reg *reg; 1911 + const struct st_lsm6dsx_event_src *src; 1881 1912 unsigned int data; 1882 1913 int err; 1883 1914 1884 - if (!hw->settings->irq_config.irq1_func.addr) 1915 + if (!hw->irq_routing) 1885 1916 return -ENOTSUPP; 1886 1917 1887 1918 reg = &hw->settings->event_settings.enable_reg; ··· 1895 1924 } 1896 1925 1897 1926 /* Enable wakeup interrupt */ 1898 - data = ST_LSM6DSX_SHIFT_VAL(state, hw->irq_routing->mask); 1899 - return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing->addr, 1900 - hw->irq_routing->mask, data); 1927 + src = &hw->settings->event_settings.sources[ST_LSM6DSX_EVENT_WAKEUP]; 1928 + data = ST_LSM6DSX_SHIFT_VAL(state, src->enable_mask); 1929 + return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing, 1930 + src->enable_mask, data); 1901 1931 } 1902 1932 1903 1933 static int st_lsm6dsx_read_event(struct iio_dev *iio_dev, ··· 2152 2180 2153 2181 switch (drdy_pin) { 2154 2182 case 1: 2155 - hw->irq_routing = &hw->settings->irq_config.irq1_func; 2183 + hw->irq_routing = hw->settings->irq_config.irq1_func; 2156 2184 *drdy_reg = &hw->settings->irq_config.irq1; 2157 2185 break; 2158 2186 case 2: 2159 - hw->irq_routing = &hw->settings->irq_config.irq2_func; 2187 + hw->irq_routing = hw->settings->irq_config.irq2_func; 2160 2188 *drdy_reg = &hw->settings->irq_config.irq2; 2161 2189 break; 2162 2190 default: