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clk: qcom: Constify list of critical CBCR registers

The static array 'xxx_critical_cbcrs' contains probe match-like data and
is not modified: neither by the driver defining it nor by common.c code
using it.

Make it const for code safety and code readability.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260331091721.61613-4-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Krzysztof Kozlowski and committed by
Bjorn Andersson
87df31ea 573ddd0d

+33 -33
+1 -1
drivers/clk/qcom/cambistmclkcc-kaanapali.c
··· 383 383 &cam_bist_mclk_cc_pll0, 384 384 }; 385 385 386 - static u32 cam_bist_mclk_cc_kaanapali_critical_cbcrs[] = { 386 + static const u32 cam_bist_mclk_cc_kaanapali_critical_cbcrs[] = { 387 387 0x40e0, /* CAM_BIST_MCLK_CC_SLEEP_CLK */ 388 388 }; 389 389
+1 -1
drivers/clk/qcom/cambistmclkcc-sm8750.c
··· 402 402 &cam_bist_mclk_cc_pll0, 403 403 }; 404 404 405 - static u32 cam_bist_mclk_cc_sm8750_critical_cbcrs[] = { 405 + static const u32 cam_bist_mclk_cc_sm8750_critical_cbcrs[] = { 406 406 0x40f8, /* CAM_BIST_MCLK_CC_SLEEP_CLK */ 407 407 }; 408 408
+1 -1
drivers/clk/qcom/camcc-kaanapali.c
··· 2600 2600 &cam_cc_pll7, 2601 2601 }; 2602 2602 2603 - static u32 cam_cc_kaanapali_critical_cbcrs[] = { 2603 + static const u32 cam_cc_kaanapali_critical_cbcrs[] = { 2604 2604 0x21398, /* CAM_CC_DRV_AHB_CLK */ 2605 2605 0x21390, /* CAM_CC_DRV_XO_CLK */ 2606 2606 0x21364, /* CAM_CC_GDSC_CLK */
+1 -1
drivers/clk/qcom/camcc-milos.c
··· 2104 2104 &cam_cc_pll6, 2105 2105 }; 2106 2106 2107 - static u32 cam_cc_milos_critical_cbcrs[] = { 2107 + static const u32 cam_cc_milos_critical_cbcrs[] = { 2108 2108 0x25038, /* CAM_CC_GDSC_CLK */ 2109 2109 0x2505c, /* CAM_CC_SLEEP_CLK */ 2110 2110 };
+1 -1
drivers/clk/qcom/camcc-sc8180x.c
··· 2829 2829 &cam_cc_pll6, 2830 2830 }; 2831 2831 2832 - static u32 cam_cc_sc8180x_critical_cbcrs[] = { 2832 + static const u32 cam_cc_sc8180x_critical_cbcrs[] = { 2833 2833 0xc1e4, /* CAM_CC_GDSC_CLK */ 2834 2834 0xc200, /* CAM_CC_SLEEP_CLK */ 2835 2835 };
+1 -1
drivers/clk/qcom/camcc-sm8450.c
··· 2915 2915 &cam_cc_pll8, 2916 2916 }; 2917 2917 2918 - static u32 cam_cc_sm8450_critical_cbcrs[] = { 2918 + static const u32 cam_cc_sm8450_critical_cbcrs[] = { 2919 2919 0x1320c, /* CAM_CC_GDSC_CLK */ 2920 2920 }; 2921 2921
+1 -1
drivers/clk/qcom/camcc-sm8550.c
··· 3517 3517 &cam_cc_pll12, 3518 3518 }; 3519 3519 3520 - static u32 cam_cc_sm8550_critical_cbcrs[] = { 3520 + static const u32 cam_cc_sm8550_critical_cbcrs[] = { 3521 3521 0x1419c, /* CAM_CC_GDSC_CLK */ 3522 3522 0x142cc, /* CAM_CC_SLEEP_CLK */ 3523 3523 };
+1 -1
drivers/clk/qcom/camcc-sm8650.c
··· 3533 3533 &cam_cc_pll10, 3534 3534 }; 3535 3535 3536 - static u32 cam_cc_sm8650_critical_cbcrs[] = { 3536 + static const u32 cam_cc_sm8650_critical_cbcrs[] = { 3537 3537 0x132ec, /* CAM_CC_GDSC_CLK */ 3538 3538 0x13308, /* CAM_CC_SLEEP_CLK */ 3539 3539 0x13314, /* CAM_CC_DRV_XO_CLK */
+1 -1
drivers/clk/qcom/camcc-sm8750.c
··· 2651 2651 &cam_cc_pll6, 2652 2652 }; 2653 2653 2654 - static u32 cam_cc_sm8750_critical_cbcrs[] = { 2654 + static const u32 cam_cc_sm8750_critical_cbcrs[] = { 2655 2655 0x113c4, /* CAM_CC_DRV_AHB_CLK */ 2656 2656 0x113c0, /* CAM_CC_DRV_XO_CLK */ 2657 2657 0x1137c, /* CAM_CC_GDSC_CLK */
+1 -1
drivers/clk/qcom/camcc-x1e80100.c
··· 2434 2434 &cam_cc_pll8, 2435 2435 }; 2436 2436 2437 - static u32 cam_cc_x1e80100_critical_cbcrs[] = { 2437 + static const u32 cam_cc_x1e80100_critical_cbcrs[] = { 2438 2438 0x13a9c, /* CAM_CC_GDSC_CLK */ 2439 2439 0x13ab8, /* CAM_CC_SLEEP_CLK */ 2440 2440 };
+1 -1
drivers/clk/qcom/common.h
··· 28 28 struct qcom_cc_driver_data { 29 29 struct clk_alpha_pll **alpha_plls; 30 30 size_t num_alpha_plls; 31 - u32 *clk_cbcrs; 31 + const u32 *clk_cbcrs; 32 32 size_t num_clk_cbcrs; 33 33 const struct clk_rcg_dfs_data *dfs_rcgs; 34 34 size_t num_dfs_rcgs;
+1 -1
drivers/clk/qcom/dispcc-eliza.c
··· 2063 2063 &disp_cc_pll2, 2064 2064 }; 2065 2065 2066 - static u32 disp_cc_eliza_critical_cbcrs[] = { 2066 + static const u32 disp_cc_eliza_critical_cbcrs[] = { 2067 2067 0xe07c, /* DISP_CC_SLEEP_CLK */ 2068 2068 0xe05c, /* DISP_CC_XO_CLK */ 2069 2069 0xc00c, /* DISP_CC_MDSS_RSCC_AHB_CLK */
+1 -1
drivers/clk/qcom/dispcc-glymur.c
··· 1921 1921 &disp_cc_pll1, 1922 1922 }; 1923 1923 1924 - static u32 disp_cc_glymur_critical_cbcrs[] = { 1924 + static const u32 disp_cc_glymur_critical_cbcrs[] = { 1925 1925 0xe07c, /* DISP_CC_SLEEP_CLK */ 1926 1926 0xe05c, /* DISP_CC_XO_CLK */ 1927 1927 };
+1 -1
drivers/clk/qcom/dispcc-kaanapali.c
··· 1886 1886 &disp_cc_pll2, 1887 1887 }; 1888 1888 1889 - static u32 disp_cc_kaanapali_critical_cbcrs[] = { 1889 + static const u32 disp_cc_kaanapali_critical_cbcrs[] = { 1890 1890 0xe064, /* DISP_CC_SLEEP_CLK */ 1891 1891 0xe05c, /* DISP_CC_XO_CLK */ 1892 1892 0xc00c, /* DISP_CC_MDSS_RSCC_AHB_CLK */
+1 -1
drivers/clk/qcom/dispcc-milos.c
··· 906 906 &disp_cc_pll0, 907 907 }; 908 908 909 - static u32 disp_cc_milos_critical_cbcrs[] = { 909 + static const u32 disp_cc_milos_critical_cbcrs[] = { 910 910 0xe06c, /* DISP_CC_SLEEP_CLK */ 911 911 0xe04c, /* DISP_CC_XO_CLK */ 912 912 };
+1 -1
drivers/clk/qcom/dispcc-qcs615.c
··· 739 739 &disp_cc_pll0, 740 740 }; 741 741 742 - static u32 disp_cc_qcs615_critical_cbcrs[] = { 742 + static const u32 disp_cc_qcs615_critical_cbcrs[] = { 743 743 0x6054, /* DISP_CC_XO_CLK */ 744 744 }; 745 745
+1 -1
drivers/clk/qcom/gcc-eliza.c
··· 3005 3005 [GCC_VIDEO_BCR] = { 0x32000 }, 3006 3006 }; 3007 3007 3008 - static u32 gcc_eliza_critical_cbcrs[] = { 3008 + static const u32 gcc_eliza_critical_cbcrs[] = { 3009 3009 0xa0004, /* GCC_CAM_BIST_MCLK_AHB_CLK */ 3010 3010 0x26004, /* GCC_CAMERA_AHB_CLK */ 3011 3011 0x26034, /* GCC_CAMERA_XO_CLK */
+1 -1
drivers/clk/qcom/gcc-glymur.c
··· 8538 8538 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src), 8539 8539 }; 8540 8540 8541 - static u32 gcc_glymur_critical_cbcrs[] = { 8541 + static const u32 gcc_glymur_critical_cbcrs[] = { 8542 8542 0x26004, /* GCC_CAMERA_AHB_CLK */ 8543 8543 0x26040, /* GCC_CAMERA_XO_CLK */ 8544 8544 0x27004, /* GCC_DISP_AHB_CLK */
+1 -1
drivers/clk/qcom/gcc-kaanapali.c
··· 3457 3457 DEFINE_RCG_DFS(gcc_qupv3_wrap4_s4_clk_src), 3458 3458 }; 3459 3459 3460 - static u32 gcc_kaanapali_critical_cbcrs[] = { 3460 + static const u32 gcc_kaanapali_critical_cbcrs[] = { 3461 3461 0xa0004, /* GCC_CAM_BIST_MCLK_AHB_CLK */ 3462 3462 0x26004, /* GCC_CAMERA_AHB_CLK */ 3463 3463 0x2603c, /* GCC_CAMERA_XO_CLK */
+1 -1
drivers/clk/qcom/gcc-milos.c
··· 3152 3152 [USB3_PHY_GDSC] = &usb3_phy_gdsc, 3153 3153 }; 3154 3154 3155 - static u32 gcc_milos_critical_cbcrs[] = { 3155 + static const u32 gcc_milos_critical_cbcrs[] = { 3156 3156 0x26004, /* GCC_CAMERA_AHB_CLK */ 3157 3157 0x26018, /* GCC_CAMERA_HF_XO_CLK */ 3158 3158 0x2601c, /* GCC_CAMERA_SF_XO_CLK */
+1 -1
drivers/clk/qcom/gcc-sc8180x.c
··· 4647 4647 [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, 4648 4648 }; 4649 4649 4650 - static u32 gcc_sc8180x_critical_cbcrs[] = { 4650 + static const u32 gcc_sc8180x_critical_cbcrs[] = { 4651 4651 0xb004, /* GCC_VIDEO_AHB_CLK */ 4652 4652 0xb008, /* GCC_CAMERA_AHB_CLK */ 4653 4653 0xb00c, /* GCC_DISP_AHB_CLK */
+1 -1
drivers/clk/qcom/gpucc-glymur.c
··· 560 560 &gpu_cc_pll0, 561 561 }; 562 562 563 - static u32 gpu_cc_glymur_critical_cbcrs[] = { 563 + static const u32 gpu_cc_glymur_critical_cbcrs[] = { 564 564 0x93a4, /* GPU_CC_CB_CLK */ 565 565 0x9008, /* GPU_CC_CXO_AON_CLK */ 566 566 0x9004, /* GPU_CC_RSCC_XO_AON_CLK */
+1 -1
drivers/clk/qcom/gpucc-kaanapali.c
··· 423 423 &gpu_cc_pll0, 424 424 }; 425 425 426 - static u32 gpu_cc_kaanapali_critical_cbcrs[] = { 426 + static const u32 gpu_cc_kaanapali_critical_cbcrs[] = { 427 427 0x9008, /* GPU_CC_CXO_AON_CLK */ 428 428 0x93e8, /* GPU_CC_RSCC_HUB_AON_CLK */ 429 429 0x9004, /* GPU_CC_RSCC_XO_AON_CLK */
+1 -1
drivers/clk/qcom/gpucc-milos.c
··· 500 500 &gpu_cc_pll0, 501 501 }; 502 502 503 - static u32 gpu_cc_milos_critical_cbcrs[] = { 503 + static const u32 gpu_cc_milos_critical_cbcrs[] = { 504 504 0x93a4, /* GPU_CC_CB_CLK */ 505 505 0x9008, /* GPU_CC_CXO_AON_CLK */ 506 506 0x9010, /* GPU_CC_DEMET_CLK */
+1 -1
drivers/clk/qcom/gpucc-qcs615.c
··· 459 459 &gpu_cc_pll1, 460 460 }; 461 461 462 - static u32 gpu_cc_qcs615_critical_cbcrs[] = { 462 + static const u32 gpu_cc_qcs615_critical_cbcrs[] = { 463 463 0x1078, /* GPU_CC_AHB_CLK */ 464 464 }; 465 465
+1 -1
drivers/clk/qcom/videocc-glymur.c
··· 467 467 &video_cc_pll0, 468 468 }; 469 469 470 - static u32 video_cc_glymur_critical_cbcrs[] = { 470 + static const u32 video_cc_glymur_critical_cbcrs[] = { 471 471 0x80e0, /* VIDEO_CC_AHB_CLK */ 472 472 0x8138, /* VIDEO_CC_SLEEP_CLK */ 473 473 0x8110, /* VIDEO_CC_XO_CLK */
+1 -1
drivers/clk/qcom/videocc-kaanapali.c
··· 741 741 &video_cc_pll3, 742 742 }; 743 743 744 - static u32 video_cc_kaanapali_critical_cbcrs[] = { 744 + static const u32 video_cc_kaanapali_critical_cbcrs[] = { 745 745 0x817c, /* VIDEO_CC_AHB_CLK */ 746 746 0x81bc, /* VIDEO_CC_SLEEP_CLK */ 747 747 0x81b0, /* VIDEO_CC_TS_XO_CLK */
+1 -1
drivers/clk/qcom/videocc-milos.c
··· 345 345 &video_cc_pll0, 346 346 }; 347 347 348 - static u32 video_cc_milos_critical_cbcrs[] = { 348 + static const u32 video_cc_milos_critical_cbcrs[] = { 349 349 0x80f4, /* VIDEO_CC_AHB_CLK */ 350 350 0x8140, /* VIDEO_CC_SLEEP_CLK */ 351 351 0x8124, /* VIDEO_CC_XO_CLK */
+1 -1
drivers/clk/qcom/videocc-qcs615.c
··· 283 283 &video_pll0, 284 284 }; 285 285 286 - static u32 video_cc_qcs615_critical_cbcrs[] = { 286 + static const u32 video_cc_qcs615_critical_cbcrs[] = { 287 287 0xab8, /* VIDEO_CC_XO_CLK */ 288 288 }; 289 289
+1 -1
drivers/clk/qcom/videocc-sm8450.c
··· 413 413 &video_cc_pll1, 414 414 }; 415 415 416 - static u32 video_cc_sm8450_critical_cbcrs[] = { 416 + static const u32 video_cc_sm8450_critical_cbcrs[] = { 417 417 0x80e4, /* VIDEO_CC_AHB_CLK */ 418 418 0x8114, /* VIDEO_CC_XO_CLK */ 419 419 0x8130, /* VIDEO_CC_SLEEP_CLK */
+2 -2
drivers/clk/qcom/videocc-sm8550.c
··· 536 536 &video_cc_pll1, 537 537 }; 538 538 539 - static u32 video_cc_sm8550_critical_cbcrs[] = { 539 + static const u32 video_cc_sm8550_critical_cbcrs[] = { 540 540 0x80f4, /* VIDEO_CC_AHB_CLK */ 541 541 0x8124, /* VIDEO_CC_XO_CLK */ 542 542 0x8140, /* VIDEO_CC_SLEEP_CLK */ 543 543 }; 544 544 545 - static u32 video_cc_sm8650_critical_cbcrs[] = { 545 + static const u32 video_cc_sm8650_critical_cbcrs[] = { 546 546 0x80f4, /* VIDEO_CC_AHB_CLK */ 547 547 0x8124, /* VIDEO_CC_XO_CLK */ 548 548 0x8150, /* VIDEO_CC_SLEEP_CLK */
+1 -1
drivers/clk/qcom/videocc-sm8750.c
··· 392 392 &video_cc_pll0, 393 393 }; 394 394 395 - static u32 video_cc_sm8750_critical_cbcrs[] = { 395 + static const u32 video_cc_sm8750_critical_cbcrs[] = { 396 396 0x80a4, /* VIDEO_CC_AHB_CLK */ 397 397 0x80f8, /* VIDEO_CC_SLEEP_CLK */ 398 398 0x80d4, /* VIDEO_CC_XO_CLK */