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Merge branch 'net-phy-dp83867-always-program-r-sgmii-enable-bits'
Sean Anderson says:
====================
net: phy: dp83867: Always program R/SGMII enable bits
The hardware designers at my company neglected to read the datasheet for
this PHY and did not add appropriate resistors to configure it for
SGMII. Add support for configuring the it based on phy-mode instead of
relying on the resistors for a suitable default.
====================
Link: https://patch.msgid.link/20260129171205.3868605-1-sean.anderson@linux.dev
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+23
-40
+23
-40
drivers/net/phy/dp83867.c
+23
-40
drivers/net/phy/dp83867.c
···
75
75
#define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
76
76
77
77
/* RGMIICTL bits */
78
+
#define DP83867_RGMII_EN BIT(7)
78
79
#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
79
80
#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
80
81
···
101
100
#define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03
102
101
#define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)
103
102
#define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)
104
-
#define DP83867_PHYCR_RESERVED_MASK BIT(11)
103
+
#define DP83867_PHYCR_SGMII_EN BIT(11)
105
104
#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
106
105
107
106
/* RGMIIDCTL bits */
···
745
744
*/
746
745
phy_disable_eee(phydev);
747
746
748
-
if (phy_interface_is_rgmii(phydev) ||
749
-
phydev->interface == PHY_INTERFACE_MODE_SGMII) {
750
-
val = phy_read(phydev, MII_DP83867_PHYCTRL);
751
-
if (val < 0)
752
-
return val;
747
+
val = phy_read(phydev, MII_DP83867_PHYCTRL);
748
+
if (val < 0)
749
+
return val;
753
750
754
-
val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
755
-
val |= (dp83867->tx_fifo_depth <<
756
-
DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
751
+
val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
752
+
val |= (dp83867->tx_fifo_depth <<
753
+
DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
757
754
758
-
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
759
-
val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
760
-
val |= (dp83867->rx_fifo_depth <<
761
-
DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
762
-
}
763
-
764
-
ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
765
-
if (ret)
766
-
return ret;
755
+
val &= ~DP83867_PHYCR_SGMII_EN;
756
+
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
757
+
val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
758
+
val |= (dp83867->rx_fifo_depth <<
759
+
DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT) |
760
+
DP83867_PHYCR_SGMII_EN;
767
761
}
768
762
763
+
ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
764
+
if (ret)
765
+
return ret;
766
+
769
767
if (phy_interface_is_rgmii(phydev)) {
770
-
val = phy_read(phydev, MII_DP83867_PHYCTRL);
771
-
if (val < 0)
772
-
return val;
773
-
774
-
/* The code below checks if "port mirroring" N/A MODE4 has been
775
-
* enabled during power on bootstrap.
776
-
*
777
-
* Such N/A mode enabled by mistake can put PHY IC in some
778
-
* internal testing mode and disable RGMII transmission.
779
-
*
780
-
* In this particular case one needs to check STRAP_STS1
781
-
* register's bit 11 (marked as RESERVED).
782
-
*/
783
-
784
-
bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
785
-
if (bs & DP83867_STRAP_STS1_RESERVED)
786
-
val &= ~DP83867_PHYCR_RESERVED_MASK;
787
-
788
-
ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
789
-
if (ret)
790
-
return ret;
791
-
792
768
/* Set up RGMII delays */
793
769
val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
794
770
771
+
val |= DP83867_RGMII_EN;
795
772
val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
796
773
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
797
774
val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
···
785
806
phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
786
807
dp83867->rx_id_delay |
787
808
(dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
809
+
} else {
810
+
val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
811
+
val &= ~DP83867_RGMII_EN;
812
+
phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
788
813
}
789
814
790
815
/* If specified, set io impedance */