tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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RDMA/irdma: Extend QP context programming for GEN3

Extend the QP context structure with support for new fields
specific to GEN3 hardware capabilities.

Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com>
Signed-off-by: Tatyana Nikolova <tatyana.e.nikolova@intel.com>
Link: https://patch.msgid.link/20250827152545.2056-10-tatyana.e.nikolova@intel.com
Tested-by: Jacob Moroni <jmoroni@google.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>

authored by

Shiraz Saleem and committed by
Leon Romanovsky 87f413b6 d6ed4b69

+215 -7
+181 -3
drivers/infiniband/hw/irdma/ctrl.c
··· 637 637 } 638 638 639 639 /** 640 - * irdma_sc_qp_setctx_roce - set qp's context 640 + * irdma_sc_qp_setctx_roce_gen_2 - set qp's context 641 641 * @qp: sc qp 642 642 * @qp_ctx: context ptr 643 643 * @info: ctx info 644 644 */ 645 - void irdma_sc_qp_setctx_roce(struct irdma_sc_qp *qp, __le64 *qp_ctx, 646 - struct irdma_qp_host_ctx_info *info) 645 + static void irdma_sc_qp_setctx_roce_gen_2(struct irdma_sc_qp *qp, 646 + __le64 *qp_ctx, 647 + struct irdma_qp_host_ctx_info *info) 647 648 { 648 649 struct irdma_roce_offload_info *roce_info; 649 650 struct irdma_udp_offload_info *udp; ··· 760 759 761 760 print_hex_dump_debug("WQE: QP_HOST CTX WQE", DUMP_PREFIX_OFFSET, 16, 762 761 8, qp_ctx, IRDMA_QP_CTX_SIZE, false); 762 + } 763 + 764 + /** 765 + * irdma_sc_get_encoded_ird_size_gen_3 - get encoded IRD size for GEN 3 766 + * @ird_size: IRD size 767 + * The ird from the connection is rounded to a supported HW setting and then encoded 768 + * for ird_size field of qp_ctx. Consumers are expected to provide valid ird size based 769 + * on hardware attributes. IRD size defaults to a value of 4 in case of invalid input. 770 + */ 771 + static u8 irdma_sc_get_encoded_ird_size_gen_3(u16 ird_size) 772 + { 773 + switch (ird_size ? 774 + roundup_pow_of_two(2 * ird_size) : 4) { 775 + case 4096: 776 + return IRDMA_IRD_HW_SIZE_4096_GEN3; 777 + case 2048: 778 + return IRDMA_IRD_HW_SIZE_2048_GEN3; 779 + case 1024: 780 + return IRDMA_IRD_HW_SIZE_1024_GEN3; 781 + case 512: 782 + return IRDMA_IRD_HW_SIZE_512_GEN3; 783 + case 256: 784 + return IRDMA_IRD_HW_SIZE_256_GEN3; 785 + case 128: 786 + return IRDMA_IRD_HW_SIZE_128_GEN3; 787 + case 64: 788 + return IRDMA_IRD_HW_SIZE_64_GEN3; 789 + case 32: 790 + return IRDMA_IRD_HW_SIZE_32_GEN3; 791 + case 16: 792 + return IRDMA_IRD_HW_SIZE_16_GEN3; 793 + case 8: 794 + return IRDMA_IRD_HW_SIZE_8_GEN3; 795 + case 4: 796 + default: 797 + break; 798 + } 799 + 800 + return IRDMA_IRD_HW_SIZE_4_GEN3; 801 + } 802 + 803 + /** 804 + * irdma_sc_qp_setctx_roce_gen_3 - set qp's context 805 + * @qp: sc qp 806 + * @qp_ctx: context ptr 807 + * @info: ctx info 808 + */ 809 + static void irdma_sc_qp_setctx_roce_gen_3(struct irdma_sc_qp *qp, 810 + __le64 *qp_ctx, 811 + struct irdma_qp_host_ctx_info *info) 812 + { 813 + struct irdma_roce_offload_info *roce_info = info->roce_info; 814 + struct irdma_udp_offload_info *udp = info->udp_info; 815 + u64 qw0, qw3, qw7 = 0, qw8 = 0; 816 + u8 push_mode_en; 817 + u32 push_idx; 818 + 819 + qp->user_pri = info->user_pri; 820 + if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) { 821 + push_mode_en = 0; 822 + push_idx = 0; 823 + } else { 824 + push_mode_en = 1; 825 + push_idx = qp->push_idx; 826 + } 827 + 828 + qw0 = FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) | 829 + FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) | 830 + FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) | 831 + FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) | 832 + FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) | 833 + FIELD_PREP(IRDMAQPC_PPIDX, push_idx) | 834 + FIELD_PREP(IRDMAQPC_PMENA, push_mode_en) | 835 + FIELD_PREP(IRDMAQPC_DC_TCP_EN, roce_info->dctcp_en) | 836 + FIELD_PREP(IRDMAQPC_ISQP1, roce_info->is_qp1) | 837 + FIELD_PREP(IRDMAQPC_ROCE_TVER, roce_info->roce_tver) | 838 + FIELD_PREP(IRDMAQPC_IPV4, udp->ipv4) | 839 + FIELD_PREP(IRDMAQPC_INSERTVLANTAG, udp->insert_vlan_tag); 840 + set_64bit_val(qp_ctx, 0, qw0); 841 + set_64bit_val(qp_ctx, 8, qp->sq_pa); 842 + set_64bit_val(qp_ctx, 16, qp->rq_pa); 843 + qw3 = FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) | 844 + FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size) | 845 + FIELD_PREP(IRDMAQPC_TTL, udp->ttl) | 846 + FIELD_PREP(IRDMAQPC_TOS, udp->tos) | 847 + FIELD_PREP(IRDMAQPC_SRCPORTNUM, udp->src_port) | 848 + FIELD_PREP(IRDMAQPC_DESTPORTNUM, udp->dst_port); 849 + set_64bit_val(qp_ctx, 24, qw3); 850 + set_64bit_val(qp_ctx, 32, 851 + FIELD_PREP(IRDMAQPC_DESTIPADDR2, udp->dest_ip_addr[2]) | 852 + FIELD_PREP(IRDMAQPC_DESTIPADDR3, udp->dest_ip_addr[3])); 853 + set_64bit_val(qp_ctx, 40, 854 + FIELD_PREP(IRDMAQPC_DESTIPADDR0, udp->dest_ip_addr[0]) | 855 + FIELD_PREP(IRDMAQPC_DESTIPADDR1, udp->dest_ip_addr[1])); 856 + set_64bit_val(qp_ctx, 48, 857 + FIELD_PREP(IRDMAQPC_SNDMSS, udp->snd_mss) | 858 + FIELD_PREP(IRDMAQPC_VLANTAG, udp->vlan_tag) | 859 + FIELD_PREP(IRDMAQPC_ARPIDX, udp->arp_idx)); 860 + qw7 = FIELD_PREP(IRDMAQPC_PKEY, roce_info->p_key) | 861 + FIELD_PREP(IRDMAQPC_ACKCREDITS, roce_info->ack_credits) | 862 + FIELD_PREP(IRDMAQPC_FLOWLABEL, udp->flow_label); 863 + set_64bit_val(qp_ctx, 56, qw7); 864 + qw8 = FIELD_PREP(IRDMAQPC_QKEY, roce_info->qkey) | 865 + FIELD_PREP(IRDMAQPC_DESTQP, roce_info->dest_qp); 866 + set_64bit_val(qp_ctx, 64, qw8); 867 + set_64bit_val(qp_ctx, 80, 868 + FIELD_PREP(IRDMAQPC_PSNNXT, udp->psn_nxt) | 869 + FIELD_PREP(IRDMAQPC_LSN, udp->lsn)); 870 + set_64bit_val(qp_ctx, 88, 871 + FIELD_PREP(IRDMAQPC_EPSN, udp->epsn)); 872 + set_64bit_val(qp_ctx, 96, 873 + FIELD_PREP(IRDMAQPC_PSNMAX, udp->psn_max) | 874 + FIELD_PREP(IRDMAQPC_PSNUNA, udp->psn_una)); 875 + set_64bit_val(qp_ctx, 112, 876 + FIELD_PREP(IRDMAQPC_CWNDROCE, udp->cwnd)); 877 + set_64bit_val(qp_ctx, 128, 878 + FIELD_PREP(IRDMAQPC_MINRNR_TIMER, udp->min_rnr_timer) | 879 + FIELD_PREP(IRDMAQPC_RNRNAK_THRESH, udp->rnr_nak_thresh) | 880 + FIELD_PREP(IRDMAQPC_REXMIT_THRESH, udp->rexmit_thresh) | 881 + FIELD_PREP(IRDMAQPC_RNRNAK_TMR, udp->rnr_nak_tmr) | 882 + FIELD_PREP(IRDMAQPC_RTOMIN, roce_info->rtomin)); 883 + set_64bit_val(qp_ctx, 136, 884 + FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) | 885 + FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num)); 886 + set_64bit_val(qp_ctx, 152, 887 + FIELD_PREP(IRDMAQPC_MACADDRESS, 888 + ether_addr_to_u64(roce_info->mac_addr)) | 889 + FIELD_PREP(IRDMAQPC_LOCALACKTIMEOUT, 890 + roce_info->local_ack_timeout)); 891 + set_64bit_val(qp_ctx, 160, 892 + FIELD_PREP(IRDMAQPC_ORDSIZE_GEN3, roce_info->ord_size) | 893 + FIELD_PREP(IRDMAQPC_IRDSIZE_GEN3, 894 + irdma_sc_get_encoded_ird_size_gen_3(roce_info->ird_size)) | 895 + FIELD_PREP(IRDMAQPC_WRRDRSPOK, roce_info->wr_rdresp_en) | 896 + FIELD_PREP(IRDMAQPC_RDOK, roce_info->rd_en) | 897 + FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, 898 + info->stats_idx_valid) | 899 + FIELD_PREP(IRDMAQPC_BINDEN, roce_info->bind_en) | 900 + FIELD_PREP(IRDMAQPC_FASTREGEN, roce_info->fast_reg_en) | 901 + FIELD_PREP(IRDMAQPC_DCQCNENABLE, roce_info->dcqcn_en) | 902 + FIELD_PREP(IRDMAQPC_RCVNOICRC, roce_info->rcv_no_icrc) | 903 + FIELD_PREP(IRDMAQPC_FW_CC_ENABLE, 904 + roce_info->fw_cc_enable) | 905 + FIELD_PREP(IRDMAQPC_UDPRIVCQENABLE, 906 + roce_info->udprivcq_en) | 907 + FIELD_PREP(IRDMAQPC_PRIVEN, roce_info->priv_mode_en) | 908 + FIELD_PREP(IRDMAQPC_TIMELYENABLE, roce_info->timely_en)); 909 + set_64bit_val(qp_ctx, 168, 910 + FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx)); 911 + set_64bit_val(qp_ctx, 176, 912 + FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) | 913 + FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) | 914 + FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle)); 915 + set_64bit_val(qp_ctx, 184, 916 + FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, udp->local_ipaddr[3]) | 917 + FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, udp->local_ipaddr[2])); 918 + set_64bit_val(qp_ctx, 192, 919 + FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, udp->local_ipaddr[1]) | 920 + FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, udp->local_ipaddr[0])); 921 + set_64bit_val(qp_ctx, 200, 922 + FIELD_PREP(IRDMAQPC_THIGH, roce_info->t_high) | 923 + FIELD_PREP(IRDMAQPC_TLOW, roce_info->t_low)); 924 + set_64bit_val(qp_ctx, 208, roce_info->pd_id | 925 + FIELD_PREP(IRDMAQPC_STAT_INDEX_GEN3, info->stats_idx) | 926 + FIELD_PREP(IRDMAQPC_PKT_LIMIT, qp->pkt_limit)); 927 + 928 + print_hex_dump_debug("WQE: QP_HOST ROCE CTX WQE", DUMP_PREFIX_OFFSET, 929 + 16, 8, qp_ctx, IRDMA_QP_CTX_SIZE, false); 930 + } 931 + 932 + void irdma_sc_qp_setctx_roce(struct irdma_sc_qp *qp, __le64 *qp_ctx, 933 + struct irdma_qp_host_ctx_info *info) 934 + { 935 + if (qp->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2) 936 + irdma_sc_qp_setctx_roce_gen_2(qp, qp_ctx, info); 937 + else 938 + irdma_sc_qp_setctx_roce_gen_3(qp, qp_ctx, info); 763 939 } 764 940 765 941 /* irdma_sc_alloc_local_mac_entry - allocate a mac entry
+23 -1
drivers/infiniband/hw/irdma/defs.h
··· 14 14 #define IRDMA_PE_DB_SIZE_4M 1 15 15 #define IRDMA_PE_DB_SIZE_8M 2 16 16 17 + #define IRDMA_IRD_HW_SIZE_4_GEN3 0 18 + #define IRDMA_IRD_HW_SIZE_8_GEN3 1 19 + #define IRDMA_IRD_HW_SIZE_16_GEN3 2 20 + #define IRDMA_IRD_HW_SIZE_32_GEN3 3 21 + #define IRDMA_IRD_HW_SIZE_64_GEN3 4 22 + #define IRDMA_IRD_HW_SIZE_128_GEN3 5 23 + #define IRDMA_IRD_HW_SIZE_256_GEN3 6 24 + #define IRDMA_IRD_HW_SIZE_512_GEN3 7 25 + #define IRDMA_IRD_HW_SIZE_1024_GEN3 8 26 + #define IRDMA_IRD_HW_SIZE_2048_GEN3 9 27 + #define IRDMA_IRD_HW_SIZE_4096_GEN3 10 28 + 17 29 #define IRDMA_IRD_HW_SIZE_4 0 18 30 #define IRDMA_IRD_HW_SIZE_16 1 19 31 #define IRDMA_IRD_HW_SIZE_64 2 ··· 848 836 #define IRDMAQPC_CWNDROCE GENMASK_ULL(55, 32) 849 837 #define IRDMAQPC_SNDWL1 GENMASK_ULL(31, 0) 850 838 #define IRDMAQPC_SNDWL2 GENMASK_ULL(63, 32) 851 - #define IRDMAQPC_ERR_RQ_IDX GENMASK_ULL(45, 32) 839 + #define IRDMAQPC_MINRNR_TIMER GENMASK_ULL(4, 0) 840 + #define IRDMAQPC_ERR_RQ_IDX GENMASK_ULL(46, 32) 852 841 #define IRDMAQPC_RTOMIN GENMASK_ULL(63, 57) 853 842 #define IRDMAQPC_MAXSNDWND GENMASK_ULL(31, 0) 854 843 #define IRDMAQPC_REXMIT_THRESH GENMASK_ULL(53, 48) ··· 862 849 #define IRDMAQPC_MACADDRESS GENMASK_ULL(63, 16) 863 850 #define IRDMAQPC_ORDSIZE GENMASK_ULL(7, 0) 864 851 852 + #define IRDMAQPC_LOCALACKTIMEOUT GENMASK_ULL(12, 8) 853 + #define IRDMAQPC_RNRNAK_TMR GENMASK_ULL(4, 0) 854 + #define IRDMAQPC_ORDSIZE_GEN3 GENMASK_ULL(10, 0) 855 + #define IRDMAQPC_REMOTE_ATOMIC_EN BIT_ULL(18) 856 + #define IRDMAQPC_STAT_INDEX_GEN3 GENMASK_ULL(47, 32) 857 + #define IRDMAQPC_PKT_LIMIT GENMASK_ULL(55, 48) 858 + 865 859 #define IRDMAQPC_IRDSIZE GENMASK_ULL(18, 16) 860 + 861 + #define IRDMAQPC_IRDSIZE_GEN3 GENMASK_ULL(17, 14) 866 862 867 863 #define IRDMAQPC_UDPRIVCQENABLE BIT_ULL(19) 868 864 #define IRDMAQPC_WRRDRSPOK BIT_ULL(20)
+4
drivers/infiniband/hw/irdma/type.h
··· 574 574 bool flush_rq:1; 575 575 bool sq_flush_code:1; 576 576 bool rq_flush_code:1; 577 + u32 pkt_limit; 577 578 enum irdma_flush_opcode flush_code; 578 579 enum irdma_qp_event_type event_type; 579 580 u8 term_flags; ··· 916 915 u32 cwnd; 917 916 u8 rexmit_thresh; 918 917 u8 rnr_nak_thresh; 918 + u8 rnr_nak_tmr; 919 + u8 min_rnr_timer; 919 920 }; 920 921 921 922 struct irdma_roce_offload_info { ··· 944 941 bool dctcp_en:1; 945 942 bool fw_cc_enable:1; 946 943 bool use_stats_inst:1; 944 + u8 local_ack_timeout; 947 945 u16 t_high; 948 946 u16 t_low; 949 947 u8 last_byte_sent;
+2 -3
drivers/infiniband/hw/irdma/uda_d.h
··· 78 78 #define IRDMA_UDAQPC_IPID GENMASK_ULL(47, 32) 79 79 #define IRDMA_UDAQPC_SNDMSS GENMASK_ULL(29, 16) 80 80 #define IRDMA_UDAQPC_VLANTAG GENMASK_ULL(15, 0) 81 - 82 - #define IRDMA_UDA_CQPSQ_MAV_PDINDEXHI GENMASK_ULL(21, 20) 81 + #define IRDMA_UDA_CQPSQ_MAV_PDINDEXHI GENMASK_ULL(27, 20) 83 82 #define IRDMA_UDA_CQPSQ_MAV_PDINDEXLO GENMASK_ULL(63, 48) 84 83 #define IRDMA_UDA_CQPSQ_MAV_SRCMACADDRINDEX GENMASK_ULL(29, 24) 85 84 #define IRDMA_UDA_CQPSQ_MAV_ARPINDEX GENMASK_ULL(63, 48) ··· 93 94 #define IRDMA_UDA_CQPSQ_MAV_OPCODE GENMASK_ULL(37, 32) 94 95 #define IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK BIT_ULL(62) 95 96 #define IRDMA_UDA_CQPSQ_MAV_IPV4VALID BIT_ULL(59) 96 - #define IRDMA_UDA_CQPSQ_MAV_AVIDX GENMASK_ULL(16, 0) 97 + #define IRDMA_UDA_CQPSQ_MAV_AVIDX GENMASK_ULL(23, 0) 97 98 #define IRDMA_UDA_CQPSQ_MAV_INSERTVLANTAG BIT_ULL(60) 98 99 #define IRDMA_UDA_MGCTX_VFFLAG BIT_ULL(29) 99 100 #define IRDMA_UDA_MGCTX_DESTPORT GENMASK_ULL(47, 32)
+5
drivers/infiniband/hw/irdma/verbs.c
··· 1162 1162 attr->pkey_index = iwqp->roce_info.p_key; 1163 1163 attr->retry_cnt = iwqp->udp_info.rexmit_thresh; 1164 1164 attr->rnr_retry = iwqp->udp_info.rnr_nak_thresh; 1165 + attr->min_rnr_timer = iwqp->udp_info.min_rnr_timer; 1165 1166 attr->max_rd_atomic = iwqp->roce_info.ord_size; 1166 1167 attr->max_dest_rd_atomic = iwqp->roce_info.ird_size; 1167 1168 } ··· 1294 1293 1295 1294 if (attr_mask & IB_QP_RNR_RETRY) 1296 1295 udp_info->rnr_nak_thresh = attr->rnr_retry; 1296 + 1297 + if (attr_mask & IB_QP_MIN_RNR_TIMER && 1298 + dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) 1299 + udp_info->min_rnr_timer = attr->min_rnr_timer; 1297 1300 1298 1301 if (attr_mask & IB_QP_RETRY_CNT) 1299 1302 udp_info->rexmit_thresh = attr->retry_cnt;