Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: renesas: Move RPC core clocks
The RPC and RPCD2 core clocks were added to the sections for internal
core clocks, while they are core clock outputs, visible from DT.
Move them to the correct sections.
Rename the ".rpc" clock on R-Car S4 to "rpc".
Fixup nearby whitespace to increase uniformity.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/a938b938f00939b9206d7fbaba78e2ef09915f5f.1649681891.git.geert+renesas@glider.be
+52
-58
+4
-5
drivers/clk/renesas/r8a774a1-cpg-mssr.c
+4
-5
drivers/clk/renesas/r8a774a1-cpg-mssr.c
···
68
68
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
69
69
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
70
70
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
71
-
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
72
71
73
-
DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC,
74
-
CLK_RPCSRC),
75
-
DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
76
-
R8A774A1_CLK_RPC),
72
+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
77
73
78
74
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
79
75
···
104
108
DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, R8A774A1_CLK_SD1H, 0x078),
105
109
DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, R8A774A1_CLK_SD2H, 0x268),
106
110
DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, R8A774A1_CLK_SD3H, 0x26c),
111
+
112
+
DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
113
+
DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774A1_CLK_RPC),
107
114
108
115
DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
109
116
DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1),
+4
-5
drivers/clk/renesas/r8a774b1-cpg-mssr.c
+4
-5
drivers/clk/renesas/r8a774b1-cpg-mssr.c
···
66
66
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
67
67
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
68
68
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
69
-
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
70
69
71
-
DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC,
72
-
CLK_RPCSRC),
73
-
DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
74
-
R8A774B1_CLK_RPC),
70
+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
75
71
76
72
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
77
73
···
101
105
DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, R8A774B1_CLK_SD1H, 0x078),
102
106
DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268),
103
107
DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c),
108
+
109
+
DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
110
+
DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774B1_CLK_RPC),
104
111
105
112
DEF_FIXED("cl", R8A774B1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
106
113
DEF_FIXED("cp", R8A774B1_CLK_CP, CLK_EXTAL, 2, 1),
+3
-5
drivers/clk/renesas/r8a774c0-cpg-mssr.c
+3
-5
drivers/clk/renesas/r8a774c0-cpg-mssr.c
···
77
77
78
78
DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
79
79
80
-
DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,
81
-
CLK_RPCSRC),
82
-
DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
83
-
R8A774C0_CLK_RPC),
84
-
85
80
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
86
81
87
82
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
···
102
107
DEF_FIXED("s3d1", R8A774C0_CLK_S3D1, CLK_S3, 1, 1),
103
108
DEF_FIXED("s3d2", R8A774C0_CLK_S3D2, CLK_S3, 2, 1),
104
109
DEF_FIXED("s3d4", R8A774C0_CLK_S3D4, CLK_S3, 4, 1),
110
+
111
+
DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
112
+
DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774C0_CLK_RPC),
105
113
106
114
DEF_GEN3_SDH("sd0h", R8A774C0_CLK_SD0H, CLK_SDSRC, 0x0074),
107
115
DEF_GEN3_SDH("sd1h", R8A774C0_CLK_SD1H, CLK_SDSRC, 0x0078),
+4
-5
drivers/clk/renesas/r8a774e1-cpg-mssr.c
+4
-5
drivers/clk/renesas/r8a774e1-cpg-mssr.c
···
68
68
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
69
69
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
70
70
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
71
-
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
72
71
73
-
DEF_BASE("rpc", R8A774E1_CLK_RPC, CLK_TYPE_GEN3_RPC,
74
-
CLK_RPCSRC),
75
-
DEF_BASE("rpcd2", R8A774E1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
76
-
R8A774E1_CLK_RPC),
72
+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
77
73
78
74
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
79
75
···
104
108
DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, R8A774E1_CLK_SD1H, 0x078),
105
109
DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, R8A774E1_CLK_SD2H, 0x268),
106
110
DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, R8A774E1_CLK_SD3H, 0x26c),
111
+
112
+
DEF_BASE("rpc", R8A774E1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
113
+
DEF_BASE("rpcd2", R8A774E1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774E1_CLK_RPC),
107
114
108
115
DEF_FIXED("cl", R8A774E1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
109
116
DEF_FIXED("cr", R8A774E1_CLK_CR, CLK_PLL1_DIV4, 2, 1),
+4
-5
drivers/clk/renesas/r8a7795-cpg-mssr.c
+4
-5
drivers/clk/renesas/r8a7795-cpg-mssr.c
···
71
71
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
72
72
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
73
73
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
74
-
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
75
74
76
-
DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC,
77
-
CLK_RPCSRC),
78
-
DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
79
-
R8A7795_CLK_RPC),
75
+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
80
76
81
77
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
82
78
···
108
112
DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, R8A7795_CLK_SD1H, 0x078),
109
113
DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, R8A7795_CLK_SD2H, 0x268),
110
114
DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, R8A7795_CLK_SD3H, 0x26c),
115
+
116
+
DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
117
+
DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A7795_CLK_RPC),
111
118
112
119
DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
113
120
DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1),
+4
-5
drivers/clk/renesas/r8a7796-cpg-mssr.c
+4
-5
drivers/clk/renesas/r8a7796-cpg-mssr.c
···
73
73
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
74
74
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
75
75
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
76
-
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
77
76
78
-
DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC,
79
-
CLK_RPCSRC),
80
-
DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
81
-
R8A7796_CLK_RPC),
77
+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
82
78
83
79
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
84
80
···
110
114
DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, R8A7796_CLK_SD1H, 0x078),
111
115
DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, R8A7796_CLK_SD2H, 0x268),
112
116
DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, R8A7796_CLK_SD3H, 0x26c),
117
+
118
+
DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
119
+
DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A7796_CLK_RPC),
113
120
114
121
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
115
122
DEF_FIXED("cr", R8A7796_CLK_CR, CLK_PLL1_DIV4, 2, 1),
+4
-5
drivers/clk/renesas/r8a77965-cpg-mssr.c
+4
-5
drivers/clk/renesas/r8a77965-cpg-mssr.c
···
69
69
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
70
70
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
71
71
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
72
-
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
73
72
74
-
DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC,
75
-
CLK_RPCSRC),
76
-
DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
77
-
R8A77965_CLK_RPC),
73
+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
78
74
79
75
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
80
76
···
105
109
DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, R8A77965_CLK_SD1H, 0x078),
106
110
DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, R8A77965_CLK_SD2H, 0x268),
107
111
DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, R8A77965_CLK_SD3H, 0x26c),
112
+
113
+
DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
114
+
DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77965_CLK_RPC),
108
115
109
116
DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
110
117
DEF_FIXED("cr", R8A77965_CLK_CR, CLK_PLL1_DIV4, 2, 1),
+6
-6
drivers/clk/renesas/r8a77980-cpg-mssr.c
+6
-6
drivers/clk/renesas/r8a77980-cpg-mssr.c
···
66
66
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
67
67
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
68
68
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
69
-
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
70
-
DEF_RATE(".oco", CLK_OCO, 32768),
71
69
72
-
DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC,
73
-
CLK_RPCSRC),
74
-
DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
75
-
R8A77980_CLK_RPC),
70
+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
71
+
72
+
DEF_RATE(".oco", CLK_OCO, 32768),
76
73
77
74
/* Core Clock Outputs */
78
75
DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
···
95
98
96
99
DEF_GEN3_SDH("sd0h", R8A77980_CLK_SD0H, CLK_SDSRC, 0x0074),
97
100
DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, R8A77980_CLK_SD0H, 0x0074),
101
+
102
+
DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
103
+
DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77980_CLK_RPC),
98
104
99
105
DEF_FIXED("cl", R8A77980_CLK_CL, CLK_PLL1_DIV2, 48, 1),
100
106
DEF_FIXED("cp", R8A77980_CLK_CP, CLK_EXTAL, 2, 1),
+2
-4
drivers/clk/renesas/r8a77990-cpg-mssr.c
+2
-4
drivers/clk/renesas/r8a77990-cpg-mssr.c
···
110
110
DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, R8A77990_CLK_SD1H, 0x0078),
111
111
DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, R8A77990_CLK_SD3H, 0x026c),
112
112
113
-
DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC,
114
-
CLK_RPCSRC),
115
-
DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
116
-
R8A77990_CLK_RPC),
113
+
DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
114
+
DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77990_CLK_RPC),
117
115
118
116
DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
119
117
DEF_FIXED("cr", R8A77990_CLK_CR, CLK_PLL1D2, 2, 1),
+4
-6
drivers/clk/renesas/r8a77995-cpg-mssr.c
+4
-6
drivers/clk/renesas/r8a77995-cpg-mssr.c
···
106
106
DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
107
107
DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
108
108
109
-
DEF_GEN3_SDH("sd0h", R8A77995_CLK_SD0H, CLK_SDSRC, 0x268),
110
-
DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, R8A77995_CLK_SD0H, 0x268),
109
+
DEF_GEN3_SDH("sd0h", R8A77995_CLK_SD0H, CLK_SDSRC, 0x268),
110
+
DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, R8A77995_CLK_SD0H, 0x268),
111
111
112
-
DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC,
113
-
CLK_RPCSRC),
114
-
DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
115
-
R8A77995_CLK_RPC),
112
+
DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
113
+
DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77995_CLK_RPC),
116
114
117
115
DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244),
118
116
DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014),
+7
-4
drivers/clk/renesas/r8a779a0-cpg-mssr.c
+7
-4
drivers/clk/renesas/r8a779a0-cpg-mssr.c
···
85
85
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1),
86
86
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1),
87
87
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV4, 1, 1),
88
+
88
89
DEF_RATE(".oco", CLK_OCO, 32768),
89
-
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
90
-
DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
91
-
DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2,
92
-
R8A779A0_CLK_RPC),
90
+
91
+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
93
92
94
93
/* Core Clock Outputs */
95
94
DEF_GEN4_Z("z0", R8A779A0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL20, 2, 0),
···
118
119
119
120
DEF_GEN4_SDH("sdh0", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870),
120
121
DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870),
122
+
123
+
DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
124
+
DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2,
125
+
R8A779A0_CLK_RPC),
121
126
122
127
DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
123
128
DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
+6
-3
drivers/clk/renesas/r8a779f0-cpg-mssr.c
+6
-3
drivers/clk/renesas/r8a779f0-cpg-mssr.c
···
70
70
DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
71
71
DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
72
72
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
73
+
73
74
DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
74
75
DEF_RATE(".oco", CLK_OCO, 32768),
75
76
76
-
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
77
-
DEF_BASE(".rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
78
-
DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC),
77
+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
79
78
80
79
/* Core Clock Outputs */
81
80
DEF_FIXED("s0d2", R8A779F0_CLK_S0D2, CLK_S0, 2, 1),
···
107
108
DEF_FIXED("cpex", R8A779F0_CLK_CPEX, CLK_EXTAL, 2, 1),
108
109
109
110
DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, CLK_SDSRC, 0x870),
111
+
112
+
DEF_BASE("rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
113
+
DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC),
114
+
110
115
DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
111
116
112
117
DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8),