tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amdgpu: Rename xcc specific functions

Add 'xcc' prefix to xcc specific functions to distinguish from IP block
functions.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Lijo Lazar and committed by
Alex Deucher 880f8b3f 497db7ea

+113 -92
+113 -92
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
··· 506 506 return 0; 507 507 } 508 508 509 - static void gfx_v9_4_3_select_se_sh(struct amdgpu_device *adev, 510 - u32 se_num, 511 - u32 sh_num, 512 - u32 instance, 513 - int xcc_id) 509 + static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 510 + u32 sh_num, u32 instance, int xcc_id) 514 511 { 515 512 u32 data; 516 513 ··· 675 678 676 679 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 677 680 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 678 - .select_se_sh = &gfx_v9_4_3_select_se_sh, 681 + .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 679 682 .read_wave_data = &gfx_v9_4_3_read_wave_data, 680 683 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 681 684 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, ··· 898 901 } 899 902 900 903 #define DEFAULT_SH_MEM_BASES (0x6000) 901 - static void gfx_v9_4_3_init_compute_vmid(struct amdgpu_device *adev, int xcc_id) 904 + static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 905 + int xcc_id) 902 906 { 903 907 int i; 904 908 uint32_t sh_mem_config; ··· 937 939 } 938 940 } 939 941 940 - static void gfx_v9_4_3_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 942 + static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 941 943 { 942 944 int vmid; 943 945 ··· 998 1000 mutex_unlock(&adev->srbm_mutex); 999 1001 1000 1002 for (i = 0; i < num_xcc; i++) { 1001 - gfx_v9_4_3_init_compute_vmid(adev, i); 1002 - gfx_v9_4_3_init_gds_vmid(adev, i); 1003 + gfx_v9_4_3_xcc_init_compute_vmid(adev, i); 1004 + gfx_v9_4_3_xcc_init_gds_vmid(adev, i); 1003 1005 } 1004 1006 } 1005 1007 1006 - static void gfx_v9_4_3_enable_save_restore_machine(struct amdgpu_device *adev, 1007 - int xcc_id) 1008 + static void 1009 + gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1010 + int xcc_id) 1008 1011 { 1009 1012 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1010 1013 } 1011 1014 1012 - static void gfx_v9_4_3_init_pg(struct amdgpu_device *adev, int xcc_id) 1015 + static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1013 1016 { 1014 1017 /* 1015 1018 * Rlc save restore list is workable since v2_1. 1016 1019 * And it's needed by gfxoff feature. 1017 1020 */ 1018 1021 if (adev->gfx.rlc.is_rlc_v2_1) 1019 - gfx_v9_4_3_enable_save_restore_machine(adev, xcc_id); 1022 + gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1020 1023 1021 1024 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 1022 1025 AMD_PG_SUPPORT_GFX_SMG | ··· 1030 1031 } 1031 1032 } 1032 1033 1033 - static void gfx_v9_4_3_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1034 + static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1034 1035 { 1035 1036 uint32_t data; 1036 1037 ··· 1039 1040 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1040 1041 } 1041 1042 1042 - static void gfx_v9_4_3_program_xcc_id(struct amdgpu_device *adev, int xcc_id) 1043 + static void gfx_v9_4_3_xcc_program_xcc_id(struct amdgpu_device *adev, 1044 + int xcc_id) 1043 1045 { 1044 1046 uint32_t tmp = 0; 1045 1047 int num_xcc; ··· 1074 1074 return true; 1075 1075 } 1076 1076 1077 - static void gfx_v9_4_3_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1077 + static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1078 1078 { 1079 1079 uint32_t data; 1080 1080 unsigned i; ··· 1091 1091 } 1092 1092 } 1093 1093 1094 - static void gfx_v9_4_3_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 1094 + static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1095 + int xcc_id) 1095 1096 { 1096 1097 uint32_t data; 1097 1098 ··· 1109 1108 return 0; 1110 1109 } 1111 1110 1112 - static void gfx_v9_4_3_wait_for_rlc_serdes(struct amdgpu_device *adev, 1113 - int xcc_id) 1111 + static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1112 + int xcc_id) 1114 1113 { 1115 1114 u32 i, j, k; 1116 1115 u32 mask; ··· 1118 1117 mutex_lock(&adev->grbm_idx_mutex); 1119 1118 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1120 1119 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1121 - gfx_v9_4_3_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 1120 + gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1121 + xcc_id); 1122 1122 for (k = 0; k < adev->usec_timeout; k++) { 1123 1123 if (RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1124 1124 break; 1125 1125 udelay(1); 1126 1126 } 1127 1127 if (k == adev->usec_timeout) { 1128 - gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 1129 - 0xffffffff, 0xffffffff, 1130 - xcc_id); 1128 + gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1129 + 0xffffffff, 1130 + 0xffffffff, xcc_id); 1131 1131 mutex_unlock(&adev->grbm_idx_mutex); 1132 1132 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1133 1133 i, j); ··· 1136 1134 } 1137 1135 } 1138 1136 } 1139 - gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, xcc_id); 1137 + gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1138 + xcc_id); 1140 1139 mutex_unlock(&adev->grbm_idx_mutex); 1141 1140 1142 1141 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | ··· 1151 1148 } 1152 1149 } 1153 1150 1154 - static void gfx_v9_4_3_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1155 - bool enable, int xcc_id) 1151 + static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1152 + bool enable, int xcc_id) 1156 1153 { 1157 1154 u32 tmp; 1158 1155 ··· 1174 1171 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1175 1172 for (i = 0; i < num_xcc; i++) { 1176 1173 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), RLC_CNTL, RLC_ENABLE_F32, 0); 1177 - gfx_v9_4_3_enable_gui_idle_interrupt(adev, false, i); 1178 - gfx_v9_4_3_wait_for_rlc_serdes(adev, i); 1174 + gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, i); 1175 + gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, i); 1179 1176 } 1180 1177 } 1181 1178 ··· 1206 1203 1207 1204 /* carrizo do enable cp interrupt after cp inited */ 1208 1205 if (!(adev->flags & AMD_IS_APU)) { 1209 - gfx_v9_4_3_enable_gui_idle_interrupt(adev, true, i); 1206 + gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, i); 1210 1207 udelay(50); 1211 1208 } 1212 1209 ··· 1229 1226 } 1230 1227 } 1231 1228 1232 - static int gfx_v9_4_3_rlc_load_microcode(struct amdgpu_device *adev, int xcc_id) 1229 + static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1230 + int xcc_id) 1233 1231 { 1234 1232 const struct rlc_firmware_header_v2_0 *hdr; 1235 1233 const __le32 *fw_data; ··· 1271 1267 /* disable CG */ 1272 1268 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_CGCG_CGLS_CTRL, 0); 1273 1269 1274 - gfx_v9_4_3_init_pg(adev, i); 1270 + gfx_v9_4_3_xcc_init_pg(adev, i); 1275 1271 1276 1272 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1277 1273 /* legacy rlc firmware loading */ 1278 - r = gfx_v9_4_3_rlc_load_microcode(adev, i); 1274 + r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, i); 1279 1275 if (r) 1280 1276 return r; 1281 1277 } ··· 1345 1341 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1346 1342 } 1347 1343 1348 - static void gfx_v9_4_3_cp_compute_enable(struct amdgpu_device *adev, 1349 - bool enable, int xcc_id) 1344 + static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1345 + bool enable, int xcc_id) 1350 1346 { 1351 1347 if (enable) { 1352 1348 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); ··· 1358 1354 udelay(50); 1359 1355 } 1360 1356 1361 - static int gfx_v9_4_3_cp_compute_load_microcode(struct amdgpu_device *adev, 1362 - int xcc_id) 1357 + static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1358 + int xcc_id) 1363 1359 { 1364 1360 const struct gfx_firmware_header_v1_0 *mec_hdr; 1365 1361 const __le32 *fw_data; ··· 1371 1367 if (!adev->gfx.mec_fw) 1372 1368 return -EINVAL; 1373 1369 1374 - gfx_v9_4_3_cp_compute_enable(adev, false, xcc_id); 1370 + gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1375 1371 1376 1372 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1377 1373 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); ··· 1407 1403 } 1408 1404 1409 1405 /* KIQ functions */ 1410 - static void gfx_v9_4_3_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1406 + static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1411 1407 { 1412 1408 uint32_t tmp; 1413 1409 struct amdgpu_device *adev = ring->adev; ··· 1562 1558 return 0; 1563 1559 } 1564 1560 1565 - static int gfx_v9_4_3_kiq_init_register(struct amdgpu_ring *ring, int xcc_id) 1561 + static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1562 + int xcc_id) 1566 1563 { 1567 1564 struct amdgpu_device *adev = ring->adev; 1568 1565 struct v9_mqd *mqd = ring->mqd_ptr; ··· 1668 1663 return 0; 1669 1664 } 1670 1665 1671 - static int gfx_v9_4_3_kiq_fini_register(struct amdgpu_ring *ring, int xcc_id) 1666 + static int gfx_v9_4_3_xcc_kiq_fini_register(struct amdgpu_ring *ring, 1667 + int xcc_id) 1672 1668 { 1673 1669 struct amdgpu_device *adev = ring->adev; 1674 1670 int j; ··· 1708 1702 return 0; 1709 1703 } 1710 1704 1711 - static int gfx_v9_4_3_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1705 + static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1712 1706 { 1713 1707 struct amdgpu_device *adev = ring->adev; 1714 1708 struct v9_mqd *mqd = ring->mqd_ptr; 1715 1709 struct v9_mqd *tmp_mqd; 1716 1710 1717 - gfx_v9_4_3_kiq_setting(ring, xcc_id); 1711 + gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 1718 1712 1719 1713 /* GPU could be in bad state during probe, driver trigger the reset 1720 1714 * after load the SMU, in this case , the mqd is not be initialized. ··· 1732 1726 amdgpu_ring_clear_ring(ring); 1733 1727 mutex_lock(&adev->srbm_mutex); 1734 1728 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1735 - gfx_v9_4_3_kiq_init_register(ring, xcc_id); 1729 + gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1736 1730 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1737 1731 mutex_unlock(&adev->srbm_mutex); 1738 1732 } else { ··· 1742 1736 mutex_lock(&adev->srbm_mutex); 1743 1737 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1744 1738 gfx_v9_4_3_mqd_init(ring); 1745 - gfx_v9_4_3_kiq_init_register(ring, xcc_id); 1739 + gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1746 1740 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1747 1741 mutex_unlock(&adev->srbm_mutex); 1748 1742 ··· 1753 1747 return 0; 1754 1748 } 1755 1749 1756 - static int gfx_v9_4_3_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1750 + static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1757 1751 { 1758 1752 struct amdgpu_device *adev = ring->adev; 1759 1753 struct v9_mqd *mqd = ring->mqd_ptr; ··· 1791 1785 return 0; 1792 1786 } 1793 1787 1794 - static int gfx_v9_4_3_kiq_resume(struct amdgpu_device *adev, int xcc_id) 1788 + static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 1795 1789 { 1796 1790 struct amdgpu_ring *ring; 1797 1791 int r; ··· 1808 1802 return r; 1809 1803 } 1810 1804 1811 - gfx_v9_4_3_kiq_init_queue(ring, xcc_id); 1805 + gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 1812 1806 amdgpu_bo_kunmap(ring->mqd_obj); 1813 1807 ring->mqd_ptr = NULL; 1814 1808 amdgpu_bo_unreserve(ring->mqd_obj); ··· 1816 1810 return 0; 1817 1811 } 1818 1812 1819 - static int gfx_v9_4_3_kcq_resume(struct amdgpu_device *adev, int xcc_id) 1813 + static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 1820 1814 { 1821 1815 struct amdgpu_ring *ring = NULL; 1822 1816 int r = 0, i; 1823 1817 1824 - gfx_v9_4_3_cp_compute_enable(adev, true, xcc_id); 1818 + gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 1825 1819 1826 1820 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1827 1821 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; ··· 1831 1825 goto done; 1832 1826 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1833 1827 if (!r) { 1834 - r = gfx_v9_4_3_kcq_init_queue(ring, xcc_id); 1828 + r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id); 1835 1829 amdgpu_bo_kunmap(ring->mqd_obj); 1836 1830 ring->mqd_ptr = NULL; 1837 1831 } ··· 1852 1846 1853 1847 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1854 1848 for (i = 0; i < num_xcc; i++) { 1855 - gfx_v9_4_3_enable_gui_idle_interrupt(adev, false, i); 1849 + gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, i); 1856 1850 1857 1851 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1858 - gfx_v9_4_3_disable_gpa_mode(adev, i); 1852 + gfx_v9_4_3_xcc_disable_gpa_mode(adev, i); 1859 1853 1860 - r = gfx_v9_4_3_cp_compute_load_microcode(adev, i); 1854 + r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, i); 1861 1855 if (r) 1862 1856 return r; 1863 1857 } ··· 1868 1862 adev, amdgpu_user_partt_mode); 1869 1863 1870 1864 /* set the virtual and physical id based on partition_mode */ 1871 - gfx_v9_4_3_program_xcc_id(adev, i); 1865 + gfx_v9_4_3_xcc_program_xcc_id(adev, i); 1872 1866 1873 - r = gfx_v9_4_3_kiq_resume(adev, i); 1867 + r = gfx_v9_4_3_xcc_kiq_resume(adev, i); 1874 1868 if (r) 1875 1869 return r; 1876 1870 1877 - r = gfx_v9_4_3_kcq_resume(adev, i); 1871 + r = gfx_v9_4_3_xcc_kcq_resume(adev, i); 1878 1872 if (r) 1879 1873 return r; 1880 1874 ··· 1885 1879 return r; 1886 1880 } 1887 1881 1888 - gfx_v9_4_3_enable_gui_idle_interrupt(adev, true, i); 1882 + gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, i); 1889 1883 } 1890 1884 1891 1885 return 0; 1892 1886 } 1893 1887 1894 - static void gfx_v9_4_3_cp_enable(struct amdgpu_device *adev, bool enable, 1895 - int xcc_id) 1888 + static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable, 1889 + int xcc_id) 1896 1890 { 1897 - gfx_v9_4_3_cp_compute_enable(adev, enable, xcc_id); 1891 + gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id); 1898 1892 } 1899 1893 1900 1894 static int gfx_v9_4_3_hw_init(void *handle) ··· 1938 1932 soc15_grbm_select(adev, adev->gfx.kiq[i].ring.me, 1939 1933 adev->gfx.kiq[i].ring.pipe, 1940 1934 adev->gfx.kiq[i].ring.queue, 0, GET_INST(GC, i)); 1941 - gfx_v9_4_3_kiq_fini_register(&adev->gfx.kiq[i].ring, i); 1935 + gfx_v9_4_3_xcc_kiq_fini_register(&adev->gfx.kiq[i].ring, 1936 + i); 1942 1937 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, i)); 1943 1938 mutex_unlock(&adev->srbm_mutex); 1944 1939 } 1945 1940 1946 - gfx_v9_4_3_cp_enable(adev, false, i); 1941 + gfx_v9_4_3_xcc_cp_enable(adev, false, i); 1947 1942 } 1948 1943 1949 1944 /* Skip suspend with A+A reset */ ··· 2031 2024 adev->gfx.rlc.funcs->stop(adev); 2032 2025 2033 2026 /* Disable MEC parsing/prefetching */ 2034 - gfx_v9_4_3_cp_compute_enable(adev, false, 0); 2027 + gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2035 2028 2036 2029 if (grbm_soft_reset) { 2037 2030 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); ··· 2118 2111 return 0; 2119 2112 } 2120 2113 2121 - static void gfx_v9_4_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2122 - bool enable, int xcc_id) 2114 + static void 2115 + gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2116 + bool enable, int xcc_id) 2123 2117 { 2124 2118 uint32_t data, def; 2125 2119 ··· 2188 2180 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2189 2181 } 2190 2182 2191 - static void gfx_v9_4_3_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2192 - bool enable, int xcc_id) 2183 + static void 2184 + gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2185 + bool enable, int xcc_id) 2193 2186 { 2194 2187 uint32_t def, data; 2195 2188 ··· 2241 2232 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2242 2233 } 2243 2234 2244 - static int gfx_v9_4_3_update_gfx_clock_gating(struct amdgpu_device *adev, 2245 - bool enable, int xcc_id) 2235 + static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2236 + bool enable, int xcc_id) 2246 2237 { 2247 2238 if (enable) { 2248 2239 /* CGCG/CGLS should be enabled after MGCG/MGLS 2249 2240 * === MGCG + MGLS === 2250 2241 */ 2251 - gfx_v9_4_3_update_medium_grain_clock_gating(adev, enable, xcc_id); 2242 + gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2243 + xcc_id); 2252 2244 /* === CGCG + CGLS === */ 2253 - gfx_v9_4_3_update_coarse_grain_clock_gating(adev, enable, xcc_id); 2245 + gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2246 + xcc_id); 2254 2247 } else { 2255 2248 /* CGCG/CGLS should be disabled before MGCG/MGLS 2256 2249 * === CGCG + CGLS === 2257 2250 */ 2258 - gfx_v9_4_3_update_coarse_grain_clock_gating(adev, enable, xcc_id); 2251 + gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2252 + xcc_id); 2259 2253 /* === MGCG + MGLS === */ 2260 - gfx_v9_4_3_update_medium_grain_clock_gating(adev, enable, xcc_id); 2254 + gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2255 + xcc_id); 2261 2256 } 2262 2257 return 0; 2263 2258 } 2264 2259 2265 2260 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2266 2261 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2267 - .set_safe_mode = gfx_v9_4_3_set_safe_mode, 2268 - .unset_safe_mode = gfx_v9_4_3_unset_safe_mode, 2262 + .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2263 + .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2269 2264 .init = gfx_v9_4_3_rlc_init, 2270 2265 .resume = gfx_v9_4_3_rlc_resume, 2271 2266 .stop = gfx_v9_4_3_rlc_stop, ··· 2298 2285 switch (adev->ip_versions[GC_HWIP][0]) { 2299 2286 case IP_VERSION(9, 4, 3): 2300 2287 for (i = 0; i < num_xcc; i++) 2301 - gfx_v9_4_3_update_gfx_clock_gating(adev, 2302 - state == AMD_CG_STATE_GATE, i); 2288 + gfx_v9_4_3_xcc_update_gfx_clock_gating( 2289 + adev, state == AMD_CG_STATE_GATE, i); 2303 2290 break; 2304 2291 default: 2305 2292 break; ··· 2566 2553 ref, mask); 2567 2554 } 2568 2555 2569 - static void gfx_v9_4_3_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 2570 - int me, int pipe, 2571 - enum amdgpu_interrupt_state state, 2572 - int xcc_id) 2556 + static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2557 + struct amdgpu_device *adev, int me, int pipe, 2558 + enum amdgpu_interrupt_state state, int xcc_id) 2573 2559 { 2574 2560 u32 mec_int_cntl, mec_int_cntl_reg; 2575 2561 ··· 2676 2664 for (i = 0; i < num_xcc; i++) { 2677 2665 switch (type) { 2678 2666 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 2679 - gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 1, 0, state, i); 2667 + gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2668 + adev, 1, 0, state, i); 2680 2669 break; 2681 2670 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 2682 - gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 1, 1, state, i); 2671 + gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2672 + adev, 1, 1, state, i); 2683 2673 break; 2684 2674 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 2685 - gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 1, 2, state, i); 2675 + gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2676 + adev, 1, 2, state, i); 2686 2677 break; 2687 2678 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 2688 - gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 1, 3, state, i); 2679 + gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2680 + adev, 1, 3, state, i); 2689 2681 break; 2690 2682 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 2691 - gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 2, 0, state, i); 2683 + gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2684 + adev, 2, 0, state, i); 2692 2685 break; 2693 2686 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 2694 - gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 2, 1, state, i); 2687 + gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2688 + adev, 2, 1, state, i); 2695 2689 break; 2696 2690 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 2697 - gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 2, 2, state, i); 2691 + gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2692 + adev, 2, 2, state, i); 2698 2693 break; 2699 2694 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 2700 - gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 2, 3, state, i); 2695 + gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2696 + adev, 2, 3, state, i); 2701 2697 break; 2702 2698 default: 2703 2699 break; ··· 3110 3090 mask = 1; 3111 3091 ao_bitmap = 0; 3112 3092 counter = 0; 3113 - gfx_v9_4_3_select_se_sh(adev, i, j, 0xffffffff, 0); 3093 + gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 0); 3114 3094 gfx_v9_4_3_set_user_cu_inactive_bitmap( 3115 3095 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 3116 3096 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev); ··· 3143 3123 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 3144 3124 } 3145 3125 } 3146 - gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3126 + gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3127 + 0); 3147 3128 mutex_unlock(&adev->grbm_idx_mutex); 3148 3129 3149 3130 cu_info->number = active_cu_number;