Merge tag 'soundwire-6.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire

+66 -28

drivers/soundwire/bus.c

··· 11 11 #include "bus.h" 12 12 #include "sysfs_local.h" 13 13 14 - static DEFINE_IDA(sdw_ida); 14 + static DEFINE_IDA(sdw_bus_ida); 15 + static DEFINE_IDA(sdw_peripheral_ida); 15 16 16 17 static int sdw_get_id(struct sdw_bus *bus) 17 18 { 18 - int rc = ida_alloc(&sdw_ida, GFP_KERNEL); 19 + int rc = ida_alloc(&sdw_bus_ida, GFP_KERNEL); 19 20 20 21 if (rc < 0) 21 22 return rc; ··· 76 75 77 76 /* 78 77 * Initialize multi_link flag 79 - * TODO: populate this flag by reading property from FW node 80 78 */ 81 79 bus->multi_link = false; 82 80 if (bus->ops->read_prop) { ··· 157 157 158 158 mutex_lock(&bus->bus_lock); 159 159 160 - if (slave->dev_num) /* clear dev_num if assigned */ 160 + if (slave->dev_num) { /* clear dev_num if assigned */ 161 161 clear_bit(slave->dev_num, bus->assigned); 162 - 162 + if (bus->dev_num_ida_min) 163 + ida_free(&sdw_peripheral_ida, slave->dev_num); 164 + } 163 165 list_del_init(&slave->node); 164 166 mutex_unlock(&bus->bus_lock); 165 167 ··· 181 179 sdw_master_device_del(bus); 182 180 183 181 sdw_bus_debugfs_exit(bus); 184 - ida_free(&sdw_ida, bus->id); 182 + ida_free(&sdw_bus_ida, bus->id); 185 183 } 186 184 EXPORT_SYMBOL(sdw_bus_master_delete); 187 185 ··· 673 671 { 674 672 int bit; 675 673 676 - bit = find_first_zero_bit(slave->bus->assigned, SDW_MAX_DEVICES); 677 - if (bit == SDW_MAX_DEVICES) { 678 - bit = -ENODEV; 679 - goto err; 674 + if (slave->bus->dev_num_ida_min) { 675 + bit = ida_alloc_range(&sdw_peripheral_ida, 676 + slave->bus->dev_num_ida_min, SDW_MAX_DEVICES, 677 + GFP_KERNEL); 678 + if (bit < 0) 679 + goto err; 680 + } else { 681 + bit = find_first_zero_bit(slave->bus->assigned, SDW_MAX_DEVICES); 682 + if (bit == SDW_MAX_DEVICES) { 683 + bit = -ENODEV; 684 + goto err; 685 + } 680 686 } 681 687 682 688 /* ··· 761 751 } 762 752 EXPORT_SYMBOL(sdw_extract_slave_id); 763 753 764 - static int sdw_program_device_num(struct sdw_bus *bus) 754 + static int sdw_program_device_num(struct sdw_bus *bus, bool *programmed) 765 755 { 766 756 u8 buf[SDW_NUM_DEV_ID_REGISTERS] = {0}; 767 757 struct sdw_slave *slave, *_s; ··· 770 760 bool found; 771 761 int count = 0, ret; 772 762 u64 addr; 763 + 764 + *programmed = false; 773 765 774 766 /* No Slave, so use raw xfer api */ 775 767 ret = sdw_fill_msg(&msg, NULL, SDW_SCP_DEVID_0, ··· 808 796 found = true; 809 797 810 798 /* 799 + * To prevent skipping state-machine stages don't 800 + * program a device until we've seen it UNATTACH. 801 + * Must return here because no other device on #0 802 + * can be detected until this one has been 803 + * assigned a device ID. 804 + */ 805 + if (slave->status != SDW_SLAVE_UNATTACHED) 806 + return 0; 807 + 808 + /* 811 809 * Assign a new dev_num to this Slave and 812 810 * not mark it present. It will be marked 813 811 * present after it reports ATTACHED on new ··· 830 808 ret); 831 809 return ret; 832 810 } 811 + 812 + *programmed = true; 833 813 834 814 break; 835 815 } ··· 872 848 mutex_lock(&bus->bus_lock); 873 849 874 850 dev_vdbg(bus->dev, 875 - "%s: changing status slave %d status %d new status %d\n", 876 - __func__, slave->dev_num, slave->status, status); 851 + "changing status slave %d status %d new status %d\n", 852 + slave->dev_num, slave->status, status); 877 853 878 854 if (status == SDW_SLAVE_UNATTACHED) { 879 855 dev_dbg(&slave->dev, 880 - "%s: initializing enumeration and init completion for Slave %d\n", 881 - __func__, slave->dev_num); 856 + "initializing enumeration and init completion for Slave %d\n", 857 + slave->dev_num); 882 858 883 859 init_completion(&slave->enumeration_complete); 884 860 init_completion(&slave->initialization_complete); ··· 886 862 } else if ((status == SDW_SLAVE_ATTACHED) && 887 863 (slave->status == SDW_SLAVE_UNATTACHED)) { 888 864 dev_dbg(&slave->dev, 889 - "%s: signaling enumeration completion for Slave %d\n", 890 - __func__, slave->dev_num); 865 + "signaling enumeration completion for Slave %d\n", 866 + slave->dev_num); 891 867 892 868 complete(&slave->enumeration_complete); 893 869 } ··· 1654 1630 port = buf2[0] & SDW_SCP_INTSTAT2_PORT4_10; 1655 1631 for_each_set_bit(bit, &port, 8) { 1656 1632 /* scp2 ports start from 4 */ 1657 - port_num = bit + 3; 1633 + port_num = bit + 4; 1658 1634 sdw_handle_port_interrupt(slave, 1659 1635 port_num, 1660 1636 &port_status[port_num]); ··· 1666 1642 port = buf2[1] & SDW_SCP_INTSTAT3_PORT11_14; 1667 1643 for_each_set_bit(bit, &port, 8) { 1668 1644 /* scp3 ports start from 11 */ 1669 - port_num = bit + 10; 1645 + port_num = bit + 11; 1670 1646 sdw_handle_port_interrupt(slave, 1671 1647 port_num, 1672 1648 &port_status[port_num]); ··· 1792 1768 { 1793 1769 enum sdw_slave_status prev_status; 1794 1770 struct sdw_slave *slave; 1795 - bool attached_initializing; 1771 + bool attached_initializing, id_programmed; 1796 1772 int i, ret = 0; 1797 1773 1798 1774 /* first check if any Slaves fell off the bus */ ··· 1813 1789 dev_warn(&slave->dev, "Slave %d state check1: UNATTACHED, status was %d\n", 1814 1790 i, slave->status); 1815 1791 sdw_modify_slave_status(slave, SDW_SLAVE_UNATTACHED); 1792 + 1793 + /* Ensure driver knows that peripheral unattached */ 1794 + ret = sdw_update_slave_status(slave, status[i]); 1795 + if (ret < 0) 1796 + dev_warn(&slave->dev, "Update Slave status failed:%d\n", ret); 1816 1797 } 1817 1798 } 1818 1799 1819 1800 if (status[0] == SDW_SLAVE_ATTACHED) { 1820 1801 dev_dbg(bus->dev, "Slave attached, programming device number\n"); 1821 - ret = sdw_program_device_num(bus); 1822 - if (ret < 0) 1823 - dev_err(bus->dev, "Slave attach failed: %d\n", ret); 1802 + 1824 1803 /* 1825 - * programming a device number will have side effects, 1826 - * so we deal with other devices at a later time 1804 + * Programming a device number will have side effects, 1805 + * so we deal with other devices at a later time. 1806 + * This relies on those devices reporting ATTACHED, which will 1807 + * trigger another call to this function. This will only 1808 + * happen if at least one device ID was programmed. 1809 + * Error returns from sdw_program_device_num() are currently 1810 + * ignored because there's no useful recovery that can be done. 1811 + * Returning the error here could result in the current status 1812 + * of other devices not being handled, because if no device IDs 1813 + * were programmed there's nothing to guarantee a status change 1814 + * to trigger another call to this function. 1827 1815 */ 1828 - return ret; 1816 + sdw_program_device_num(bus, &id_programmed); 1817 + if (id_programmed) 1818 + return 0; 1829 1819 } 1830 1820 1831 1821 /* Continue to check other slave statuses */ ··· 1908 1870 "Update Slave status failed:%d\n", ret); 1909 1871 if (attached_initializing) { 1910 1872 dev_dbg(&slave->dev, 1911 - "%s: signaling initialization completion for Slave %d\n", 1912 - __func__, slave->dev_num); 1873 + "signaling initialization completion for Slave %d\n", 1874 + slave->dev_num); 1913 1875 1914 1876 complete(&slave->initialization_complete); 1915 1877

+59 -51

drivers/soundwire/cadence_master.c

··· 544 544 return SDW_CMD_IGNORED; 545 545 } 546 546 547 - /* fill response */ 548 - for (i = 0; i < count; i++) 549 - msg->buf[i + offset] = FIELD_GET(CDNS_MCP_RESP_RDATA, cdns->response_buf[i]); 547 + if (msg->flags == SDW_MSG_FLAG_READ) { 548 + /* fill response */ 549 + for (i = 0; i < count; i++) 550 + msg->buf[i + offset] = FIELD_GET(CDNS_MCP_RESP_RDATA, 551 + cdns->response_buf[i]); 552 + } 550 553 551 554 return SDW_CMD_OK; 552 555 } ··· 569 566 } 570 567 571 568 base = CDNS_MCP_CMD_BASE; 572 - addr = msg->addr; 569 + addr = msg->addr + offset; 573 570 574 571 for (i = 0; i < count; i++) { 575 572 data = FIELD_PREP(CDNS_MCP_CMD_DEV_ADDR, msg->dev_num); ··· 708 705 for (i = 0; i < msg->len / CDNS_MCP_CMD_LEN; i++) { 709 706 ret = _cdns_xfer_msg(cdns, msg, cmd, i * CDNS_MCP_CMD_LEN, 710 707 CDNS_MCP_CMD_LEN, false); 711 - if (ret < 0) 712 - goto exit; 708 + if (ret != SDW_CMD_OK) 709 + return ret; 713 710 } 714 711 715 712 if (!(msg->len % CDNS_MCP_CMD_LEN)) 716 - goto exit; 713 + return SDW_CMD_OK; 717 714 718 - ret = _cdns_xfer_msg(cdns, msg, cmd, i * CDNS_MCP_CMD_LEN, 719 - msg->len % CDNS_MCP_CMD_LEN, false); 720 - 721 - exit: 722 - return ret; 715 + return _cdns_xfer_msg(cdns, msg, cmd, i * CDNS_MCP_CMD_LEN, 716 + msg->len % CDNS_MCP_CMD_LEN, false); 723 717 } 724 718 EXPORT_SYMBOL(cdns_xfer_msg); 725 719 ··· 790 790 enum sdw_slave_status status[SDW_MAX_DEVICES + 1]; 791 791 bool is_slave = false; 792 792 u32 mask; 793 + u32 val; 793 794 int i, set_status; 794 795 795 796 memset(status, 0, sizeof(status)); ··· 798 797 for (i = 0; i <= SDW_MAX_DEVICES; i++) { 799 798 mask = (slave_intstat >> (i * CDNS_MCP_SLAVE_STATUS_NUM)) & 800 799 CDNS_MCP_SLAVE_STATUS_BITS; 801 - if (!mask) 802 - continue; 803 800 804 - is_slave = true; 805 801 set_status = 0; 806 802 807 - if (mask & CDNS_MCP_SLAVE_INTSTAT_RESERVED) { 808 - status[i] = SDW_SLAVE_RESERVED; 809 - set_status++; 803 + if (mask) { 804 + is_slave = true; 805 + 806 + if (mask & CDNS_MCP_SLAVE_INTSTAT_RESERVED) { 807 + status[i] = SDW_SLAVE_RESERVED; 808 + set_status++; 809 + } 810 + 811 + if (mask & CDNS_MCP_SLAVE_INTSTAT_ATTACHED) { 812 + status[i] = SDW_SLAVE_ATTACHED; 813 + set_status++; 814 + } 815 + 816 + if (mask & CDNS_MCP_SLAVE_INTSTAT_ALERT) { 817 + status[i] = SDW_SLAVE_ALERT; 818 + set_status++; 819 + } 820 + 821 + if (mask & CDNS_MCP_SLAVE_INTSTAT_NPRESENT) { 822 + status[i] = SDW_SLAVE_UNATTACHED; 823 + set_status++; 824 + } 810 825 } 811 826 812 - if (mask & CDNS_MCP_SLAVE_INTSTAT_ATTACHED) { 813 - status[i] = SDW_SLAVE_ATTACHED; 814 - set_status++; 815 - } 816 - 817 - if (mask & CDNS_MCP_SLAVE_INTSTAT_ALERT) { 818 - status[i] = SDW_SLAVE_ALERT; 819 - set_status++; 820 - } 821 - 822 - if (mask & CDNS_MCP_SLAVE_INTSTAT_NPRESENT) { 823 - status[i] = SDW_SLAVE_UNATTACHED; 824 - set_status++; 825 - } 826 - 827 - /* first check if Slave reported multiple status */ 828 - if (set_status > 1) { 829 - u32 val; 830 - 831 - dev_warn_ratelimited(cdns->dev, 832 - "Slave %d reported multiple Status: %d\n", 833 - i, mask); 834 - 835 - /* check latest status extracted from PING commands */ 827 + /* 828 + * check that there was a single reported Slave status and when 829 + * there is not use the latest status extracted from PING commands 830 + */ 831 + if (set_status != 1) { 836 832 val = cdns_readl(cdns, CDNS_MCP_SLAVE_STAT); 837 833 val >>= (i * 2); 838 834 ··· 848 850 status[i] = SDW_SLAVE_RESERVED; 849 851 break; 850 852 } 851 - 852 - dev_warn_ratelimited(cdns->dev, 853 - "Slave %d status updated to %d\n", 854 - i, status[i]); 855 - 856 853 } 857 854 } 858 855 ··· 962 969 u32 device0_status; 963 970 int retry_count = 0; 964 971 972 + /* 973 + * Clear main interrupt first so we don't lose any assertions 974 + * that happen during this function. 975 + */ 976 + cdns_writel(cdns, CDNS_MCP_INTSTAT, CDNS_MCP_INT_SLAVE_MASK); 977 + 965 978 slave0 = cdns_readl(cdns, CDNS_MCP_SLAVE_INTSTAT0); 966 979 slave1 = cdns_readl(cdns, CDNS_MCP_SLAVE_INTSTAT1); 980 + 981 + /* 982 + * Clear the bits before handling so we don't lose any 983 + * bits that re-assert. 984 + */ 985 + cdns_writel(cdns, CDNS_MCP_SLAVE_INTSTAT0, slave0); 986 + cdns_writel(cdns, CDNS_MCP_SLAVE_INTSTAT1, slave1); 967 987 968 988 /* combine the two status */ 969 989 slave_intstat = ((u64)slave1 << 32) | slave0; ··· 985 979 986 980 update_status: 987 981 cdns_update_slave_status(cdns, slave_intstat); 988 - cdns_writel(cdns, CDNS_MCP_SLAVE_INTSTAT0, slave0); 989 - cdns_writel(cdns, CDNS_MCP_SLAVE_INTSTAT1, slave1); 990 982 991 983 /* 992 984 * When there is more than one peripheral per link, it's ··· 1001 997 * attention with PING commands. There is no need to check for 1002 998 * ALERTS since they are not allowed until a non-zero 1003 999 * device_number is assigned. 1000 + * 1001 + * Do not clear the INTSTAT0/1. While looping to enumerate devices on 1002 + * #0 there could be status changes on other devices - these must 1003 + * be kept in the INTSTAT so they can be handled when all #0 devices 1004 + * have been handled. 1004 1005 */ 1005 1006 1006 1007 device0_status = cdns_readl(cdns, CDNS_MCP_SLAVE_STAT); ··· 1025 1016 } 1026 1017 } 1027 1018 1028 - /* clear and unmask Slave interrupt now */ 1029 - cdns_writel(cdns, CDNS_MCP_INTSTAT, CDNS_MCP_INT_SLAVE_MASK); 1019 + /* unmask Slave interrupt now */ 1030 1020 cdns_updatel(cdns, CDNS_MCP_INTMASK, 1031 1021 CDNS_MCP_INT_SLAVE_MASK, CDNS_MCP_INT_SLAVE_MASK); 1032 1022

+27

drivers/soundwire/dmi-quirks.c

··· 55 55 {} 56 56 }; 57 57 58 + /* 59 + * The HP Omen 16-k0005TX does not expose the correct version of RT711 on link0 60 + * and does not expose a RT1316 on link3 61 + */ 62 + static const struct adr_remap hp_omen_16[] = { 63 + /* rt711-sdca on link0 */ 64 + { 65 + 0x000020025d071100ull, 66 + 0x000030025d071101ull 67 + }, 68 + /* rt1316-sdca on link3 */ 69 + { 70 + 0x000120025d071100ull, 71 + 0x000330025d131601ull 72 + }, 73 + {} 74 + }; 75 + 58 76 static const struct dmi_system_id adr_remap_quirk_table[] = { 77 + /* TGL devices */ 59 78 { 60 79 .matches = { 61 80 DMI_MATCH(DMI_SYS_VENDOR, "HP"), ··· 96 77 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0A3E") 97 78 }, 98 79 .driver_data = (void *)dell_sku_0A3E, 80 + }, 81 + /* ADL devices */ 82 + { 83 + .matches = { 84 + DMI_MATCH(DMI_SYS_VENDOR, "HP"), 85 + DMI_MATCH(DMI_PRODUCT_NAME, "OMEN by HP Gaming Laptop 16-k0xxx"), 86 + }, 87 + .driver_data = (void *)hp_omen_16, 99 88 }, 100 89 {} 101 90 };

+361 -373

drivers/soundwire/intel.c

··· 22 22 #include "bus.h" 23 23 #include "intel.h" 24 24 25 + /* IDA min selected to avoid conflicts with HDaudio/iDISP SDI values */ 26 + #define INTEL_DEV_NUM_IDA_MIN 4 27 + 25 28 #define INTEL_MASTER_SUSPEND_DELAY_MS 3000 26 29 #define INTEL_MASTER_RESET_ITERATIONS 10 27 30 ··· 138 135 if (!buf) 139 136 return -ENOMEM; 140 137 141 - links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0); 138 + links = intel_readl(s, SDW_SHIM_LCAP) & SDW_SHIM_LCAP_LCOUNT_MASK; 142 139 143 140 ret = scnprintf(buf, RD_BUF, "Register Value\n"); 144 141 ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n"); ··· 170 167 ret += intel_sprintf(s, false, buf, ret, 171 168 SDW_SHIM_PCMSYCHC(i, j)); 172 169 } 173 - ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n"); 170 + ret += scnprintf(buf + ret, RD_BUF - ret, "\n IOCTL, CTMCTL\n"); 174 171 175 - ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i)); 176 172 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i)); 177 173 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i)); 178 174 } ··· 260 258 /* 261 259 * shim ops 262 260 */ 263 - 264 - static int intel_link_power_up(struct sdw_intel *sdw) 265 - { 266 - unsigned int link_id = sdw->instance; 267 - void __iomem *shim = sdw->link_res->shim; 268 - u32 *shim_mask = sdw->link_res->shim_mask; 269 - struct sdw_bus *bus = &sdw->cdns.bus; 270 - struct sdw_master_prop *prop = &bus->prop; 271 - u32 spa_mask, cpa_mask; 272 - u32 link_control; 273 - int ret = 0; 274 - u32 syncprd; 275 - u32 sync_reg; 276 - 277 - mutex_lock(sdw->link_res->shim_lock); 278 - 279 - /* 280 - * The hardware relies on an internal counter, typically 4kHz, 281 - * to generate the SoundWire SSP - which defines a 'safe' 282 - * synchronization point between commands and audio transport 283 - * and allows for multi link synchronization. The SYNCPRD value 284 - * is only dependent on the oscillator clock provided to 285 - * the IP, so adjust based on _DSD properties reported in DSDT 286 - * tables. The values reported are based on either 24MHz 287 - * (CNL/CML) or 38.4 MHz (ICL/TGL+). 288 - */ 289 - if (prop->mclk_freq % 6000000) 290 - syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4; 291 - else 292 - syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24; 293 - 294 - if (!*shim_mask) { 295 - dev_dbg(sdw->cdns.dev, "%s: powering up all links\n", __func__); 296 - 297 - /* we first need to program the SyncPRD/CPU registers */ 298 - dev_dbg(sdw->cdns.dev, 299 - "%s: first link up, programming SYNCPRD\n", __func__); 300 - 301 - /* set SyncPRD period */ 302 - sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 303 - u32p_replace_bits(&sync_reg, syncprd, SDW_SHIM_SYNC_SYNCPRD); 304 - 305 - /* Set SyncCPU bit */ 306 - sync_reg |= SDW_SHIM_SYNC_SYNCCPU; 307 - intel_writel(shim, SDW_SHIM_SYNC, sync_reg); 308 - 309 - /* Link power up sequence */ 310 - link_control = intel_readl(shim, SDW_SHIM_LCTL); 311 - 312 - /* only power-up enabled links */ 313 - spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, sdw->link_res->link_mask); 314 - cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask); 315 - 316 - link_control |= spa_mask; 317 - 318 - ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask); 319 - if (ret < 0) { 320 - dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret); 321 - goto out; 322 - } 323 - 324 - /* SyncCPU will change once link is active */ 325 - ret = intel_wait_bit(shim, SDW_SHIM_SYNC, 326 - SDW_SHIM_SYNC_SYNCCPU, 0); 327 - if (ret < 0) { 328 - dev_err(sdw->cdns.dev, 329 - "Failed to set SHIM_SYNC: %d\n", ret); 330 - goto out; 331 - } 332 - } 333 - 334 - *shim_mask |= BIT(link_id); 335 - 336 - sdw->cdns.link_up = true; 337 - out: 338 - mutex_unlock(sdw->link_res->shim_lock); 339 - 340 - return ret; 341 - } 342 - 343 261 /* this needs to be called with shim_lock */ 344 262 static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw) 345 263 { ··· 311 389 /* at this point Integration Glue has full control of the I/Os */ 312 390 } 313 391 314 - static int intel_shim_init(struct sdw_intel *sdw, bool clock_stop) 392 + /* this needs to be called with shim_lock */ 393 + static void intel_shim_init(struct sdw_intel *sdw) 315 394 { 316 395 void __iomem *shim = sdw->link_res->shim; 317 396 unsigned int link_id = sdw->instance; 318 - int ret = 0; 319 397 u16 ioctl = 0, act = 0; 320 - 321 - mutex_lock(sdw->link_res->shim_lock); 322 398 323 399 /* Initialize Shim */ 324 400 ioctl |= SDW_SHIM_IOCTL_BKE; ··· 342 422 act |= SDW_SHIM_CTMCTL_DODS; 343 423 intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act); 344 424 usleep_range(10, 15); 425 + } 345 426 346 - mutex_unlock(sdw->link_res->shim_lock); 427 + static int intel_shim_check_wake(struct sdw_intel *sdw) 428 + { 429 + void __iomem *shim; 430 + u16 wake_sts; 347 431 348 - return ret; 432 + shim = sdw->link_res->shim; 433 + wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS); 434 + 435 + return wake_sts & BIT(sdw->instance); 349 436 } 350 437 351 438 static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable) ··· 381 454 mutex_unlock(sdw->link_res->shim_lock); 382 455 } 383 456 457 + static int intel_link_power_up(struct sdw_intel *sdw) 458 + { 459 + unsigned int link_id = sdw->instance; 460 + void __iomem *shim = sdw->link_res->shim; 461 + u32 *shim_mask = sdw->link_res->shim_mask; 462 + struct sdw_bus *bus = &sdw->cdns.bus; 463 + struct sdw_master_prop *prop = &bus->prop; 464 + u32 spa_mask, cpa_mask; 465 + u32 link_control; 466 + int ret = 0; 467 + u32 syncprd; 468 + u32 sync_reg; 469 + 470 + mutex_lock(sdw->link_res->shim_lock); 471 + 472 + /* 473 + * The hardware relies on an internal counter, typically 4kHz, 474 + * to generate the SoundWire SSP - which defines a 'safe' 475 + * synchronization point between commands and audio transport 476 + * and allows for multi link synchronization. The SYNCPRD value 477 + * is only dependent on the oscillator clock provided to 478 + * the IP, so adjust based on _DSD properties reported in DSDT 479 + * tables. The values reported are based on either 24MHz 480 + * (CNL/CML) or 38.4 MHz (ICL/TGL+). 481 + */ 482 + if (prop->mclk_freq % 6000000) 483 + syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4; 484 + else 485 + syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24; 486 + 487 + if (!*shim_mask) { 488 + dev_dbg(sdw->cdns.dev, "powering up all links\n"); 489 + 490 + /* we first need to program the SyncPRD/CPU registers */ 491 + dev_dbg(sdw->cdns.dev, 492 + "first link up, programming SYNCPRD\n"); 493 + 494 + /* set SyncPRD period */ 495 + sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 496 + u32p_replace_bits(&sync_reg, syncprd, SDW_SHIM_SYNC_SYNCPRD); 497 + 498 + /* Set SyncCPU bit */ 499 + sync_reg |= SDW_SHIM_SYNC_SYNCCPU; 500 + intel_writel(shim, SDW_SHIM_SYNC, sync_reg); 501 + 502 + /* Link power up sequence */ 503 + link_control = intel_readl(shim, SDW_SHIM_LCTL); 504 + 505 + /* only power-up enabled links */ 506 + spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, sdw->link_res->link_mask); 507 + cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask); 508 + 509 + link_control |= spa_mask; 510 + 511 + ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask); 512 + if (ret < 0) { 513 + dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret); 514 + goto out; 515 + } 516 + 517 + /* SyncCPU will change once link is active */ 518 + ret = intel_wait_bit(shim, SDW_SHIM_SYNC, 519 + SDW_SHIM_SYNC_SYNCCPU, 0); 520 + if (ret < 0) { 521 + dev_err(sdw->cdns.dev, 522 + "Failed to set SHIM_SYNC: %d\n", ret); 523 + goto out; 524 + } 525 + } 526 + 527 + *shim_mask |= BIT(link_id); 528 + 529 + sdw->cdns.link_up = true; 530 + 531 + intel_shim_init(sdw); 532 + 533 + out: 534 + mutex_unlock(sdw->link_res->shim_lock); 535 + 536 + return ret; 537 + } 538 + 384 539 static int intel_link_power_down(struct sdw_intel *sdw) 385 540 { 386 541 u32 link_control, spa_mask, cpa_mask; ··· 485 476 486 477 if (!*shim_mask) { 487 478 488 - dev_dbg(sdw->cdns.dev, "%s: powering down all links\n", __func__); 479 + dev_dbg(sdw->cdns.dev, "powering down all links\n"); 489 480 490 481 /* Link power down sequence */ 491 482 link_control = intel_readl(shim, SDW_SHIM_LCTL); ··· 1178 1169 1179 1170 static int intel_register_dai(struct sdw_intel *sdw) 1180 1171 { 1172 + struct sdw_cdns_stream_config config; 1181 1173 struct sdw_cdns *cdns = &sdw->cdns; 1182 1174 struct sdw_cdns_streams *stream; 1183 1175 struct snd_soc_dai_driver *dais; 1184 1176 int num_dai, ret, off = 0; 1177 + 1178 + /* Read the PDI config and initialize cadence PDI */ 1179 + intel_pdi_init(sdw, &config); 1180 + ret = sdw_cdns_pdi_init(cdns, config); 1181 + if (ret) 1182 + return ret; 1183 + 1184 + intel_pdi_ch_update(sdw); 1185 1185 1186 1186 /* DAIs are created based on total number of PDIs supported */ 1187 1187 num_dai = cdns->pcm.num_pdi; ··· 1219 1201 if (ret) 1220 1202 return ret; 1221 1203 1222 - return snd_soc_register_component(cdns->dev, &dai_component, 1223 - dais, num_dai); 1204 + return devm_snd_soc_register_component(cdns->dev, &dai_component, 1205 + dais, num_dai); 1206 + } 1207 + 1208 + static int intel_start_bus(struct sdw_intel *sdw) 1209 + { 1210 + struct device *dev = sdw->cdns.dev; 1211 + struct sdw_cdns *cdns = &sdw->cdns; 1212 + struct sdw_bus *bus = &cdns->bus; 1213 + int ret; 1214 + 1215 + ret = sdw_cdns_enable_interrupt(cdns, true); 1216 + if (ret < 0) { 1217 + dev_err(dev, "%s: cannot enable interrupts: %d\n", __func__, ret); 1218 + return ret; 1219 + } 1220 + 1221 + /* 1222 + * follow recommended programming flows to avoid timeouts when 1223 + * gsync is enabled 1224 + */ 1225 + if (bus->multi_link) 1226 + intel_shim_sync_arm(sdw); 1227 + 1228 + ret = sdw_cdns_init(cdns); 1229 + if (ret < 0) { 1230 + dev_err(dev, "%s: unable to initialize Cadence IP: %d\n", __func__, ret); 1231 + goto err_interrupt; 1232 + } 1233 + 1234 + ret = sdw_cdns_exit_reset(cdns); 1235 + if (ret < 0) { 1236 + dev_err(dev, "%s: unable to exit bus reset sequence: %d\n", __func__, ret); 1237 + goto err_interrupt; 1238 + } 1239 + 1240 + if (bus->multi_link) { 1241 + ret = intel_shim_sync_go(sdw); 1242 + if (ret < 0) { 1243 + dev_err(dev, "%s: sync go failed: %d\n", __func__, ret); 1244 + goto err_interrupt; 1245 + } 1246 + } 1247 + sdw_cdns_check_self_clearing_bits(cdns, __func__, 1248 + true, INTEL_MASTER_RESET_ITERATIONS); 1249 + 1250 + return 0; 1251 + 1252 + err_interrupt: 1253 + sdw_cdns_enable_interrupt(cdns, false); 1254 + return ret; 1255 + } 1256 + 1257 + static int intel_start_bus_after_reset(struct sdw_intel *sdw) 1258 + { 1259 + struct device *dev = sdw->cdns.dev; 1260 + struct sdw_cdns *cdns = &sdw->cdns; 1261 + struct sdw_bus *bus = &cdns->bus; 1262 + bool clock_stop0; 1263 + int status; 1264 + int ret; 1265 + 1266 + /* 1267 + * An exception condition occurs for the CLK_STOP_BUS_RESET 1268 + * case if one or more masters remain active. In this condition, 1269 + * all the masters are powered on for they are in the same power 1270 + * domain. Master can preserve its context for clock stop0, so 1271 + * there is no need to clear slave status and reset bus. 1272 + */ 1273 + clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns); 1274 + 1275 + if (!clock_stop0) { 1276 + 1277 + /* 1278 + * make sure all Slaves are tagged as UNATTACHED and 1279 + * provide reason for reinitialization 1280 + */ 1281 + 1282 + status = SDW_UNATTACH_REQUEST_MASTER_RESET; 1283 + sdw_clear_slave_status(bus, status); 1284 + 1285 + ret = sdw_cdns_enable_interrupt(cdns, true); 1286 + if (ret < 0) { 1287 + dev_err(dev, "cannot enable interrupts during resume\n"); 1288 + return ret; 1289 + } 1290 + 1291 + /* 1292 + * follow recommended programming flows to avoid 1293 + * timeouts when gsync is enabled 1294 + */ 1295 + if (bus->multi_link) 1296 + intel_shim_sync_arm(sdw); 1297 + 1298 + /* 1299 + * Re-initialize the IP since it was powered-off 1300 + */ 1301 + sdw_cdns_init(&sdw->cdns); 1302 + 1303 + } else { 1304 + ret = sdw_cdns_enable_interrupt(cdns, true); 1305 + if (ret < 0) { 1306 + dev_err(dev, "cannot enable interrupts during resume\n"); 1307 + return ret; 1308 + } 1309 + } 1310 + 1311 + ret = sdw_cdns_clock_restart(cdns, !clock_stop0); 1312 + if (ret < 0) { 1313 + dev_err(dev, "unable to restart clock during resume\n"); 1314 + goto err_interrupt; 1315 + } 1316 + 1317 + if (!clock_stop0) { 1318 + ret = sdw_cdns_exit_reset(cdns); 1319 + if (ret < 0) { 1320 + dev_err(dev, "unable to exit bus reset sequence during resume\n"); 1321 + goto err_interrupt; 1322 + } 1323 + 1324 + if (bus->multi_link) { 1325 + ret = intel_shim_sync_go(sdw); 1326 + if (ret < 0) { 1327 + dev_err(sdw->cdns.dev, "sync go failed during resume\n"); 1328 + goto err_interrupt; 1329 + } 1330 + } 1331 + } 1332 + sdw_cdns_check_self_clearing_bits(cdns, __func__, true, INTEL_MASTER_RESET_ITERATIONS); 1333 + 1334 + return 0; 1335 + 1336 + err_interrupt: 1337 + sdw_cdns_enable_interrupt(cdns, false); 1338 + return ret; 1339 + } 1340 + 1341 + static void intel_check_clock_stop(struct sdw_intel *sdw) 1342 + { 1343 + struct device *dev = sdw->cdns.dev; 1344 + bool clock_stop0; 1345 + 1346 + clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns); 1347 + if (!clock_stop0) 1348 + dev_err(dev, "%s: invalid configuration, clock was not stopped\n", __func__); 1349 + } 1350 + 1351 + static int intel_start_bus_after_clock_stop(struct sdw_intel *sdw) 1352 + { 1353 + struct device *dev = sdw->cdns.dev; 1354 + struct sdw_cdns *cdns = &sdw->cdns; 1355 + int ret; 1356 + 1357 + ret = sdw_cdns_enable_interrupt(cdns, true); 1358 + if (ret < 0) { 1359 + dev_err(dev, "%s: cannot enable interrupts: %d\n", __func__, ret); 1360 + return ret; 1361 + } 1362 + 1363 + ret = sdw_cdns_clock_restart(cdns, false); 1364 + if (ret < 0) { 1365 + dev_err(dev, "%s: unable to restart clock: %d\n", __func__, ret); 1366 + sdw_cdns_enable_interrupt(cdns, false); 1367 + return ret; 1368 + } 1369 + 1370 + sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime no_quirks", 1371 + true, INTEL_MASTER_RESET_ITERATIONS); 1372 + 1373 + return 0; 1374 + } 1375 + 1376 + static int intel_stop_bus(struct sdw_intel *sdw, bool clock_stop) 1377 + { 1378 + struct device *dev = sdw->cdns.dev; 1379 + struct sdw_cdns *cdns = &sdw->cdns; 1380 + bool wake_enable = false; 1381 + int ret; 1382 + 1383 + if (clock_stop) { 1384 + ret = sdw_cdns_clock_stop(cdns, true); 1385 + if (ret < 0) 1386 + dev_err(dev, "%s: cannot stop clock: %d\n", __func__, ret); 1387 + else 1388 + wake_enable = true; 1389 + } 1390 + 1391 + ret = sdw_cdns_enable_interrupt(cdns, false); 1392 + if (ret < 0) { 1393 + dev_err(dev, "%s: cannot disable interrupts: %d\n", __func__, ret); 1394 + return ret; 1395 + } 1396 + 1397 + ret = intel_link_power_down(sdw); 1398 + if (ret) { 1399 + dev_err(dev, "%s: Link power down failed: %d\n", __func__, ret); 1400 + return ret; 1401 + } 1402 + 1403 + intel_shim_wake(sdw, wake_enable); 1404 + 1405 + return 0; 1224 1406 } 1225 1407 1226 1408 static int sdw_master_read_intel_prop(struct sdw_bus *bus) ··· 1472 1254 } 1473 1255 1474 1256 static struct sdw_master_ops sdw_intel_ops = { 1475 - .read_prop = sdw_master_read_prop, 1257 + .read_prop = intel_prop_read, 1476 1258 .override_adr = sdw_dmi_override_adr, 1477 1259 .xfer_msg = cdns_xfer_msg, 1478 1260 .xfer_msg_defer = cdns_xfer_msg_defer, ··· 1482 1264 .post_bank_switch = intel_post_bank_switch, 1483 1265 .read_ping_status = cdns_read_ping_status, 1484 1266 }; 1485 - 1486 - static int intel_init(struct sdw_intel *sdw) 1487 - { 1488 - bool clock_stop; 1489 - 1490 - /* Initialize shim and controller */ 1491 - intel_link_power_up(sdw); 1492 - 1493 - clock_stop = sdw_cdns_is_clock_stop(&sdw->cdns); 1494 - 1495 - intel_shim_init(sdw, clock_stop); 1496 - 1497 - return 0; 1498 - } 1499 1267 1500 1268 /* 1501 1269 * probe and init (aux_dev_id argument is required by function prototype but not used) ··· 1512 1308 cdns->msg_count = 0; 1513 1309 1514 1310 bus->link_id = auxdev->id; 1311 + bus->dev_num_ida_min = INTEL_DEV_NUM_IDA_MIN; 1515 1312 1516 1313 sdw_cdns_probe(cdns); 1517 1314 1518 - /* Set property read ops */ 1519 - sdw_intel_ops.read_prop = intel_prop_read; 1315 + /* Set ops */ 1520 1316 bus->ops = &sdw_intel_ops; 1521 1317 1522 1318 /* set driver data, accessed by snd_soc_dai_get_drvdata() */ ··· 1549 1345 1550 1346 int intel_link_startup(struct auxiliary_device *auxdev) 1551 1347 { 1552 - struct sdw_cdns_stream_config config; 1553 1348 struct device *dev = &auxdev->dev; 1554 1349 struct sdw_cdns *cdns = auxiliary_get_drvdata(auxdev); 1555 1350 struct sdw_intel *sdw = cdns_to_intel(cdns); ··· 1569 1366 multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK); 1570 1367 if (!multi_link) { 1571 1368 dev_dbg(dev, "Multi-link is disabled\n"); 1572 - bus->multi_link = false; 1573 1369 } else { 1574 1370 /* 1575 1371 * hardware-based synchronization is required regardless ··· 1576 1374 * synchronization is gated by gsync when the multi-master 1577 1375 * mode is set. 1578 1376 */ 1579 - bus->multi_link = true; 1580 1377 bus->hw_sync_min_links = 1; 1581 1378 } 1379 + bus->multi_link = multi_link; 1582 1380 1583 1381 /* Initialize shim, controller */ 1584 - ret = intel_init(sdw); 1382 + ret = intel_link_power_up(sdw); 1585 1383 if (ret) 1586 1384 goto err_init; 1587 - 1588 - /* Read the PDI config and initialize cadence PDI */ 1589 - intel_pdi_init(sdw, &config); 1590 - ret = sdw_cdns_pdi_init(cdns, config); 1591 - if (ret) 1592 - goto err_init; 1593 - 1594 - intel_pdi_ch_update(sdw); 1595 - 1596 - ret = sdw_cdns_enable_interrupt(cdns, true); 1597 - if (ret < 0) { 1598 - dev_err(dev, "cannot enable interrupts\n"); 1599 - goto err_init; 1600 - } 1601 - 1602 - /* 1603 - * follow recommended programming flows to avoid timeouts when 1604 - * gsync is enabled 1605 - */ 1606 - if (multi_link) 1607 - intel_shim_sync_arm(sdw); 1608 - 1609 - ret = sdw_cdns_init(cdns); 1610 - if (ret < 0) { 1611 - dev_err(dev, "unable to initialize Cadence IP\n"); 1612 - goto err_interrupt; 1613 - } 1614 - 1615 - ret = sdw_cdns_exit_reset(cdns); 1616 - if (ret < 0) { 1617 - dev_err(dev, "unable to exit bus reset sequence\n"); 1618 - goto err_interrupt; 1619 - } 1620 - 1621 - if (multi_link) { 1622 - ret = intel_shim_sync_go(sdw); 1623 - if (ret < 0) { 1624 - dev_err(dev, "sync go failed: %d\n", ret); 1625 - goto err_interrupt; 1626 - } 1627 - } 1628 - sdw_cdns_check_self_clearing_bits(cdns, __func__, 1629 - true, INTEL_MASTER_RESET_ITERATIONS); 1630 1385 1631 1386 /* Register DAIs */ 1632 1387 ret = intel_register_dai(sdw); 1633 1388 if (ret) { 1634 1389 dev_err(dev, "DAI registration failed: %d\n", ret); 1635 - snd_soc_unregister_component(dev); 1636 - goto err_interrupt; 1390 + goto err_power_up; 1637 1391 } 1638 1392 1639 1393 intel_debugfs_init(sdw); 1394 + 1395 + /* start bus */ 1396 + ret = intel_start_bus(sdw); 1397 + if (ret) { 1398 + dev_err(dev, "bus start failed: %d\n", ret); 1399 + goto err_power_up; 1400 + } 1640 1401 1641 1402 /* Enable runtime PM */ 1642 1403 if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME)) { ··· 1645 1480 sdw->startup_done = true; 1646 1481 return 0; 1647 1482 1648 - err_interrupt: 1649 - sdw_cdns_enable_interrupt(cdns, false); 1483 + err_power_up: 1484 + intel_link_power_down(sdw); 1650 1485 err_init: 1651 1486 return ret; 1652 1487 } 1653 1488 1654 1489 static void intel_link_remove(struct auxiliary_device *auxdev) 1655 1490 { 1656 - struct device *dev = &auxdev->dev; 1657 1491 struct sdw_cdns *cdns = auxiliary_get_drvdata(auxdev); 1658 1492 struct sdw_intel *sdw = cdns_to_intel(cdns); 1659 1493 struct sdw_bus *bus = &cdns->bus; ··· 1665 1501 if (!bus->prop.hw_disabled) { 1666 1502 intel_debugfs_exit(sdw); 1667 1503 sdw_cdns_enable_interrupt(cdns, false); 1668 - snd_soc_unregister_component(dev); 1669 1504 } 1670 1505 sdw_bus_master_delete(bus); 1671 1506 } ··· 1674 1511 struct device *dev = &auxdev->dev; 1675 1512 struct sdw_intel *sdw; 1676 1513 struct sdw_bus *bus; 1677 - void __iomem *shim; 1678 - u16 wake_sts; 1679 1514 1680 1515 sdw = auxiliary_get_drvdata(auxdev); 1681 1516 bus = &sdw->cdns.bus; ··· 1684 1523 return 0; 1685 1524 } 1686 1525 1687 - shim = sdw->link_res->shim; 1688 - wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS); 1689 - 1690 - if (!(wake_sts & BIT(sdw->instance))) 1526 + if (!intel_shim_check_wake(sdw)) 1691 1527 return 0; 1692 1528 1693 1529 /* disable WAKEEN interrupt ASAP to prevent interrupt flood */ ··· 1712 1554 struct sdw_slave *slave = dev_to_sdw_dev(dev); 1713 1555 1714 1556 if (!slave->probed) { 1715 - dev_dbg(dev, "%s: skipping device, no probed driver\n", __func__); 1557 + dev_dbg(dev, "skipping device, no probed driver\n"); 1716 1558 return 0; 1717 1559 } 1718 1560 if (!slave->dev_num_sticky) { 1719 - dev_dbg(dev, "%s: skipping device, never detected on bus\n", __func__); 1561 + dev_dbg(dev, "skipping device, never detected on bus\n"); 1720 1562 return 0; 1721 1563 } 1722 1564 ··· 1802 1644 } 1803 1645 1804 1646 if (pm_runtime_suspended(dev)) { 1805 - dev_dbg(dev, "%s: pm_runtime status: suspended\n", __func__); 1647 + dev_dbg(dev, "pm_runtime status: suspended\n"); 1806 1648 1807 1649 clock_stop_quirks = sdw->link_res->clock_stop_quirks; 1808 1650 ··· 1823 1665 return 0; 1824 1666 } 1825 1667 1826 - ret = sdw_cdns_enable_interrupt(cdns, false); 1668 + ret = intel_stop_bus(sdw, false); 1827 1669 if (ret < 0) { 1828 - dev_err(dev, "cannot disable interrupts on suspend\n"); 1670 + dev_err(dev, "%s: cannot stop bus: %d\n", __func__, ret); 1829 1671 return ret; 1830 1672 } 1831 - 1832 - ret = intel_link_power_down(sdw); 1833 - if (ret) { 1834 - dev_err(dev, "Link power down failed: %d\n", ret); 1835 - return ret; 1836 - } 1837 - 1838 - intel_shim_wake(sdw, false); 1839 1673 1840 1674 return 0; 1841 1675 } ··· 1849 1699 clock_stop_quirks = sdw->link_res->clock_stop_quirks; 1850 1700 1851 1701 if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) { 1852 - 1853 - ret = sdw_cdns_enable_interrupt(cdns, false); 1702 + ret = intel_stop_bus(sdw, false); 1854 1703 if (ret < 0) { 1855 - dev_err(dev, "cannot disable interrupts on suspend\n"); 1704 + dev_err(dev, "%s: cannot stop bus during teardown: %d\n", 1705 + __func__, ret); 1856 1706 return ret; 1857 1707 } 1858 - 1859 - ret = intel_link_power_down(sdw); 1860 - if (ret) { 1861 - dev_err(dev, "Link power down failed: %d\n", ret); 1862 - return ret; 1863 - } 1864 - 1865 - intel_shim_wake(sdw, false); 1866 - 1867 - } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET || 1868 - !clock_stop_quirks) { 1869 - bool wake_enable = true; 1870 - 1871 - ret = sdw_cdns_clock_stop(cdns, true); 1708 + } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET || !clock_stop_quirks) { 1709 + ret = intel_stop_bus(sdw, true); 1872 1710 if (ret < 0) { 1873 - dev_err(dev, "cannot enable clock stop on suspend\n"); 1874 - wake_enable = false; 1875 - } 1876 - 1877 - ret = sdw_cdns_enable_interrupt(cdns, false); 1878 - if (ret < 0) { 1879 - dev_err(dev, "cannot disable interrupts on suspend\n"); 1711 + dev_err(dev, "%s: cannot stop bus during clock_stop: %d\n", 1712 + __func__, ret); 1880 1713 return ret; 1881 1714 } 1882 - 1883 - ret = intel_link_power_down(sdw); 1884 - if (ret) { 1885 - dev_err(dev, "Link power down failed: %d\n", ret); 1886 - return ret; 1887 - } 1888 - 1889 - intel_shim_wake(sdw, wake_enable); 1890 1715 } else { 1891 1716 dev_err(dev, "%s clock_stop_quirks %x unsupported\n", 1892 1717 __func__, clock_stop_quirks); ··· 1877 1752 struct sdw_intel *sdw = cdns_to_intel(cdns); 1878 1753 struct sdw_bus *bus = &cdns->bus; 1879 1754 int link_flags; 1880 - bool multi_link; 1881 1755 int ret; 1882 1756 1883 1757 if (bus->prop.hw_disabled || !sdw->startup_done) { ··· 1886 1762 } 1887 1763 1888 1764 link_flags = md_flags >> (bus->link_id * 8); 1889 - multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK); 1890 1765 1891 1766 if (pm_runtime_suspended(dev)) { 1892 - dev_dbg(dev, "%s: pm_runtime status was suspended, forcing active\n", __func__); 1767 + dev_dbg(dev, "pm_runtime status was suspended, forcing active\n"); 1893 1768 1894 1769 /* follow required sequence from runtime_pm.rst */ 1895 1770 pm_runtime_disable(dev); ··· 1902 1779 pm_runtime_idle(dev); 1903 1780 } 1904 1781 1905 - ret = intel_init(sdw); 1782 + ret = intel_link_power_up(sdw); 1906 1783 if (ret) { 1907 1784 dev_err(dev, "%s failed: %d\n", __func__, ret); 1908 1785 return ret; ··· 1914 1791 */ 1915 1792 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET); 1916 1793 1917 - ret = sdw_cdns_enable_interrupt(cdns, true); 1794 + ret = intel_start_bus(sdw); 1918 1795 if (ret < 0) { 1919 - dev_err(dev, "cannot enable interrupts during resume\n"); 1796 + dev_err(dev, "cannot start bus during resume\n"); 1797 + intel_link_power_down(sdw); 1920 1798 return ret; 1921 1799 } 1922 - 1923 - /* 1924 - * follow recommended programming flows to avoid timeouts when 1925 - * gsync is enabled 1926 - */ 1927 - if (multi_link) 1928 - intel_shim_sync_arm(sdw); 1929 - 1930 - ret = sdw_cdns_init(&sdw->cdns); 1931 - if (ret < 0) { 1932 - dev_err(dev, "unable to initialize Cadence IP during resume\n"); 1933 - return ret; 1934 - } 1935 - 1936 - ret = sdw_cdns_exit_reset(cdns); 1937 - if (ret < 0) { 1938 - dev_err(dev, "unable to exit bus reset sequence during resume\n"); 1939 - return ret; 1940 - } 1941 - 1942 - if (multi_link) { 1943 - ret = intel_shim_sync_go(sdw); 1944 - if (ret < 0) { 1945 - dev_err(dev, "sync go failed during resume\n"); 1946 - return ret; 1947 - } 1948 - } 1949 - sdw_cdns_check_self_clearing_bits(cdns, __func__, 1950 - true, INTEL_MASTER_RESET_ITERATIONS); 1951 1800 1952 1801 /* 1953 1802 * after system resume, the pm_runtime suspend() may kick in ··· 1933 1838 */ 1934 1839 pm_runtime_mark_last_busy(dev); 1935 1840 1936 - return ret; 1841 + return 0; 1937 1842 } 1938 1843 1939 1844 static int __maybe_unused intel_resume_runtime(struct device *dev) ··· 1942 1847 struct sdw_intel *sdw = cdns_to_intel(cdns); 1943 1848 struct sdw_bus *bus = &cdns->bus; 1944 1849 u32 clock_stop_quirks; 1945 - bool clock_stop0; 1946 - int link_flags; 1947 - bool multi_link; 1948 - int status; 1949 1850 int ret; 1950 1851 1951 1852 if (bus->prop.hw_disabled || !sdw->startup_done) { ··· 1953 1862 /* unconditionally disable WAKEEN interrupt */ 1954 1863 intel_shim_wake(sdw, false); 1955 1864 1956 - link_flags = md_flags >> (bus->link_id * 8); 1957 - multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK); 1958 - 1959 1865 clock_stop_quirks = sdw->link_res->clock_stop_quirks; 1960 1866 1961 1867 if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) { 1962 - ret = intel_init(sdw); 1868 + ret = intel_link_power_up(sdw); 1963 1869 if (ret) { 1964 - dev_err(dev, "%s failed: %d\n", __func__, ret); 1870 + dev_err(dev, "%s: power_up failed after teardown: %d\n", __func__, ret); 1965 1871 return ret; 1966 1872 } 1967 1873 ··· 1968 1880 */ 1969 1881 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET); 1970 1882 1971 - ret = sdw_cdns_enable_interrupt(cdns, true); 1883 + ret = intel_start_bus(sdw); 1972 1884 if (ret < 0) { 1973 - dev_err(dev, "cannot enable interrupts during resume\n"); 1885 + dev_err(dev, "%s: cannot start bus after teardown: %d\n", __func__, ret); 1886 + intel_link_power_down(sdw); 1974 1887 return ret; 1975 1888 } 1976 1889 1977 - /* 1978 - * follow recommended programming flows to avoid 1979 - * timeouts when gsync is enabled 1980 - */ 1981 - if (multi_link) 1982 - intel_shim_sync_arm(sdw); 1983 - 1984 - ret = sdw_cdns_init(&sdw->cdns); 1985 - if (ret < 0) { 1986 - dev_err(dev, "unable to initialize Cadence IP during resume\n"); 1987 - return ret; 1988 - } 1989 - 1990 - ret = sdw_cdns_exit_reset(cdns); 1991 - if (ret < 0) { 1992 - dev_err(dev, "unable to exit bus reset sequence during resume\n"); 1993 - return ret; 1994 - } 1995 - 1996 - if (multi_link) { 1997 - ret = intel_shim_sync_go(sdw); 1998 - if (ret < 0) { 1999 - dev_err(dev, "sync go failed during resume\n"); 2000 - return ret; 2001 - } 2002 - } 2003 - sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime TEARDOWN", 2004 - true, INTEL_MASTER_RESET_ITERATIONS); 2005 1890 2006 1891 } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) { 2007 - ret = intel_init(sdw); 1892 + ret = intel_link_power_up(sdw); 2008 1893 if (ret) { 2009 - dev_err(dev, "%s failed: %d\n", __func__, ret); 1894 + dev_err(dev, "%s: power_up failed after bus reset: %d\n", __func__, ret); 2010 1895 return ret; 2011 1896 } 2012 1897 2013 - /* 2014 - * An exception condition occurs for the CLK_STOP_BUS_RESET 2015 - * case if one or more masters remain active. In this condition, 2016 - * all the masters are powered on for they are in the same power 2017 - * domain. Master can preserve its context for clock stop0, so 2018 - * there is no need to clear slave status and reset bus. 2019 - */ 2020 - clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns); 2021 - 2022 - if (!clock_stop0) { 2023 - 2024 - /* 2025 - * make sure all Slaves are tagged as UNATTACHED and 2026 - * provide reason for reinitialization 2027 - */ 2028 - 2029 - status = SDW_UNATTACH_REQUEST_MASTER_RESET; 2030 - sdw_clear_slave_status(bus, status); 2031 - 2032 - ret = sdw_cdns_enable_interrupt(cdns, true); 2033 - if (ret < 0) { 2034 - dev_err(dev, "cannot enable interrupts during resume\n"); 2035 - return ret; 2036 - } 2037 - 2038 - /* 2039 - * follow recommended programming flows to avoid 2040 - * timeouts when gsync is enabled 2041 - */ 2042 - if (multi_link) 2043 - intel_shim_sync_arm(sdw); 2044 - 2045 - /* 2046 - * Re-initialize the IP since it was powered-off 2047 - */ 2048 - sdw_cdns_init(&sdw->cdns); 2049 - 2050 - } else { 2051 - ret = sdw_cdns_enable_interrupt(cdns, true); 2052 - if (ret < 0) { 2053 - dev_err(dev, "cannot enable interrupts during resume\n"); 2054 - return ret; 2055 - } 2056 - } 2057 - 2058 - ret = sdw_cdns_clock_restart(cdns, !clock_stop0); 1898 + ret = intel_start_bus_after_reset(sdw); 2059 1899 if (ret < 0) { 2060 - dev_err(dev, "unable to restart clock during resume\n"); 1900 + dev_err(dev, "%s: cannot start bus after reset: %d\n", __func__, ret); 1901 + intel_link_power_down(sdw); 2061 1902 return ret; 2062 1903 } 2063 - 2064 - if (!clock_stop0) { 2065 - ret = sdw_cdns_exit_reset(cdns); 2066 - if (ret < 0) { 2067 - dev_err(dev, "unable to exit bus reset sequence during resume\n"); 2068 - return ret; 2069 - } 2070 - 2071 - if (multi_link) { 2072 - ret = intel_shim_sync_go(sdw); 2073 - if (ret < 0) { 2074 - dev_err(sdw->cdns.dev, "sync go failed during resume\n"); 2075 - return ret; 2076 - } 2077 - } 2078 - } 2079 - sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime BUS_RESET", 2080 - true, INTEL_MASTER_RESET_ITERATIONS); 2081 - 2082 1904 } else if (!clock_stop_quirks) { 2083 1905 2084 - clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns); 2085 - if (!clock_stop0) 2086 - dev_err(dev, "%s invalid configuration, clock was not stopped", __func__); 1906 + intel_check_clock_stop(sdw); 2087 1907 2088 - ret = intel_init(sdw); 1908 + ret = intel_link_power_up(sdw); 2089 1909 if (ret) { 2090 - dev_err(dev, "%s failed: %d\n", __func__, ret); 1910 + dev_err(dev, "%s: power_up failed: %d\n", __func__, ret); 2091 1911 return ret; 2092 1912 } 2093 1913 2094 - ret = sdw_cdns_enable_interrupt(cdns, true); 1914 + ret = intel_start_bus_after_clock_stop(sdw); 2095 1915 if (ret < 0) { 2096 - dev_err(dev, "cannot enable interrupts during resume\n"); 1916 + dev_err(dev, "%s: cannot start bus after clock stop: %d\n", __func__, ret); 1917 + intel_link_power_down(sdw); 2097 1918 return ret; 2098 1919 } 2099 - 2100 - ret = sdw_cdns_clock_restart(cdns, false); 2101 - if (ret < 0) { 2102 - dev_err(dev, "unable to resume master during resume\n"); 2103 - return ret; 2104 - } 2105 - 2106 - sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime no_quirks", 2107 - true, INTEL_MASTER_RESET_ITERATIONS); 2108 1920 } else { 2109 - dev_err(dev, "%s clock_stop_quirks %x unsupported\n", 1921 + dev_err(dev, "%s: clock_stop_quirks %x unsupported\n", 2110 1922 __func__, clock_stop_quirks); 2111 1923 ret = -EINVAL; 2112 1924 }

+1 -1

drivers/soundwire/intel_init.c

··· 306 306 307 307 /* Check SNDWLCAP.LCOUNT */ 308 308 caps = ioread32(ctx->mmio_base + ctx->shim_base + SDW_SHIM_LCAP); 309 - caps &= GENMASK(2, 0); 309 + caps &= SDW_SHIM_LCAP_LCOUNT_MASK; 310 310 311 311 /* Check HW supported vs property value */ 312 312 if (caps < ctx->count) {

+4 -5

drivers/soundwire/qcom.c

··· 420 420 421 421 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); 422 422 423 - for (dev_num = 0; dev_num <= SDW_MAX_DEVICES; dev_num++) { 423 + for (dev_num = 1; dev_num <= SDW_MAX_DEVICES; dev_num++) { 424 424 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ)); 425 425 426 426 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) { ··· 440 440 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); 441 441 ctrl->slave_status = val; 442 442 443 - for (i = 0; i <= SDW_MAX_DEVICES; i++) { 443 + for (i = 1; i <= SDW_MAX_DEVICES; i++) { 444 444 u32 s; 445 445 446 446 s = (val >> (i * 2)); ··· 573 573 break; 574 574 case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED: 575 575 case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS: 576 - dev_err_ratelimited(swrm->dev, "%s: SWR new slave attached\n", 577 - __func__); 576 + dev_dbg_ratelimited(swrm->dev, "SWR new slave attached\n"); 578 577 swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status); 579 578 if (swrm->slave_status == slave_status) { 580 - dev_err(swrm->dev, "Slave status not changed %x\n", 579 + dev_dbg(swrm->dev, "Slave status not changed %x\n", 581 580 slave_status); 582 581 } else { 583 582 qcom_swrm_get_device_status(swrm);

+4

include/linux/soundwire/sdw.h

··· 892 892 * meaningful if multi_link is set. If set to 1, hardware-based 893 893 * synchronization will be used even if a stream only uses a single 894 894 * SoundWire segment. 895 + * @dev_num_ida_min: if set, defines the minimum values for the IDA 896 + * used to allocate system-unique device numbers. This value needs to be 897 + * identical across all SoundWire bus in the system. 895 898 */ 896 899 struct sdw_bus { 897 900 struct device *dev; ··· 919 916 u32 bank_switch_timeout; 920 917 bool multi_link; 921 918 int hw_sync_min_links; 919 + int dev_num_ida_min; 922 920 }; 923 921 924 922 int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent,

+38 -25

include/linux/soundwire/sdw_intel.h

··· 15 15 #define SDW_LINK_SIZE 0x10000 16 16 17 17 /* Intel SHIM Registers Definition */ 18 + /* LCAP */ 18 19 #define SDW_SHIM_LCAP 0x0 20 + #define SDW_SHIM_LCAP_LCOUNT_MASK GENMASK(2, 0) 21 + 22 + /* LCTL */ 19 23 #define SDW_SHIM_LCTL 0x4 20 - #define SDW_SHIM_IPPTR 0x8 21 - #define SDW_SHIM_SYNC 0xC 22 - 23 - #define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x)) 24 - #define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x)) 25 - #define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x)) 26 - #define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x)) 27 - #define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x)) 28 - #define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x)) 29 - 30 - #define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y))) 31 - #define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y))) 32 - #define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x)) 33 - #define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x)) 34 - #define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x)) 35 - 36 - #define SDW_SHIM_WAKEEN 0x190 37 - #define SDW_SHIM_WAKESTS 0x192 38 24 39 25 #define SDW_SHIM_LCTL_SPA BIT(0) 40 26 #define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0) 41 27 #define SDW_SHIM_LCTL_CPA BIT(8) 42 28 #define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8) 29 + 30 + /* SYNC */ 31 + #define SDW_SHIM_SYNC 0xC 43 32 44 33 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1) 45 34 #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1) ··· 38 49 #define SDW_SHIM_SYNC_CMDSYNC BIT(16) 39 50 #define SDW_SHIM_SYNC_SYNCGO BIT(24) 40 51 52 + /* Control stream capabililities and channel mask */ 53 + #define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x)) 54 + #define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x)) 55 + #define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x)) 56 + #define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x)) 57 + #define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x)) 58 + 59 + /* PCM Stream capabilities */ 60 + #define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x)) 61 + 41 62 #define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0) 42 63 #define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4) 43 64 #define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8) 65 + 66 + /* PCM Stream Channel Map */ 67 + #define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y))) 68 + 69 + /* PCM Stream Channel Count */ 70 + #define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y))) 44 71 45 72 #define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0) 46 73 #define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4) 47 74 #define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8) 48 75 #define SDW_SHIM_PCMSYCM_DIR BIT(15) 49 76 50 - #define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0) 51 - #define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4) 52 - #define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8) 53 - #define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13) 77 + /* IO control */ 78 + #define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x)) 54 79 55 80 #define SDW_SHIM_IOCTL_MIF BIT(0) 56 81 #define SDW_SHIM_IOCTL_CO BIT(1) ··· 76 73 #define SDW_SHIM_IOCTL_CIBD BIT(8) 77 74 #define SDW_SHIM_IOCTL_DIBD BIT(9) 78 75 76 + /* Wake Enable*/ 77 + #define SDW_SHIM_WAKEEN 0x190 78 + 79 + #define SDW_SHIM_WAKEEN_ENABLE BIT(0) 80 + 81 + /* Wake Status */ 82 + #define SDW_SHIM_WAKESTS 0x192 83 + 84 + #define SDW_SHIM_WAKESTS_STATUS BIT(0) 85 + 86 + /* AC Timing control */ 87 + #define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x)) 88 + 79 89 #define SDW_SHIM_CTMCTL_DACTQE BIT(0) 80 90 #define SDW_SHIM_CTMCTL_DODS BIT(1) 81 91 #define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3) 82 - 83 - #define SDW_SHIM_WAKEEN_ENABLE BIT(0) 84 - #define SDW_SHIM_WAKESTS_STATUS BIT(0) 85 92 86 93 /* Intel ALH Register definitions */ 87 94 #define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))

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