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drm/amdgpu: expose the minimum shader/memory clock frequency

Otherwise, some UMD tools will treate them as 0 at default while
actually they are not.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Evan Quan and committed by
Alex Deucher
88347fa1 5cfd9784

+10 -2
+8 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
··· 785 785 if (adev->pm.dpm_enabled) { 786 786 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 787 787 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 788 + dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10; 789 + dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10; 788 790 } else { 789 - dev_info->max_engine_clock = adev->clock.default_sclk * 10; 790 - dev_info->max_memory_clock = adev->clock.default_mclk * 10; 791 + dev_info->max_engine_clock = 792 + dev_info->min_engine_clock = 793 + adev->clock.default_sclk * 10; 794 + dev_info->max_memory_clock = 795 + dev_info->min_memory_clock = 796 + adev->clock.default_mclk * 10; 791 797 } 792 798 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 793 799 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
+2
include/uapi/drm/amdgpu_drm.h
··· 1111 1111 __u32 pa_sc_tile_steering_override; 1112 1112 /* disabled TCCs */ 1113 1113 __u64 tcc_disabled_mask; 1114 + __u64 min_engine_clock; 1115 + __u64 min_memory_clock; 1114 1116 }; 1115 1117 1116 1118 struct drm_amdgpu_info_hw_ip {