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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge branch 'net-mlx5-misc-changes-2025-07-21'
Tariq Toukan says:
====================
net/mlx5: misc changes 2025-07-21
This series by Lama contains misc enhancements to the SHAMPO parameters.
====================
Link: https://patch.msgid.link/1753081999-326247-1-git-send-email-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+39
-51
+5
-5
drivers/net/ethernet/mellanox/mlx5/core/en.h
+5
-5
drivers/net/ethernet/mellanox/mlx5/core/en.h
···
84
84
#define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9)
85
85
#define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE)
86
86
#define MLX5E_SHAMPO_LOG_WQ_HEADER_PER_PAGE (PAGE_SHIFT - MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE)
87
-
#define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64)
88
-
#define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024)
89
-
#define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096)
87
+
#define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE_SHIFT (6)
88
+
#define MLX5E_SHAMPO_WQ_RESRV_SIZE_BASE_SHIFT (12)
89
+
#define MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE (16)
90
+
#define MLX5E_SHAMPO_WQ_RESRV_SIZE BIT(MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE)
90
91
91
92
#define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
92
93
(6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
···
630
629
};
631
630
632
631
struct mlx5e_shampo_hd {
633
-
u32 mkey;
634
632
struct mlx5e_frag_page *pages;
635
633
u32 hd_per_wq;
636
634
u16 hd_per_wqe;
637
635
unsigned long *bitmap;
638
636
u16 pi;
639
637
u16 ci;
640
-
__be32 key;
638
+
__be32 mkey_be;
641
639
};
642
640
643
641
struct mlx5e_hw_gro_data {
+15
-30
drivers/net/ethernet/mellanox/mlx5/core/en/params.c
+15
-30
drivers/net/ethernet/mellanox/mlx5/core/en/params.c
···
414
414
return params->log_rq_mtu_frames - log_pkts_per_wqe;
415
415
}
416
416
417
-
u8 mlx5e_shampo_get_log_hd_entry_size(struct mlx5_core_dev *mdev,
418
-
struct mlx5e_params *params)
417
+
static u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5e_params *params)
419
418
{
420
-
return order_base_2(DIV_ROUND_UP(MLX5E_RX_MAX_HEAD, MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE));
421
-
}
422
-
423
-
u8 mlx5e_shampo_get_log_rsrv_size(struct mlx5_core_dev *mdev,
424
-
struct mlx5e_params *params)
425
-
{
426
-
return order_base_2(MLX5E_SHAMPO_WQ_RESRV_SIZE / MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE);
427
-
}
428
-
429
-
u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5_core_dev *mdev,
430
-
struct mlx5e_params *params)
431
-
{
432
-
u32 resrv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) *
433
-
MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE;
434
-
435
-
return order_base_2(DIV_ROUND_UP(resrv_size, params->sw_mtu));
419
+
return order_base_2(DIV_ROUND_UP(MLX5E_SHAMPO_WQ_RESRV_SIZE,
420
+
params->sw_mtu));
436
421
}
437
422
438
423
u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
···
819
834
struct mlx5e_params *params,
820
835
struct mlx5e_xsk_param *xsk)
821
836
{
822
-
int rsrv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) *
823
-
MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE;
824
837
u16 num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
825
-
int pkt_per_rsrv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params));
826
838
u8 log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
839
+
int pkt_per_rsrv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(params));
827
840
int wq_size = BIT(mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk));
828
841
int wqe_size = BIT(log_stride_sz) * num_strides;
842
+
int rsrv_size = MLX5E_SHAMPO_WQ_RESRV_SIZE;
829
843
830
844
/* +1 is for the case that the pkt_per_rsrv dont consume the reservation
831
845
* so we get a filler cqe for the rest of the reservation.
···
916
932
917
933
MLX5_SET(wq, wq, shampo_enable, true);
918
934
MLX5_SET(wq, wq, log_reservation_size,
919
-
mlx5e_shampo_get_log_rsrv_size(mdev, params));
935
+
MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE -
936
+
MLX5E_SHAMPO_WQ_RESRV_SIZE_BASE_SHIFT);
920
937
MLX5_SET(wq, wq,
921
938
log_max_num_of_packets_per_reservation,
922
-
mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params));
939
+
mlx5e_shampo_get_log_pkt_per_rsrv(params));
923
940
MLX5_SET(wq, wq, log_headers_entry_size,
924
-
mlx5e_shampo_get_log_hd_entry_size(mdev, params));
941
+
MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE -
942
+
MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE_SHIFT);
925
943
lro_timeout =
926
944
mlx5e_choose_lro_timeout(mdev,
927
945
MLX5E_DEFAULT_SHAMPO_TIMEOUT);
···
1034
1048
struct mlx5e_params *params,
1035
1049
struct mlx5e_rq_param *rq_param)
1036
1050
{
1037
-
int resv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) *
1038
-
MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE;
1039
1051
u16 num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, NULL));
1040
-
int pkt_per_resv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params));
1041
1052
u8 log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL);
1053
+
int pkt_per_rsrv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(params));
1042
1054
int wqe_size = BIT(log_stride_sz) * num_strides;
1055
+
int rsrv_size = MLX5E_SHAMPO_WQ_RESRV_SIZE;
1043
1056
u32 hd_per_wqe;
1044
1057
1045
1058
/* Assumption: hd_per_wqe % 8 == 0. */
1046
-
hd_per_wqe = (wqe_size / resv_size) * pkt_per_resv;
1047
-
mlx5_core_dbg(mdev, "%s hd_per_wqe = %d rsrv_size = %d wqe_size = %d pkt_per_resv = %d\n",
1048
-
__func__, hd_per_wqe, resv_size, wqe_size, pkt_per_resv);
1059
+
hd_per_wqe = (wqe_size / rsrv_size) * pkt_per_rsrv;
1060
+
mlx5_core_dbg(mdev, "%s hd_per_wqe = %d rsrv_size = %d wqe_size = %d pkt_per_rsrv = %d\n",
1061
+
__func__, hd_per_wqe, rsrv_size, wqe_size, pkt_per_rsrv);
1049
1062
return hd_per_wqe;
1050
1063
}
1051
1064
-6
drivers/net/ethernet/mellanox/mlx5/core/en/params.h
-6
drivers/net/ethernet/mellanox/mlx5/core/en/params.h
···
95
95
u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5_core_dev *mdev,
96
96
struct mlx5e_params *params,
97
97
struct mlx5e_xsk_param *xsk);
98
-
u8 mlx5e_shampo_get_log_hd_entry_size(struct mlx5_core_dev *mdev,
99
-
struct mlx5e_params *params);
100
-
u8 mlx5e_shampo_get_log_rsrv_size(struct mlx5_core_dev *mdev,
101
-
struct mlx5e_params *params);
102
-
u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5_core_dev *mdev,
103
-
struct mlx5e_params *params);
104
98
u32 mlx5e_shampo_hd_per_wqe(struct mlx5_core_dev *mdev,
105
99
struct mlx5e_params *params,
106
100
struct mlx5e_rq_param *rq_param);
+18
-9
drivers/net/ethernet/mellanox/mlx5/core/en_main.c
+18
-9
drivers/net/ethernet/mellanox/mlx5/core/en_main.c
···
546
546
}
547
547
548
548
static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev,
549
-
u16 hd_per_wq, u32 *umr_mkey)
549
+
u16 hd_per_wq, __be32 *umr_mkey)
550
550
{
551
551
u32 max_ksm_size = BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size));
552
+
u32 mkey;
553
+
int err;
552
554
553
555
if (max_ksm_size < hd_per_wq) {
554
556
mlx5_core_err(mdev, "max ksm list size 0x%x is smaller than shampo header buffer list size 0x%x\n",
555
557
max_ksm_size, hd_per_wq);
556
558
return -EINVAL;
557
559
}
558
-
return mlx5e_create_umr_ksm_mkey(mdev, hd_per_wq,
559
-
MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE,
560
-
umr_mkey);
560
+
561
+
err = mlx5e_create_umr_ksm_mkey(mdev, hd_per_wq,
562
+
MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE,
563
+
&mkey);
564
+
if (err)
565
+
return err;
566
+
567
+
*umr_mkey = cpu_to_be32(mkey);
568
+
return 0;
561
569
}
562
570
563
571
static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
···
791
783
goto err_shampo_hd_info_alloc;
792
784
793
785
err = mlx5e_create_rq_hd_umr_mkey(mdev, hd_per_wq,
794
-
&rq->mpwqe.shampo->mkey);
786
+
&rq->mpwqe.shampo->mkey_be);
795
787
if (err)
796
788
goto err_umr_mkey;
797
789
798
-
rq->mpwqe.shampo->key = cpu_to_be32(rq->mpwqe.shampo->mkey);
799
790
rq->mpwqe.shampo->hd_per_wqe =
800
791
mlx5e_shampo_hd_per_wqe(mdev, params, rqp);
801
792
wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz));
···
839
832
err_hw_gro_data:
840
833
page_pool_destroy(rq->hd_page_pool);
841
834
err_hds_page_pool:
842
-
mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey);
835
+
mlx5_core_destroy_mkey(mdev, be32_to_cpu(rq->mpwqe.shampo->mkey_be));
843
836
err_umr_mkey:
844
837
mlx5e_rq_shampo_hd_info_free(rq);
845
838
err_shampo_hd_info_alloc:
···
856
849
if (rq->hd_page_pool != rq->page_pool)
857
850
page_pool_destroy(rq->hd_page_pool);
858
851
mlx5e_rq_shampo_hd_info_free(rq);
859
-
mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey);
852
+
mlx5_core_destroy_mkey(rq->mdev,
853
+
be32_to_cpu(rq->mpwqe.shampo->mkey_be));
860
854
kvfree(rq->mpwqe.shampo);
861
855
}
862
856
···
1130
1122
if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
1131
1123
MLX5_SET(wq, wq, log_headers_buffer_entry_num,
1132
1124
order_base_2(rq->mpwqe.shampo->hd_per_wq));
1133
-
MLX5_SET(wq, wq, headers_mkey, rq->mpwqe.shampo->mkey);
1125
+
MLX5_SET(wq, wq, headers_mkey,
1126
+
be32_to_cpu(rq->mpwqe.shampo->mkey_be));
1134
1127
}
1135
1128
1136
1129
mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
···
676
676
wqe_bbs = MLX5E_KSM_UMR_WQEBBS(ksm_entries);
677
677
pi = mlx5e_icosq_get_next_pi(sq, wqe_bbs);
678
678
umr_wqe = mlx5_wq_cyc_get_wqe(&sq->wq, pi);
679
-
build_ksm_umr(sq, umr_wqe, shampo->key, index, ksm_entries);
679
+
build_ksm_umr(sq, umr_wqe, shampo->mkey_be, index, ksm_entries);
680
680
681
681
WARN_ON_ONCE(ksm_entries & (MLX5E_SHAMPO_WQ_HEADER_PER_PAGE - 1));
682
682
while (i < ksm_entries) {