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serial: 8250_dw: Rework dw8250_handle_irq() locking and IIR handling

dw8250_handle_irq() takes port's lock multiple times with no good
reason to release it in between and calls serial8250_handle_irq()
that also takes port's lock.

Take port's lock only once in dw8250_handle_irq() and use
serial8250_handle_irq_locked() to avoid releasing port's lock in
between.

As IIR_NO_INT check in serial8250_handle_irq() was outside of port's
lock, it has to be done already in dw8250_handle_irq().

DW UART can, in addition to IIR_NO_INT, report BUSY_DETECT (0x7) which
collided with the IIR_NO_INT (0x1) check in serial8250_handle_irq()
(because & is used instead of ==) meaning that no other work is done by
serial8250_handle_irq() during an BUSY_DETECT interrupt.

This allows reorganizing code in dw8250_handle_irq() to do both
IIR_NO_INT and BUSY_DETECT handling right at the start simplifying
the logic.

Tested-by: Bandal, Shankar <shankar.bandal@intel.com>
Tested-by: Murthy, Shanth <shanth.murthy@intel.com>
Cc: stable <stable@kernel.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Link: https://patch.msgid.link/20260203171049.4353-5-ilpo.jarvinen@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Ilpo Järvinen and committed by
Greg Kroah-Hartman 883c5a2b 8324a54f

+21 -16
+21 -16
drivers/tty/serial/8250/8250_dw.c
··· 9 9 * LCR is written whilst busy. If it is, then a busy detect interrupt is 10 10 * raised, the LCR needs to be rewritten and the uart status register read. 11 11 */ 12 + #include <linux/bitfield.h> 13 + #include <linux/bits.h> 14 + #include <linux/cleanup.h> 12 15 #include <linux/clk.h> 13 16 #include <linux/delay.h> 14 17 #include <linux/device.h> ··· 43 40 #define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */ 44 41 45 42 /* DesignWare specific register fields */ 43 + #define DW_UART_IIR_IID GENMASK(3, 0) 44 + 46 45 #define DW_UART_MCR_SIRE BIT(6) 47 46 48 47 /* Renesas specific register fields */ ··· 317 312 bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT; 318 313 unsigned int quirks = d->pdata->quirks; 319 314 unsigned int status; 320 - unsigned long flags; 315 + 316 + switch (FIELD_GET(DW_UART_IIR_IID, iir)) { 317 + case UART_IIR_NO_INT: 318 + return 0; 319 + 320 + case UART_IIR_BUSY: 321 + /* Clear the USR */ 322 + serial_port_in(p, d->pdata->usr_reg); 323 + 324 + return 1; 325 + } 326 + 327 + guard(uart_port_lock_irqsave)(p); 321 328 322 329 /* 323 330 * There are ways to get Designware-based UARTs into a state where ··· 342 325 * so we limit the workaround only to non-DMA mode. 343 326 */ 344 327 if (!up->dma && rx_timeout) { 345 - uart_port_lock_irqsave(p, &flags); 346 328 status = serial_lsr_in(up); 347 329 348 330 if (!(status & (UART_LSR_DR | UART_LSR_BI))) 349 331 serial_port_in(p, UART_RX); 350 - 351 - uart_port_unlock_irqrestore(p, flags); 352 332 } 353 333 354 334 /* Manually stop the Rx DMA transfer when acting as flow controller */ 355 335 if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) { 356 - uart_port_lock_irqsave(p, &flags); 357 336 status = serial_lsr_in(up); 358 - uart_port_unlock_irqrestore(p, flags); 359 337 360 338 if (status & (UART_LSR_DR | UART_LSR_BI)) { 361 339 dw8250_writel_ext(p, RZN1_UART_RDMACR, 0); ··· 358 346 } 359 347 } 360 348 361 - if (serial8250_handle_irq(p, iir)) 362 - return 1; 349 + serial8250_handle_irq_locked(p, iir); 363 350 364 - if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 365 - /* Clear the USR */ 366 - serial_port_in(p, d->pdata->usr_reg); 367 - 368 - return 1; 369 - } 370 - 371 - return 0; 351 + return 1; 372 352 } 373 353 374 354 static void dw8250_clk_work_cb(struct work_struct *work) ··· 871 867 872 868 module_platform_driver(dw8250_platform_driver); 873 869 870 + MODULE_IMPORT_NS("SERIAL_8250"); 874 871 MODULE_AUTHOR("Jamie Iles"); 875 872 MODULE_LICENSE("GPL"); 876 873 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");