crypto: hisilicon/zip - add hashjoin, gather, and UDMA data move features

The new version of the hisilicon zip driver supports the hash join
and gather features, as well as the data move feature (UDMA),
including data copying and memory initialization functions.These
features are registered to the uacce subsystem.

Signed-off-by: Zhushuai Yin <yinzhushuai@huawei.com>
Signed-off-by: Chenghai Huang <huangchenghai2@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Zhushuai Yin and committed by

Herbert Xu 9 months ago 886d6981 cf79ed6a

+33 -9

4 changed files

expand all

drivers

crypto

hisilicon

qm.c

zip

dae_main.c

include

linux

hisi_acc_qm.h

uapi

misc

uacce

hisi_qm.h

+22 -7

drivers/crypto/hisilicon/qm.c

··· 2742 2742 } 2743 2743 } 2744 2744 2745 + static void qm_uacce_api_ver_init(struct hisi_qm *qm) 2746 + { 2747 + struct uacce_device *uacce = qm->uacce; 2748 + 2749 + switch (qm->ver) { 2750 + case QM_HW_V1: 2751 + uacce->api_ver = HISI_QM_API_VER_BASE; 2752 + break; 2753 + case QM_HW_V2: 2754 + uacce->api_ver = HISI_QM_API_VER2_BASE; 2755 + break; 2756 + case QM_HW_V3: 2757 + case QM_HW_V4: 2758 + uacce->api_ver = HISI_QM_API_VER3_BASE; 2759 + break; 2760 + default: 2761 + uacce->api_ver = HISI_QM_API_VER5_BASE; 2762 + break; 2763 + } 2764 + } 2765 + 2745 2766 static int qm_alloc_uacce(struct hisi_qm *qm) 2746 2767 { 2747 2768 struct pci_dev *pdev = qm->pdev; ··· 2797 2776 uacce->priv = qm; 2798 2777 2799 2778 if (qm->ver == QM_HW_V1) 2800 - uacce->api_ver = HISI_QM_API_VER_BASE; 2801 - else if (qm->ver == QM_HW_V2) 2802 - uacce->api_ver = HISI_QM_API_VER2_BASE; 2803 - else 2804 - uacce->api_ver = HISI_QM_API_VER3_BASE; 2805 - 2806 - if (qm->ver == QM_HW_V1) 2807 2779 mmio_page_nr = QM_DOORBELL_PAGE_NR; 2808 2780 else if (!test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps)) 2809 2781 mmio_page_nr = QM_DOORBELL_PAGE_NR + ··· 2815 2801 uacce->qf_pg_num[UACCE_QFRT_DUS] = dus_page_nr; 2816 2802 2817 2803 qm->uacce = uacce; 2804 + qm_uacce_api_ver_init(qm); 2818 2805 INIT_LIST_HEAD(&qm->isolate_data.qm_hw_errs); 2819 2806 mutex_init(&qm->isolate_data.isolate_lock); 2820 2807

+9 -2

drivers/crypto/hisilicon/zip/dae_main.c

··· 15 15 #define DAE_REG_RD_TMOUT_US USEC_PER_SEC 16 16 17 17 #define DAE_ALG_NAME "hashagg" 18 + #define DAE_V5_ALG_NAME "hashagg\nudma\nhashjoin\ngather" 18 19 19 20 /* error */ 20 21 #define DAE_AXI_CFG_OFFSET 0x331000 ··· 83 82 84 83 int hisi_dae_set_alg(struct hisi_qm *qm) 85 84 { 85 + const char *alg_name; 86 86 size_t len; 87 87 88 88 if (!dae_is_support(qm)) ··· 92 90 if (!qm->uacce) 93 91 return 0; 94 92 93 + if (qm->ver >= QM_HW_V5) 94 + alg_name = DAE_V5_ALG_NAME; 95 + else 96 + alg_name = DAE_ALG_NAME; 97 + 95 98 len = strlen(qm->uacce->algs); 96 99 /* A line break may be required */ 97 - if (len + strlen(DAE_ALG_NAME) + 1 >= QM_DEV_ALG_MAX_LEN) { 100 + if (len + strlen(alg_name) + 1 >= QM_DEV_ALG_MAX_LEN) { 98 101 pci_err(qm->pdev, "algorithm name is too long!\n"); 99 102 return -EINVAL; 100 103 } ··· 107 100 if (len) 108 101 strcat((char *)qm->uacce->algs, "\n"); 109 102 110 - strcat((char *)qm->uacce->algs, DAE_ALG_NAME); 103 + strcat((char *)qm->uacce->algs, alg_name); 111 104 112 105 return 0; 113 106 }

include/linux/hisi_acc_qm.h

··· 125 125 QM_HW_V2 = 0x21, 126 126 QM_HW_V3 = 0x30, 127 127 QM_HW_V4 = 0x50, 128 + QM_HW_V5 = 0x51, 128 129 }; 129 130 130 131 enum qm_fun_type {

include/uapi/misc/uacce/hisi_qm.h

··· 31 31 #define HISI_QM_API_VER_BASE "hisi_qm_v1" 32 32 #define HISI_QM_API_VER2_BASE "hisi_qm_v2" 33 33 #define HISI_QM_API_VER3_BASE "hisi_qm_v3" 34 + #define HISI_QM_API_VER5_BASE "hisi_qm_v5" 34 35 35 36 /* UACCE_CMD_QM_SET_QP_CTX: Set qp algorithm type */ 36 37 #define UACCE_CMD_QM_SET_QP_CTX _IOWR('H', 10, struct hisi_qp_ctx)

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