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dt-bindings: pinctrl: Convert brcm,iproc-gpio to DT schema

Convert the Broadcom iProc/Cygnus GPIO/Pinconf binding to DT schema
format.

The child node structure is based on the example as there's not any
actual .dts files with child nodes.

The binding wasn't clear that "reg" can be 1 or 2 entries. The number of
"reg" entries doesn't appear to be based on compatible, so no per
compatible constraints for it

The "brcm,iproc-stingray-gpio" could possibly be dropped. There are no
.dts files using it, but the driver uses it.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/20250812203348.733749-1-robh@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

authored by

Rob Herring (Arm) and committed by
Linus Walleij
8898cf86 2b31c1c7

+111 -123
-123
Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt
··· 1 - Broadcom iProc GPIO/PINCONF Controller 2 - 3 - Required properties: 4 - 5 - - compatible: 6 - "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that 7 - supports full-featured pinctrl and GPIO functions used in various iProc 8 - based SoCs 9 - 10 - May contain an SoC-specific compatibility string to accommodate any 11 - SoC-specific features 12 - 13 - "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or 14 - "brcm,cygnus-crmu-gpio" for Cygnus SoCs 15 - 16 - "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support 17 - disabled 18 - 19 - "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general 20 - pinctrl support completely disabled in this IP block. In Stingray, a 21 - different IP block is used to handle pinctrl related functions 22 - 23 - - reg: 24 - Define the base and range of the I/O address space that contains SoC 25 - GPIO/PINCONF controller registers 26 - 27 - - ngpios: 28 - Total number of in-use slots in GPIO controller 29 - 30 - - #gpio-cells: 31 - Must be two. The first cell is the GPIO pin number (within the 32 - controller's pin space) and the second cell is used for the following: 33 - bit[0]: polarity (0 for active high and 1 for active low) 34 - 35 - - gpio-controller: 36 - Specifies that the node is a GPIO controller 37 - 38 - Optional properties: 39 - 40 - - interrupts: 41 - Interrupt ID 42 - 43 - - interrupt-controller: 44 - Specifies that the node is an interrupt controller 45 - 46 - - gpio-ranges: 47 - Specifies the mapping between gpio controller and pin-controllers pins. 48 - This requires 4 fields in cells defined as - 49 - 1. Phandle of pin-controller. 50 - 2. GPIO base pin offset. 51 - 3 Pin-control base pin offset. 52 - 4. number of gpio pins which are linearly mapped from pin base. 53 - 54 - Supported generic PINCONF properties in child nodes: 55 - 56 - - pins: 57 - The list of pins (within the controller's own pin space) that properties 58 - in the node apply to. Pin names are "gpio-<pin>" 59 - 60 - - bias-disable: 61 - Disable pin bias 62 - 63 - - bias-pull-up: 64 - Enable internal pull up resistor 65 - 66 - - bias-pull-down: 67 - Enable internal pull down resistor 68 - 69 - - drive-strength: 70 - Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA) 71 - 72 - Example: 73 - gpio_ccm: gpio@1800a000 { 74 - compatible = "brcm,cygnus-ccm-gpio"; 75 - reg = <0x1800a000 0x50>, 76 - <0x0301d164 0x20>; 77 - ngpios = <24>; 78 - #gpio-cells = <2>; 79 - gpio-controller; 80 - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 81 - interrupt-controller; 82 - 83 - touch_pins: touch_pins { 84 - pwr: pwr { 85 - pins = "gpio-0"; 86 - drive-strength = <16>; 87 - }; 88 - 89 - event: event { 90 - pins = "gpio-1"; 91 - bias-pull-up; 92 - }; 93 - }; 94 - }; 95 - 96 - gpio_asiu: gpio@180a5000 { 97 - compatible = "brcm,cygnus-asiu-gpio"; 98 - reg = <0x180a5000 0x668>; 99 - ngpios = <146>; 100 - #gpio-cells = <2>; 101 - gpio-controller; 102 - interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 103 - interrupt-controller; 104 - gpio-ranges = <&pinctrl 0 42 1>, 105 - <&pinctrl 1 44 3>; 106 - }; 107 - 108 - /* 109 - * Touchscreen that uses the CCM GPIO 0 and 1 110 - */ 111 - tsc { 112 - ... 113 - ... 114 - gpio-pwr = <&gpio_ccm 0 0>; 115 - gpio-event = <&gpio_ccm 1 0>; 116 - }; 117 - 118 - /* Bluetooth that uses the ASIU GPIO 5, with polarity inverted */ 119 - bluetooth { 120 - ... 121 - ... 122 - bcm,rfkill-bank-sel = <&gpio_asiu 5 1> 123 - }
+111
Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pinctrl/brcm,iproc-gpio.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom iProc GPIO/PINCONF Controller 8 + 9 + maintainers: 10 + - Ray Jui <rjui@broadcom.com> 11 + - Scott Branden <sbranden@broadcom.com> 12 + 13 + properties: 14 + compatible: 15 + oneOf: 16 + - enum: 17 + - brcm,cygnus-asiu-gpio 18 + - brcm,cygnus-ccm-gpio 19 + - brcm,cygnus-crmu-gpio 20 + - brcm,iproc-gpio 21 + - brcm,iproc-stingray-gpio 22 + - items: 23 + - enum: 24 + - brcm,iproc-hr2-gpio 25 + - brcm,iproc-nsp-gpio 26 + - const: brcm,iproc-gpio 27 + 28 + reg: 29 + minItems: 1 30 + items: 31 + - description: GPIO Bank registers 32 + - description: IO Ctrl registers 33 + 34 + "#gpio-cells": 35 + const: 2 36 + 37 + gpio-controller: true 38 + 39 + gpio-ranges: true 40 + 41 + ngpios: true 42 + 43 + "#interrupt-cells": 44 + const: 2 45 + 46 + interrupts: 47 + maxItems: 1 48 + 49 + interrupt-controller: true 50 + 51 + required: 52 + - compatible 53 + - reg 54 + - "#gpio-cells" 55 + - gpio-controller 56 + - ngpios 57 + 58 + patternProperties: 59 + '-pins$': 60 + type: object 61 + additionalProperties: 62 + description: Pin configuration child nodes. 63 + allOf: 64 + - $ref: pincfg-node.yaml# 65 + - $ref: pinmux-node.yaml# 66 + additionalProperties: false 67 + 68 + properties: 69 + pins: 70 + items: 71 + pattern: '^gpio-' 72 + 73 + bias-disable: true 74 + bias-pull-up: true 75 + bias-pull-down: true 76 + 77 + drive-strength: 78 + enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ] 79 + 80 + required: 81 + - pins 82 + 83 + additionalProperties: false 84 + 85 + examples: 86 + - | 87 + #include <dt-bindings/interrupt-controller/arm-gic.h> 88 + 89 + gpio@1800a000 { 90 + compatible = "brcm,cygnus-ccm-gpio"; 91 + reg = <0x1800a000 0x50>, 92 + <0x0301d164 0x20>; 93 + ngpios = <24>; 94 + #gpio-cells = <2>; 95 + gpio-controller; 96 + #interrupt-cells = <2>; 97 + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 98 + interrupt-controller; 99 + 100 + touch-pins { 101 + pwr { 102 + pins = "gpio-0"; 103 + drive-strength = <16>; 104 + }; 105 + 106 + event { 107 + pins = "gpio-1"; 108 + bias-pull-up; 109 + }; 110 + }; 111 + };