Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: cadence: salvo: add access for USB2PHY
There is an offset for USB2PHY in SALVO phy, add offset parameter for read
and write API to cover both USB2 and USB3 PHY control.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20230517161646.3418250-2-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Peter Chen
and committed by
Vinod Koul
88bc4cda
1178c93c
+10
-8
+10
-8
drivers/phy/cadence/phy-cadence-salvo.c
+10
-8
drivers/phy/cadence/phy-cadence-salvo.c
···
15
15
#include <linux/of.h>
16
16
#include <linux/of_platform.h>
17
17
18
-
/* PHY register definition */
18
+
#define USB3_PHY_OFFSET 0x0
19
+
#define USB2_PHY_OFFSET 0x38000
20
+
/* USB3 PHY register definition */
19
21
#define PHY_PMA_CMN_CTRL1 0xC800
20
22
#define TB_ADDR_CMN_DIAG_HSCLK_SEL 0x01e0
21
23
#define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR 0x0084
···
111
109
};
112
110
113
111
static const struct of_device_id cdns_salvo_phy_of_match[];
114
-
static u16 cdns_salvo_read(struct cdns_salvo_phy *salvo_phy, u32 reg)
112
+
static u16 cdns_salvo_read(struct cdns_salvo_phy *salvo_phy, u32 offset, u32 reg)
115
113
{
116
-
return (u16)readl(salvo_phy->base +
114
+
return (u16)readl(salvo_phy->base + offset +
117
115
reg * (1 << salvo_phy->data->reg_offset_shift));
118
116
}
119
117
120
-
static void cdns_salvo_write(struct cdns_salvo_phy *salvo_phy,
118
+
static void cdns_salvo_write(struct cdns_salvo_phy *salvo_phy, u32 offset,
121
119
u32 reg, u16 val)
122
120
{
123
-
writel(val, salvo_phy->base +
121
+
writel(val, salvo_phy->base + offset +
124
122
reg * (1 << salvo_phy->data->reg_offset_shift));
125
123
}
126
124
···
221
219
for (i = 0; i < data->init_sequence_length; i++) {
222
220
const struct cdns_reg_pairs *reg_pair = data->init_sequence_val + i;
223
221
224
-
cdns_salvo_write(salvo_phy, reg_pair->off, reg_pair->val);
222
+
cdns_salvo_write(salvo_phy, USB3_PHY_OFFSET, reg_pair->off, reg_pair->val);
225
223
}
226
224
227
225
/* RXDET_IN_P3_32KHZ, Receiver detect slow clock enable */
228
-
value = cdns_salvo_read(salvo_phy, TB_ADDR_TX_RCVDETSC_CTRL);
226
+
value = cdns_salvo_read(salvo_phy, USB3_PHY_OFFSET, TB_ADDR_TX_RCVDETSC_CTRL);
229
227
value |= RXDET_IN_P3_32KHZ;
230
-
cdns_salvo_write(salvo_phy, TB_ADDR_TX_RCVDETSC_CTRL,
228
+
cdns_salvo_write(salvo_phy, USB3_PHY_OFFSET, TB_ADDR_TX_RCVDETSC_CTRL,
231
229
RXDET_IN_P3_32KHZ);
232
230
233
231
udelay(10);