Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'armsoc-for-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Another week, another small batch of fixes.
Most of these make zynq, socfpga and sunxi platforms work a bit
better:
- due to new requirements for regulators, DWMMC on socfpga broke past
v3.17
- SMP spinup fix for socfpga
- a few DT fixes for zynq
- another option (FIXED_REGULATOR) for sunxi is needed that used to
be selected by other options but no longer is.
- a couple of small DT fixes for at91
- ...and a couple for i.MX"
* tag 'armsoc-for-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: dts: imx28-evk: Let i2c0 run at 100kHz
ARM: i.MX6: Fix "emi" clock name typo
ARM: multi_v7_defconfig: enable CONFIG_MMC_DW_ROCKCHIP
ARM: sunxi_defconfig: enable CONFIG_REGULATOR_FIXED_VOLTAGE
ARM: dts: socfpga: Add a 3.3V fixed regulator node
ARM: dts: socfpga: Fix SD card detect
ARM: dts: socfpga: rename gpio nodes
ARM: at91/dt: sam9263: fix PLLB frequencies
power: reset: at91-reset: fix power down register
MAINTAINERS: add atmel ssc driver maintainer entry
arm: socfpga: fix fetching cpu1start_addr for SMP
ARM: zynq: DT: trivial: Fix mc node
ARM: zynq: DT: Add cadence watchdog node
ARM: zynq: DT: Add missing reference for memory-controller
ARM: zynq: DT: Add missing reference for ADC
ARM: zynq: DT: Add missing address for L2 pl310
ARM: zynq: DT: Remove 222 MHz OPP
ARM: zynq: DT: Fix GEM register area size
+107
-46
+7
MAINTAINERS
+7
MAINTAINERS
···
1749
1749
S: Supported
1750
1750
F: drivers/spi/spi-atmel.*
1751
1751
1752
+
ATMEL SSC DRIVER
1753
+
M: Bo Shen <voice.shen@atmel.com>
1754
+
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1755
+
S: Supported
1756
+
F: drivers/misc/atmel-ssc.c
1757
+
F: include/linux/atmel-ssc.h
1758
+
1752
1759
ATMEL Timer Counter (TC) AND CLOCKSOURCE DRIVERS
1753
1760
M: Nicolas Ferre <nicolas.ferre@atmel.com>
1754
1761
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+3
-2
arch/arm/boot/dts/at91sam9263.dtsi
+3
-2
arch/arm/boot/dts/at91sam9263.dtsi
···
122
122
interrupts-extended = <&pmc AT91_PMC_LOCKB>;
123
123
clocks = <&main>;
124
124
reg = <1>;
125
-
atmel,clk-input-range = <1000000 5000000>;
125
+
atmel,clk-input-range = <1000000 32000000>;
126
126
#atmel,pll-clk-output-range-cells = <4>;
127
-
atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
127
+
atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
128
+
<190000000 240000000 2 1>;
128
129
};
129
130
130
131
mck: masterck {
-1
arch/arm/boot/dts/imx28-evk.dts
-1
arch/arm/boot/dts/imx28-evk.dts
+6
-6
arch/arm/boot/dts/socfpga.dtsi
+6
-6
arch/arm/boot/dts/socfpga.dtsi
···
547
547
status = "disabled";
548
548
};
549
549
550
-
gpio@ff708000 {
550
+
gpio0: gpio@ff708000 {
551
551
#address-cells = <1>;
552
552
#size-cells = <0>;
553
553
compatible = "snps,dw-apb-gpio";
···
555
555
clocks = <&per_base_clk>;
556
556
status = "disabled";
557
557
558
-
gpio0: gpio-controller@0 {
558
+
porta: gpio-controller@0 {
559
559
compatible = "snps,dw-apb-gpio-port";
560
560
gpio-controller;
561
561
#gpio-cells = <2>;
···
567
567
};
568
568
};
569
569
570
-
gpio@ff709000 {
570
+
gpio1: gpio@ff709000 {
571
571
#address-cells = <1>;
572
572
#size-cells = <0>;
573
573
compatible = "snps,dw-apb-gpio";
···
575
575
clocks = <&per_base_clk>;
576
576
status = "disabled";
577
577
578
-
gpio1: gpio-controller@0 {
578
+
portb: gpio-controller@0 {
579
579
compatible = "snps,dw-apb-gpio-port";
580
580
gpio-controller;
581
581
#gpio-cells = <2>;
···
587
587
};
588
588
};
589
589
590
-
gpio@ff70a000 {
590
+
gpio2: gpio@ff70a000 {
591
591
#address-cells = <1>;
592
592
#size-cells = <0>;
593
593
compatible = "snps,dw-apb-gpio";
···
595
595
clocks = <&per_base_clk>;
596
596
status = "disabled";
597
597
598
-
gpio2: gpio-controller@0 {
598
+
portc: gpio-controller@0 {
599
599
compatible = "snps,dw-apb-gpio-port";
600
600
gpio-controller;
601
601
#gpio-cells = <2>;
+1
-1
arch/arm/boot/dts/socfpga_arria5.dtsi
+1
-1
arch/arm/boot/dts/socfpga_arria5.dtsi
+12
arch/arm/boot/dts/socfpga_arria5_socdk.dts
+12
arch/arm/boot/dts/socfpga_arria5_socdk.dts
···
37
37
*/
38
38
ethernet0 = &gmac1;
39
39
};
40
+
41
+
regulator_3_3v: 3-3-v-regulator {
42
+
compatible = "regulator-fixed";
43
+
regulator-name = "3.3V";
44
+
regulator-min-microvolt = <3300000>;
45
+
regulator-max-microvolt = <3300000>;
46
+
};
40
47
};
41
48
42
49
&gmac1 {
···
73
66
compatible = "dallas,ds1339";
74
67
reg = <0x68>;
75
68
};
69
+
};
70
+
71
+
&mmc0 {
72
+
vmmc-supply = <®ulator_3_3v>;
73
+
vqmmc-supply = <®ulator_3_3v>;
76
74
};
77
75
78
76
&usb1 {
+14
-1
arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+14
-1
arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
···
37
37
*/
38
38
ethernet0 = &gmac1;
39
39
};
40
+
41
+
regulator_3_3v: 3-3-v-regulator {
42
+
compatible = "regulator-fixed";
43
+
regulator-name = "3.3V";
44
+
regulator-min-microvolt = <3300000>;
45
+
regulator-max-microvolt = <3300000>;
46
+
};
40
47
};
41
48
42
49
&gmac1 {
···
58
51
txc-skew-ps = <2600>;
59
52
rxdv-skew-ps = <0>;
60
53
rxc-skew-ps = <2000>;
54
+
};
55
+
56
+
&gpio1 {
57
+
status = "okay";
61
58
};
62
59
63
60
&i2c0 {
···
80
69
};
81
70
82
71
&mmc0 {
83
-
cd-gpios = <&gpio1 18 0>;
72
+
cd-gpios = <&portb 18 0>;
73
+
vmmc-supply = <®ulator_3_3v>;
74
+
vqmmc-supply = <®ulator_3_3v>;
84
75
};
85
76
86
77
&usb1 {
+12
arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
+12
arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
···
37
37
*/
38
38
ethernet0 = &gmac1;
39
39
};
40
+
41
+
regulator_3_3v: vcc3p3-regulator {
42
+
compatible = "regulator-fixed";
43
+
regulator-name = "VCC3P3";
44
+
regulator-min-microvolt = <3300000>;
45
+
regulator-max-microvolt = <3300000>;
46
+
};
40
47
};
41
48
42
49
&gmac1 {
···
58
51
txc-skew-ps = <2600>;
59
52
rxdv-skew-ps = <0>;
60
53
rxc-skew-ps = <2000>;
54
+
};
55
+
56
+
&mmc0 {
57
+
vmmc-supply = <®ulator_3_3v>;
58
+
vqmmc-supply = <®ulator_3_3v>;
61
59
};
62
60
63
61
&usb1 {
+17
-7
arch/arm/boot/dts/zynq-7000.dtsi
+17
-7
arch/arm/boot/dts/zynq-7000.dtsi
···
30
30
/* kHz uV */
31
31
666667 1000000
32
32
333334 1000000
33
-
222223 1000000
34
33
>;
35
34
};
36
35
···
64
65
interrupt-parent = <&intc>;
65
66
ranges;
66
67
67
-
adc@f8007100 {
68
+
adc: adc@f8007100 {
68
69
compatible = "xlnx,zynq-xadc-1.00.a";
69
70
reg = <0xf8007100 0x20>;
70
71
interrupts = <0 7 4>;
···
136
137
<0xF8F00100 0x100>;
137
138
};
138
139
139
-
L2: cache-controller {
140
+
L2: cache-controller@f8f02000 {
140
141
compatible = "arm,pl310-cache";
141
142
reg = <0xF8F02000 0x1000>;
142
143
arm,data-latency = <3 2 2>;
···
145
146
cache-level = <2>;
146
147
};
147
148
148
-
memory-controller@f8006000 {
149
+
mc: memory-controller@f8006000 {
149
150
compatible = "xlnx,zynq-ddrc-a05";
150
151
reg = <0xf8006000 0x1000>;
151
-
} ;
152
+
};
152
153
153
154
uart0: serial@e0000000 {
154
155
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
···
194
195
195
196
gem0: ethernet@e000b000 {
196
197
compatible = "cdns,gem";
197
-
reg = <0xe000b000 0x4000>;
198
+
reg = <0xe000b000 0x1000>;
198
199
status = "disabled";
199
200
interrupts = <0 22 4>;
200
201
clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
···
205
206
206
207
gem1: ethernet@e000c000 {
207
208
compatible = "cdns,gem";
208
-
reg = <0xe000c000 0x4000>;
209
+
reg = <0xe000c000 0x1000>;
209
210
status = "disabled";
210
211
interrupts = <0 45 4>;
211
212
clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
···
313
314
compatible = "arm,cortex-a9-twd-timer";
314
315
reg = <0xf8f00600 0x20>;
315
316
clocks = <&clkc 4>;
317
+
};
318
+
319
+
watchdog0: watchdog@f8005000 {
320
+
clocks = <&clkc 45>;
321
+
compatible = "xlnx,zynq-wdt-r1p2";
322
+
device_type = "watchdog";
323
+
interrupt-parent = <&intc>;
324
+
interrupts = <0 9 1>;
325
+
reg = <0xf8005000 0x1000>;
326
+
reset = <0>;
327
+
timeout-sec = <10>;
316
328
};
317
329
};
318
330
};
+1
arch/arm/configs/multi_v7_defconfig
+1
arch/arm/configs/multi_v7_defconfig
+1
arch/arm/configs/sunxi_defconfig
+1
arch/arm/configs/sunxi_defconfig
+7
-7
arch/arm/mach-imx/clk-imx6q.c
+7
-7
arch/arm/mach-imx/clk-imx6q.c
···
50
50
static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", };
51
51
static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
52
52
static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
53
-
static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
54
-
static const char *emi_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
53
+
static const char *eim_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
54
+
static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
55
55
static const char *vdo_axi_sels[] = { "axi", "ahb", };
56
56
static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
57
57
static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
···
302
302
clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
303
303
clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
304
304
clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
305
-
clk[IMX6QDL_CLK_EMI_SEL] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup);
306
-
clk[IMX6QDL_CLK_EMI_SLOW_SEL] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup);
305
+
clk[IMX6QDL_CLK_EIM_SEL] = imx_clk_fixup_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels), imx_cscmr1_fixup);
306
+
clk[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup);
307
307
clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
308
308
clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
309
309
clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
···
354
354
clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
355
355
clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
356
356
clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
357
-
clk[IMX6QDL_CLK_EMI_PODF] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
358
-
clk[IMX6QDL_CLK_EMI_SLOW_PODF] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
357
+
clk[IMX6QDL_CLK_EIM_PODF] = imx_clk_fixup_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
358
+
clk[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_fixup_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
359
359
clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
360
360
clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
361
361
clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
···
456
456
clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
457
457
clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
458
458
clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
459
-
clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10);
459
+
clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10);
460
460
clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
461
461
clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
462
462
clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
+1
-1
arch/arm/mach-socfpga/core.h
+1
-1
arch/arm/mach-socfpga/core.h
+15
-10
arch/arm/mach-socfpga/headsmp.S
+15
-10
arch/arm/mach-socfpga/headsmp.S
···
9
9
*/
10
10
#include <linux/linkage.h>
11
11
#include <linux/init.h>
12
+
#include <asm/memory.h>
12
13
13
14
.arch armv7-a
14
15
15
16
ENTRY(secondary_trampoline)
16
-
movw r2, #:lower16:cpu1start_addr
17
-
movt r2, #:upper16:cpu1start_addr
17
+
/* CPU1 will always fetch from 0x0 when it is brought out of reset.
18
+
* Thus, we can just subtract the PAGE_OFFSET to get the physical
19
+
* address of &cpu1start_addr. This would not work for platforms
20
+
* where the physical memory does not start at 0x0.
21
+
*/
22
+
adr r0, 1f
23
+
ldmia r0, {r1, r2}
24
+
sub r2, r2, #PAGE_OFFSET
25
+
ldr r3, [r2]
26
+
ldr r4, [r3]
27
+
bx r4
18
28
19
-
/* The socfpga VT cannot handle a 0xC0000000 page offset when loading
20
-
the cpu1start_addr, we bit clear it. Tested on HW and VT. */
21
-
bic r2, r2, #0x40000000
22
-
23
-
ldr r0, [r2]
24
-
ldr r1, [r0]
25
-
bx r1
26
-
29
+
.align
30
+
1: .long .
31
+
.long socfpga_cpu1start_addr
27
32
ENTRY(secondary_trampoline_end)
28
33
29
34
ENTRY(socfpga_secondary_startup)
+2
-2
arch/arm/mach-socfpga/platsmp.c
+2
-2
arch/arm/mach-socfpga/platsmp.c
···
33
33
{
34
34
int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
35
35
36
-
if (cpu1start_addr) {
36
+
if (socfpga_cpu1start_addr) {
37
37
memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
38
38
39
39
__raw_writel(virt_to_phys(socfpga_secondary_startup),
40
-
(sys_manager_base_addr + (cpu1start_addr & 0x000000ff)));
40
+
(sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff)));
41
41
42
42
flush_cache_all();
43
43
smp_wmb();
+2
-2
arch/arm/mach-socfpga/socfpga.c
+2
-2
arch/arm/mach-socfpga/socfpga.c
···
29
29
void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
30
30
void __iomem *sys_manager_base_addr;
31
31
void __iomem *rst_manager_base_addr;
32
-
unsigned long cpu1start_addr;
32
+
unsigned long socfpga_cpu1start_addr;
33
33
34
34
static struct map_desc scu_io_desc __initdata = {
35
35
.virtual = SOCFPGA_SCU_VIRT_BASE,
···
70
70
np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
71
71
72
72
if (of_property_read_u32(np, "cpu1-start-addr",
73
-
(u32 *) &cpu1start_addr))
73
+
(u32 *) &socfpga_cpu1start_addr))
74
74
pr_err("SMP: Need cpu1-start-addr in device tree.\n");
75
75
76
76
sys_manager_base_addr = of_iomap(np, 0);
+2
-2
drivers/power/reset/at91-reset.c
+2
-2
drivers/power/reset/at91-reset.c
···
100
100
/* Disable SDRAM0 accesses */
101
101
"1: str %3, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
102
102
/* Power down SDRAM0 */
103
-
" str %4, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
103
+
" str %4, [%0, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
104
104
/* Disable SDRAM1 accesses */
105
105
" strne %3, [%1, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
106
106
/* Power down SDRAM1 */
107
-
" strne %4, [%1, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
107
+
" strne %4, [%1, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
108
108
/* Reset CPU */
109
109
" str %5, [%2, #" __stringify(AT91_RSTC_CR) "]\n\t"
110
110
+4
-4
include/dt-bindings/clock/imx6qdl-clock.h
+4
-4
include/dt-bindings/clock/imx6qdl-clock.h
···
62
62
#define IMX6QDL_CLK_USDHC3_SEL 50
63
63
#define IMX6QDL_CLK_USDHC4_SEL 51
64
64
#define IMX6QDL_CLK_ENFC_SEL 52
65
-
#define IMX6QDL_CLK_EMI_SEL 53
66
-
#define IMX6QDL_CLK_EMI_SLOW_SEL 54
65
+
#define IMX6QDL_CLK_EIM_SEL 53
66
+
#define IMX6QDL_CLK_EIM_SLOW_SEL 54
67
67
#define IMX6QDL_CLK_VDO_AXI_SEL 55
68
68
#define IMX6QDL_CLK_VPU_AXI_SEL 56
69
69
#define IMX6QDL_CLK_CKO1_SEL 57
···
106
106
#define IMX6QDL_CLK_USDHC4_PODF 94
107
107
#define IMX6QDL_CLK_ENFC_PRED 95
108
108
#define IMX6QDL_CLK_ENFC_PODF 96
109
-
#define IMX6QDL_CLK_EMI_PODF 97
110
-
#define IMX6QDL_CLK_EMI_SLOW_PODF 98
109
+
#define IMX6QDL_CLK_EIM_PODF 97
110
+
#define IMX6QDL_CLK_EIM_SLOW_PODF 98
111
111
#define IMX6QDL_CLK_VPU_AXI_PODF 99
112
112
#define IMX6QDL_CLK_CKO1_PODF 100
113
113
#define IMX6QDL_CLK_AXI 101