Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2020-02-21' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Varied fixes for rc3.
i915 is the largest, they are seeing some ACPI problems with their CI
which hopefully get solved soon [1].
msm has a bunch of fixes for new hw added in the merge, a bunch of
amdgpu fixes, and nouveau adds support for some new firmwares for
turing tu11x GPUs that were just released into linux-firmware by
nvidia, they operate the same as the ones we already have for tu10x so
should be fine to hook up.
Otherwise it's just misc fixes for panfrost and sun4i.
core:
- Allow only one rotation argument, and allow zero rotation in video
cmdline.
i915:
- Workaround missing Display Stream Compression (DSC) state readout
by forcing modeset when its enabled at probe
- Fix EHL port clock voltage level requirements
- Fix queuing retire workers on the virtual engine
- Fix use of partially initialized waiters
- Stop using drm_pci_alloc/drm_pci/free
- Fix rewind of RING_TAIL by forcing a context reload
- Fix locking on resetting ring->head
- Propagate our bug filing URL change to stable kernels
panfrost:
- Small compiler warning fix for panfrost.
- Fix when using performance counters in panfrost when using per fd
address space.
sun4xi:
- Fix dt binding
nouveau:
- tu11x modesetting fix
- ACR/GR firmware support for tu11x (fw is public now)
msm:
- fix UBWC on GPU and display side for sc7180
- fix DSI suspend/resume issue encountered on sc7180
- fix some breakage on so called "linux-android" devices
(fallout from sc7180/a618 support, not seen earlier due to
bootloader/firmware differences)
- couple other misc fixes
amdgpu:
- HDCP fixes
- xclk fix for raven
- GFXOFF fixes"
[1] The Intel suspend testing should now be fixed by commit 63fb9623427f
("ACPI: PM: s2idle: Check fixed wakeup events in acpi_s2idle_wake()")
* tag 'drm-fixes-2020-02-21' of git://anongit.freedesktop.org/drm/drm: (39 commits)
drm/amdgpu/display: clean up hdcp workqueue handling
drm/amdgpu: add is_raven_kicker judgement for raven1
drm/i915/gt: Avoid resetting ring->head outside of its timeline mutex
drm/i915/execlists: Always force a context reload when rewinding RING_TAIL
drm/i915: Wean off drm_pci_alloc/drm_pci_free
drm/i915/gt: Protect defer_request() from new waiters
drm/i915/gt: Prevent queuing retire workers on the virtual engine
drm/i915/dsc: force full modeset whenever DSC is enabled at probe
drm/i915/ehl: Update port clock voltage level requirements
drm/i915: Update drm/i915 bug filing URL
MAINTAINERS: Update drm/i915 bug filing URL
drm/i915: Initialise basic fence before acquiring seqno
drm/i915/gem: Require per-engine reset support for non-persistent contexts
drm/nouveau/kms/gv100-: Re-set LUT after clearing for modesets
drm/nouveau/gr/tu11x: initial support
drm/nouveau/acr/tu11x: initial support
drm/amdgpu/gfx10: disable gfxoff when reading rlc clock
drm/amdgpu/gfx9: disable gfxoff when reading rlc clock
drm/amdgpu/soc15: fix xclk for raven
drm/amd/powerplay: always refetch the enabled features status on dpm enablement
...
+489
-246
+5
-1
Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml
+5
-1
Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml
···
43
43
- enum:
44
44
- allwinner,sun8i-h3-tcon-tv
45
45
- allwinner,sun50i-a64-tcon-tv
46
-
- allwinner,sun50i-h6-tcon-tv
47
46
- const: allwinner,sun8i-a83t-tcon-tv
47
+
48
+
- items:
49
+
- enum:
50
+
- allwinner,sun50i-h6-tcon-tv
51
+
- const: allwinner,sun8i-r40-tcon-tv
48
52
49
53
reg:
50
54
maxItems: 1
+1
-1
MAINTAINERS
+1
-1
MAINTAINERS
···
8392
8392
M: Rodrigo Vivi <rodrigo.vivi@intel.com>
8393
8393
L: intel-gfx@lists.freedesktop.org
8394
8394
W: https://01.org/linuxgraphics/
8395
-
B: https://01.org/linuxgraphics/documentation/how-report-bugs
8395
+
B: https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs
8396
8396
C: irc://chat.freenode.net/intel-gfx
8397
8397
Q: http://patchwork.freedesktop.org/project/intel-gfx/
8398
8398
T: git git://anongit.freedesktop.org/drm-intel
+25
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+25
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
···
1013
1013
return 0;
1014
1014
}
1015
1015
1016
+
static int psp_dtm_unload(struct psp_context *psp)
1017
+
{
1018
+
int ret;
1019
+
struct psp_gfx_cmd_resp *cmd;
1020
+
1021
+
/*
1022
+
* TODO: bypass the unloading in sriov for now
1023
+
*/
1024
+
if (amdgpu_sriov_vf(psp->adev))
1025
+
return 0;
1026
+
1027
+
cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1028
+
if (!cmd)
1029
+
return -ENOMEM;
1030
+
1031
+
psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id);
1032
+
1033
+
ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1034
+
1035
+
kfree(cmd);
1036
+
1037
+
return ret;
1038
+
}
1039
+
1016
1040
int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1017
1041
{
1018
1042
/*
···
1061
1037
if (!psp->dtm_context.dtm_initialized)
1062
1038
return 0;
1063
1039
1064
-
ret = psp_hdcp_unload(psp);
1040
+
ret = psp_dtm_unload(psp);
1065
1041
if (ret)
1066
1042
return ret;
1067
1043
+2
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+2
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
···
3923
3923
{
3924
3924
uint64_t clock;
3925
3925
3926
+
amdgpu_gfx_off_ctrl(adev, false);
3926
3927
mutex_lock(&adev->gfx.gpu_clock_mutex);
3927
3928
WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3928
3929
clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3929
3930
((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3930
3931
mutex_unlock(&adev->gfx.gpu_clock_mutex);
3932
+
amdgpu_gfx_off_ctrl(adev, true);
3931
3933
return clock;
3932
3934
}
3933
3935
+11
-2
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+11
-2
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
···
1193
1193
return false;
1194
1194
}
1195
1195
1196
+
static bool is_raven_kicker(struct amdgpu_device *adev)
1197
+
{
1198
+
if (adev->pm.fw_version >= 0x41e2b)
1199
+
return true;
1200
+
else
1201
+
return false;
1202
+
}
1203
+
1196
1204
static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
1197
1205
{
1198
1206
if (gfx_v9_0_should_disable_gfxoff(adev->pdev))
···
1213
1205
break;
1214
1206
case CHIP_RAVEN:
1215
1207
if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) &&
1216
-
((adev->gfx.rlc_fw_version != 106 &&
1208
+
((!is_raven_kicker(adev) &&
1217
1209
adev->gfx.rlc_fw_version < 531) ||
1218
-
(adev->gfx.rlc_fw_version == 53815) ||
1219
1210
(adev->gfx.rlc_feature_version < 1) ||
1220
1211
!adev->gfx.rlc.is_rlc_v2_1))
1221
1212
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
···
3966
3959
{
3967
3960
uint64_t clock;
3968
3961
3962
+
amdgpu_gfx_off_ctrl(adev, false);
3969
3963
mutex_lock(&adev->gfx.gpu_clock_mutex);
3970
3964
if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {
3971
3965
uint32_t tmp, lsb, msb, i = 0;
···
3985
3977
((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3986
3978
}
3987
3979
mutex_unlock(&adev->gfx.gpu_clock_mutex);
3980
+
amdgpu_gfx_off_ctrl(adev, true);
3988
3981
return clock;
3989
3982
}
3990
3983
+6
-1
drivers/gpu/drm/amd/amdgpu/soc15.c
+6
-1
drivers/gpu/drm/amd/amdgpu/soc15.c
···
272
272
273
273
static u32 soc15_get_xclk(struct amdgpu_device *adev)
274
274
{
275
-
return adev->clock.spll.reference_freq;
275
+
u32 reference_clock = adev->clock.spll.reference_freq;
276
+
277
+
if (adev->asic_type == CHIP_RAVEN)
278
+
return reference_clock / 4;
279
+
280
+
return reference_clock;
276
281
}
277
282
278
283
+6
-4
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+6
-4
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
1911
1911
mutex_lock(&aconnector->hpd_lock);
1912
1912
1913
1913
#ifdef CONFIG_DRM_AMD_DC_HDCP
1914
-
if (adev->asic_type >= CHIP_RAVEN)
1914
+
if (adev->dm.hdcp_workqueue)
1915
1915
hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
1916
1916
#endif
1917
1917
if (aconnector->fake_enable)
···
2088
2088
}
2089
2089
}
2090
2090
#ifdef CONFIG_DRM_AMD_DC_HDCP
2091
-
if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ)
2092
-
hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
2091
+
if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
2092
+
if (adev->dm.hdcp_workqueue)
2093
+
hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
2094
+
}
2093
2095
#endif
2094
2096
if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2095
2097
(dc_link->type == dc_connection_mst_branch))
···
5704
5702
drm_connector_attach_vrr_capable_property(
5705
5703
&aconnector->base);
5706
5704
#ifdef CONFIG_DRM_AMD_DC_HDCP
5707
-
if (adev->asic_type >= CHIP_RAVEN)
5705
+
if (adev->dm.hdcp_workqueue)
5708
5706
drm_connector_attach_content_protection_property(&aconnector->base, true);
5709
5707
#endif
5710
5708
}
+2
-2
drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
+2
-2
drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
···
46
46
enum mod_hdcp_status status;
47
47
48
48
if (is_dp_hdcp(hdcp))
49
-
status = (hdcp->auth.msg.hdcp2.rxcaps_dp[2] & HDCP_2_2_RX_CAPS_VERSION_VAL) &&
50
-
HDCP_2_2_DP_HDCP_CAPABLE(hdcp->auth.msg.hdcp2.rxcaps_dp[0]) ?
49
+
status = (hdcp->auth.msg.hdcp2.rxcaps_dp[0] == HDCP_2_2_RX_CAPS_VERSION_VAL) &&
50
+
HDCP_2_2_DP_HDCP_CAPABLE(hdcp->auth.msg.hdcp2.rxcaps_dp[2]) ?
51
51
MOD_HDCP_STATUS_SUCCESS :
52
52
MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE;
53
53
else
+3
-3
drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+3
-3
drivers/gpu/drm/amd/powerplay/smu_v11_0.c
···
898
898
if (ret)
899
899
return ret;
900
900
901
+
bitmap_zero(feature->enabled, feature->feature_num);
902
+
bitmap_zero(feature->supported, feature->feature_num);
903
+
901
904
if (en) {
902
905
ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
903
906
if (ret)
···
910
907
feature->feature_num);
911
908
bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
912
909
feature->feature_num);
913
-
} else {
914
-
bitmap_zero(feature->enabled, feature->feature_num);
915
-
bitmap_zero(feature->supported, feature->feature_num);
916
910
}
917
911
918
912
return ret;
+4
-4
drivers/gpu/drm/bridge/tc358767.c
+4
-4
drivers/gpu/drm/bridge/tc358767.c
···
297
297
298
298
static int tc_aux_wait_busy(struct tc_data *tc)
299
299
{
300
-
return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 1000, 100000);
300
+
return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 100, 100000);
301
301
}
302
302
303
303
static int tc_aux_write_data(struct tc_data *tc, const void *data,
···
640
640
if (ret)
641
641
goto err;
642
642
643
-
ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 1000);
643
+
ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 100, 100000);
644
644
if (ret == -ETIMEDOUT) {
645
645
dev_err(tc->dev, "Timeout waiting for PHY to become ready");
646
646
return ret;
···
876
876
int ret;
877
877
878
878
ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE,
879
-
LT_LOOPDONE, 1, 1000);
879
+
LT_LOOPDONE, 500, 100000);
880
880
if (ret) {
881
881
dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n");
882
882
return ret;
···
949
949
dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
950
950
ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
951
951
952
-
ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 1000);
952
+
ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 500, 100000);
953
953
if (ret) {
954
954
dev_err(dev, "timeout waiting for phy become ready");
955
955
return ret;
+2
-1
drivers/gpu/drm/bridge/ti-tfp410.c
+2
-1
drivers/gpu/drm/bridge/ti-tfp410.c
+2
-1
drivers/gpu/drm/drm_client_modeset.c
+2
-1
drivers/gpu/drm/drm_client_modeset.c
···
951
951
* depending on the hardware this may require the framebuffer
952
952
* to be in a specific tiling format.
953
953
*/
954
-
if ((*rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_180 ||
954
+
if (((*rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0 &&
955
+
(*rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_180) ||
955
956
!plane->rotation_property)
956
957
return false;
957
958
+7
drivers/gpu/drm/drm_modes.c
+7
drivers/gpu/drm/drm_modes.c
···
1698
1698
if (rotation && freestanding)
1699
1699
return -EINVAL;
1700
1700
1701
+
if (!(rotation & DRM_MODE_ROTATE_MASK))
1702
+
rotation |= DRM_MODE_ROTATE_0;
1703
+
1704
+
/* Make sure there is exactly one rotation defined */
1705
+
if (!is_power_of_2(rotation & DRM_MODE_ROTATE_MASK))
1706
+
return -EINVAL;
1707
+
1701
1708
mode->rotation_reflection = rotation;
1702
1709
1703
1710
return 0;
+2
-3
drivers/gpu/drm/i915/Kconfig
+2
-3
drivers/gpu/drm/i915/Kconfig
···
75
75
help
76
76
This option enables capturing the GPU state when a hang is detected.
77
77
This information is vital for triaging hangs and assists in debugging.
78
-
Please report any hang to
79
-
https://bugs.freedesktop.org/enter_bug.cgi?product=DRI
80
-
for triaging.
78
+
Please report any hang for triaging according to:
79
+
https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs
81
80
82
81
If in doubt, say "Y".
83
82
+3
-1
drivers/gpu/drm/i915/display/intel_ddi.c
+3
-1
drivers/gpu/drm/i915/display/intel_ddi.c
···
4251
4251
void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
4252
4252
struct intel_crtc_state *crtc_state)
4253
4253
{
4254
-
if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
4254
+
if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000)
4255
+
crtc_state->min_voltage_level = 3;
4256
+
else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
4255
4257
crtc_state->min_voltage_level = 1;
4256
4258
else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
4257
4259
crtc_state->min_voltage_level = 2;
+19
-1
drivers/gpu/drm/i915/display/intel_display.c
+19
-1
drivers/gpu/drm/i915/display/intel_display.c
···
11087
11087
u32 base;
11088
11088
11089
11089
if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
11090
-
base = obj->phys_handle->busaddr;
11090
+
base = sg_dma_address(obj->mm.pages->sgl);
11091
11091
else
11092
11092
base = intel_plane_ggtt_offset(plane_state);
11093
11093
···
17433
17433
* have readout for pipe gamma enable.
17434
17434
*/
17435
17435
crtc_state->uapi.color_mgmt_changed = true;
17436
+
17437
+
/*
17438
+
* FIXME hack to force full modeset when DSC is being
17439
+
* used.
17440
+
*
17441
+
* As long as we do not have full state readout and
17442
+
* config comparison of crtc_state->dsc, we have no way
17443
+
* to ensure reliable fastset. Remove once we have
17444
+
* readout for DSC.
17445
+
*/
17446
+
if (crtc_state->dsc.compression_enable) {
17447
+
ret = drm_atomic_add_affected_connectors(state,
17448
+
&crtc->base);
17449
+
if (ret)
17450
+
goto out;
17451
+
crtc_state->uapi.mode_changed = true;
17452
+
drm_dbg_kms(dev, "Force full modeset for DSC\n");
17453
+
}
17436
17454
}
17437
17455
}
17438
17456
+16
drivers/gpu/drm/i915/gem/i915_gem_context.c
+16
drivers/gpu/drm/i915/gem/i915_gem_context.c
···
565
565
if (!(ctx->i915->caps.scheduler & I915_SCHEDULER_CAP_PREEMPTION))
566
566
return -ENODEV;
567
567
568
+
/*
569
+
* If the cancel fails, we then need to reset, cleanly!
570
+
*
571
+
* If the per-engine reset fails, all hope is lost! We resort
572
+
* to a full GPU reset in that unlikely case, but realistically
573
+
* if the engine could not reset, the full reset does not fare
574
+
* much better. The damage has been done.
575
+
*
576
+
* However, if we cannot reset an engine by itself, we cannot
577
+
* cleanup a hanging persistent context without causing
578
+
* colateral damage, and we should not pretend we can by
579
+
* exposing the interface.
580
+
*/
581
+
if (!intel_has_reset_engine(&ctx->i915->gt))
582
+
return -ENODEV;
583
+
568
584
i915_gem_context_clear_persistence(ctx);
569
585
}
570
586
-3
drivers/gpu/drm/i915/gem/i915_gem_object_types.h
-3
drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+53
-51
drivers/gpu/drm/i915/gem/i915_gem_phys.c
+53
-51
drivers/gpu/drm/i915/gem/i915_gem_phys.c
···
22
22
static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
23
23
{
24
24
struct address_space *mapping = obj->base.filp->f_mapping;
25
-
struct drm_dma_handle *phys;
26
-
struct sg_table *st;
27
25
struct scatterlist *sg;
28
-
char *vaddr;
26
+
struct sg_table *st;
27
+
dma_addr_t dma;
28
+
void *vaddr;
29
+
void *dst;
29
30
int i;
30
-
int err;
31
31
32
32
if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
33
33
return -EINVAL;
34
34
35
-
/* Always aligning to the object size, allows a single allocation
35
+
/*
36
+
* Always aligning to the object size, allows a single allocation
36
37
* to handle all possible callers, and given typical object sizes,
37
38
* the alignment of the buddy allocation will naturally match.
38
39
*/
39
-
phys = drm_pci_alloc(obj->base.dev,
40
-
roundup_pow_of_two(obj->base.size),
41
-
roundup_pow_of_two(obj->base.size));
42
-
if (!phys)
40
+
vaddr = dma_alloc_coherent(&obj->base.dev->pdev->dev,
41
+
roundup_pow_of_two(obj->base.size),
42
+
&dma, GFP_KERNEL);
43
+
if (!vaddr)
43
44
return -ENOMEM;
44
45
45
-
vaddr = phys->vaddr;
46
-
for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
47
-
struct page *page;
48
-
char *src;
49
-
50
-
page = shmem_read_mapping_page(mapping, i);
51
-
if (IS_ERR(page)) {
52
-
err = PTR_ERR(page);
53
-
goto err_phys;
54
-
}
55
-
56
-
src = kmap_atomic(page);
57
-
memcpy(vaddr, src, PAGE_SIZE);
58
-
drm_clflush_virt_range(vaddr, PAGE_SIZE);
59
-
kunmap_atomic(src);
60
-
61
-
put_page(page);
62
-
vaddr += PAGE_SIZE;
63
-
}
64
-
65
-
intel_gt_chipset_flush(&to_i915(obj->base.dev)->gt);
66
-
67
46
st = kmalloc(sizeof(*st), GFP_KERNEL);
68
-
if (!st) {
69
-
err = -ENOMEM;
70
-
goto err_phys;
71
-
}
47
+
if (!st)
48
+
goto err_pci;
72
49
73
-
if (sg_alloc_table(st, 1, GFP_KERNEL)) {
74
-
kfree(st);
75
-
err = -ENOMEM;
76
-
goto err_phys;
77
-
}
50
+
if (sg_alloc_table(st, 1, GFP_KERNEL))
51
+
goto err_st;
78
52
79
53
sg = st->sgl;
80
54
sg->offset = 0;
81
55
sg->length = obj->base.size;
82
56
83
-
sg_dma_address(sg) = phys->busaddr;
57
+
sg_assign_page(sg, (struct page *)vaddr);
58
+
sg_dma_address(sg) = dma;
84
59
sg_dma_len(sg) = obj->base.size;
85
60
86
-
obj->phys_handle = phys;
61
+
dst = vaddr;
62
+
for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
63
+
struct page *page;
64
+
void *src;
65
+
66
+
page = shmem_read_mapping_page(mapping, i);
67
+
if (IS_ERR(page))
68
+
goto err_st;
69
+
70
+
src = kmap_atomic(page);
71
+
memcpy(dst, src, PAGE_SIZE);
72
+
drm_clflush_virt_range(dst, PAGE_SIZE);
73
+
kunmap_atomic(src);
74
+
75
+
put_page(page);
76
+
dst += PAGE_SIZE;
77
+
}
78
+
79
+
intel_gt_chipset_flush(&to_i915(obj->base.dev)->gt);
87
80
88
81
__i915_gem_object_set_pages(obj, st, sg->length);
89
82
90
83
return 0;
91
84
92
-
err_phys:
93
-
drm_pci_free(obj->base.dev, phys);
94
-
95
-
return err;
85
+
err_st:
86
+
kfree(st);
87
+
err_pci:
88
+
dma_free_coherent(&obj->base.dev->pdev->dev,
89
+
roundup_pow_of_two(obj->base.size),
90
+
vaddr, dma);
91
+
return -ENOMEM;
96
92
}
97
93
98
94
static void
99
95
i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
100
96
struct sg_table *pages)
101
97
{
98
+
dma_addr_t dma = sg_dma_address(pages->sgl);
99
+
void *vaddr = sg_page(pages->sgl);
100
+
102
101
__i915_gem_object_release_shmem(obj, pages, false);
103
102
104
103
if (obj->mm.dirty) {
105
104
struct address_space *mapping = obj->base.filp->f_mapping;
106
-
char *vaddr = obj->phys_handle->vaddr;
105
+
void *src = vaddr;
107
106
int i;
108
107
109
108
for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
···
114
115
continue;
115
116
116
117
dst = kmap_atomic(page);
117
-
drm_clflush_virt_range(vaddr, PAGE_SIZE);
118
-
memcpy(dst, vaddr, PAGE_SIZE);
118
+
drm_clflush_virt_range(src, PAGE_SIZE);
119
+
memcpy(dst, src, PAGE_SIZE);
119
120
kunmap_atomic(dst);
120
121
121
122
set_page_dirty(page);
122
123
if (obj->mm.madv == I915_MADV_WILLNEED)
123
124
mark_page_accessed(page);
124
125
put_page(page);
125
-
vaddr += PAGE_SIZE;
126
+
127
+
src += PAGE_SIZE;
126
128
}
127
129
obj->mm.dirty = false;
128
130
}
···
131
131
sg_free_table(pages);
132
132
kfree(pages);
133
133
134
-
drm_pci_free(obj->base.dev, obj->phys_handle);
134
+
dma_free_coherent(&obj->base.dev->pdev->dev,
135
+
roundup_pow_of_two(obj->base.size),
136
+
vaddr, dma);
135
137
}
136
138
137
139
static void phys_release(struct drm_i915_gem_object *obj)
+3
drivers/gpu/drm/i915/gt/intel_gt_requests.c
+3
drivers/gpu/drm/i915/gt/intel_gt_requests.c
···
99
99
void intel_engine_add_retire(struct intel_engine_cs *engine,
100
100
struct intel_timeline *tl)
101
101
{
102
+
/* We don't deal well with the engine disappearing beneath us */
103
+
GEM_BUG_ON(intel_engine_is_virtual(engine));
104
+
102
105
if (add_retire(engine, tl))
103
106
schedule_work(&engine->retire_work);
104
107
}
+31
-30
drivers/gpu/drm/i915/gt/intel_lrc.c
+31
-30
drivers/gpu/drm/i915/gt/intel_lrc.c
···
237
237
bool close);
238
238
static void
239
239
__execlists_update_reg_state(const struct intel_context *ce,
240
-
const struct intel_engine_cs *engine);
240
+
const struct intel_engine_cs *engine,
241
+
u32 head);
241
242
242
243
static void mark_eio(struct i915_request *rq)
243
244
{
···
1187
1186
head = rq->tail;
1188
1187
else
1189
1188
head = active_request(ce->timeline, rq)->head;
1190
-
ce->ring->head = intel_ring_wrap(ce->ring, head);
1191
-
intel_ring_update_space(ce->ring);
1189
+
head = intel_ring_wrap(ce->ring, head);
1192
1190
1193
1191
/* Scrub the context image to prevent replaying the previous batch */
1194
1192
restore_default_state(ce, engine);
1195
-
__execlists_update_reg_state(ce, engine);
1193
+
__execlists_update_reg_state(ce, engine, head);
1196
1194
1197
1195
/* We've switched away, so this should be a no-op, but intent matters */
1198
1196
ce->lrc_desc |= CTX_DESC_FORCE_RESTORE;
···
1321
1321
{
1322
1322
struct intel_context *ce = rq->context;
1323
1323
u64 desc = ce->lrc_desc;
1324
-
u32 tail;
1324
+
u32 tail, prev;
1325
1325
1326
1326
/*
1327
1327
* WaIdleLiteRestore:bdw,skl
···
1334
1334
* subsequent resubmissions (for lite restore). Should that fail us,
1335
1335
* and we try and submit the same tail again, force the context
1336
1336
* reload.
1337
+
*
1338
+
* If we need to return to a preempted context, we need to skip the
1339
+
* lite-restore and force it to reload the RING_TAIL. Otherwise, the
1340
+
* HW has a tendency to ignore us rewinding the TAIL to the end of
1341
+
* an earlier request.
1337
1342
*/
1338
1343
tail = intel_ring_set_tail(rq->ring, rq->tail);
1339
-
if (unlikely(ce->lrc_reg_state[CTX_RING_TAIL] == tail))
1344
+
prev = ce->lrc_reg_state[CTX_RING_TAIL];
1345
+
if (unlikely(intel_ring_direction(rq->ring, tail, prev) <= 0))
1340
1346
desc |= CTX_DESC_FORCE_RESTORE;
1341
1347
ce->lrc_reg_state[CTX_RING_TAIL] = tail;
1342
1348
rq->tail = rq->wa_tail;
···
1611
1605
return *last;
1612
1606
}
1613
1607
1608
+
#define for_each_waiter(p__, rq__) \
1609
+
list_for_each_entry_lockless(p__, \
1610
+
&(rq__)->sched.waiters_list, \
1611
+
wait_link)
1612
+
1614
1613
static void defer_request(struct i915_request *rq, struct list_head * const pl)
1615
1614
{
1616
1615
LIST_HEAD(list);
···
1633
1622
GEM_BUG_ON(i915_request_is_active(rq));
1634
1623
list_move_tail(&rq->sched.link, pl);
1635
1624
1636
-
list_for_each_entry(p, &rq->sched.waiters_list, wait_link) {
1625
+
for_each_waiter(p, rq) {
1637
1626
struct i915_request *w =
1638
1627
container_of(p->waiter, typeof(*w), sched);
1639
1628
···
1845
1834
*/
1846
1835
__unwind_incomplete_requests(engine);
1847
1836
1848
-
/*
1849
-
* If we need to return to the preempted context, we
1850
-
* need to skip the lite-restore and force it to
1851
-
* reload the RING_TAIL. Otherwise, the HW has a
1852
-
* tendency to ignore us rewinding the TAIL to the
1853
-
* end of an earlier request.
1854
-
*/
1855
-
last->context->lrc_desc |= CTX_DESC_FORCE_RESTORE;
1856
1837
last = NULL;
1857
1838
} else if (need_timeslice(engine, last) &&
1858
1839
timer_expired(&engine->execlists.timer)) {
···
2863
2860
2864
2861
static void
2865
2862
__execlists_update_reg_state(const struct intel_context *ce,
2866
-
const struct intel_engine_cs *engine)
2863
+
const struct intel_engine_cs *engine,
2864
+
u32 head)
2867
2865
{
2868
2866
struct intel_ring *ring = ce->ring;
2869
2867
u32 *regs = ce->lrc_reg_state;
2870
2868
2871
-
GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
2869
+
GEM_BUG_ON(!intel_ring_offset_valid(ring, head));
2872
2870
GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
2873
2871
2874
2872
regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
2875
-
regs[CTX_RING_HEAD] = ring->head;
2873
+
regs[CTX_RING_HEAD] = head;
2876
2874
regs[CTX_RING_TAIL] = ring->tail;
2877
2875
2878
2876
/* RPCS */
···
2902
2898
2903
2899
ce->lrc_desc = lrc_descriptor(ce, engine) | CTX_DESC_FORCE_RESTORE;
2904
2900
ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
2905
-
__execlists_update_reg_state(ce, engine);
2901
+
__execlists_update_reg_state(ce, engine, ce->ring->tail);
2906
2902
2907
2903
return 0;
2908
2904
}
···
2943
2939
/* Scrub away the garbage */
2944
2940
execlists_init_reg_state(ce->lrc_reg_state,
2945
2941
ce, ce->engine, ce->ring, true);
2946
-
__execlists_update_reg_state(ce, ce->engine);
2942
+
__execlists_update_reg_state(ce, ce->engine, ce->ring->tail);
2947
2943
2948
2944
ce->lrc_desc |= CTX_DESC_FORCE_RESTORE;
2949
2945
}
···
3498
3494
struct intel_engine_execlists * const execlists = &engine->execlists;
3499
3495
struct intel_context *ce;
3500
3496
struct i915_request *rq;
3497
+
u32 head;
3501
3498
3502
3499
mb(); /* paranoia: read the CSB pointers from after the reset */
3503
3500
clflush(execlists->csb_write);
···
3526
3521
3527
3522
if (i915_request_completed(rq)) {
3528
3523
/* Idle context; tidy up the ring so we can restart afresh */
3529
-
ce->ring->head = intel_ring_wrap(ce->ring, rq->tail);
3524
+
head = intel_ring_wrap(ce->ring, rq->tail);
3530
3525
goto out_replay;
3531
3526
}
3532
3527
3533
3528
/* Context has requests still in-flight; it should not be idle! */
3534
3529
GEM_BUG_ON(i915_active_is_idle(&ce->active));
3535
3530
rq = active_request(ce->timeline, rq);
3536
-
ce->ring->head = intel_ring_wrap(ce->ring, rq->head);
3537
-
GEM_BUG_ON(ce->ring->head == ce->ring->tail);
3531
+
head = intel_ring_wrap(ce->ring, rq->head);
3532
+
GEM_BUG_ON(head == ce->ring->tail);
3538
3533
3539
3534
/*
3540
3535
* If this request hasn't started yet, e.g. it is waiting on a
···
3579
3574
3580
3575
out_replay:
3581
3576
ENGINE_TRACE(engine, "replay {head:%04x, tail:%04x}\n",
3582
-
ce->ring->head, ce->ring->tail);
3583
-
intel_ring_update_space(ce->ring);
3577
+
head, ce->ring->tail);
3584
3578
__execlists_reset_reg_state(ce, engine);
3585
-
__execlists_update_reg_state(ce, engine);
3579
+
__execlists_update_reg_state(ce, engine, head);
3586
3580
ce->lrc_desc |= CTX_DESC_FORCE_RESTORE; /* paranoid: GPU was reset! */
3587
3581
3588
3582
unwind:
···
5224
5220
restore_default_state(ce, engine);
5225
5221
5226
5222
/* Rerun the request; its payload has been neutered (if guilty). */
5227
-
ce->ring->head = head;
5228
-
intel_ring_update_space(ce->ring);
5229
-
5230
-
__execlists_update_reg_state(ce, engine);
5223
+
__execlists_update_reg_state(ce, engine, head);
5231
5224
}
5232
5225
5233
5226
bool
+1
drivers/gpu/drm/i915/gt/intel_ring.c
+1
drivers/gpu/drm/i915/gt/intel_ring.c
+8
drivers/gpu/drm/i915/gt/intel_ring.h
+8
drivers/gpu/drm/i915/gt/intel_ring.h
···
56
56
return pos & (ring->size - 1);
57
57
}
58
58
59
+
static inline int intel_ring_direction(const struct intel_ring *ring,
60
+
u32 next, u32 prev)
61
+
{
62
+
typecheck(typeof(ring->size), next);
63
+
typecheck(typeof(ring->size), prev);
64
+
return (next - prev) << ring->wrap;
65
+
}
66
+
59
67
static inline bool
60
68
intel_ring_offset_valid(const struct intel_ring *ring,
61
69
unsigned int pos)
+4
-3
drivers/gpu/drm/i915/gt/intel_ring_types.h
+4
-3
drivers/gpu/drm/i915/gt/intel_ring_types.h
···
39
39
*/
40
40
atomic_t pin_count;
41
41
42
-
u32 head;
43
-
u32 tail;
44
-
u32 emit;
42
+
u32 head; /* updated during retire, loosely tracks RING_HEAD */
43
+
u32 tail; /* updated on submission, used for RING_TAIL */
44
+
u32 emit; /* updated during request construction */
45
45
46
46
u32 space;
47
47
u32 size;
48
+
u32 wrap;
48
49
u32 effective_size;
49
50
};
50
51
+1
-1
drivers/gpu/drm/i915/gt/selftest_lrc.c
+1
-1
drivers/gpu/drm/i915/gt/selftest_lrc.c
···
186
186
}
187
187
GEM_BUG_ON(!ce[1]->ring->size);
188
188
intel_ring_reset(ce[1]->ring, ce[1]->ring->size / 2);
189
-
__execlists_update_reg_state(ce[1], engine);
189
+
__execlists_update_reg_state(ce[1], engine, ce[1]->ring->head);
190
190
191
191
rq[0] = igt_spinner_create_request(&spin, ce[0], MI_ARB_CHECK);
192
192
if (IS_ERR(rq[0])) {
+4
-4
drivers/gpu/drm/i915/i915_gem.c
+4
-4
drivers/gpu/drm/i915/i915_gem.c
···
180
180
struct drm_i915_gem_pwrite *args,
181
181
struct drm_file *file)
182
182
{
183
-
void *vaddr = obj->phys_handle->vaddr + args->offset;
183
+
void *vaddr = sg_page(obj->mm.pages->sgl) + args->offset;
184
184
char __user *user_data = u64_to_user_ptr(args->data_ptr);
185
185
186
186
/*
···
844
844
ret = i915_gem_gtt_pwrite_fast(obj, args);
845
845
846
846
if (ret == -EFAULT || ret == -ENOSPC) {
847
-
if (obj->phys_handle)
848
-
ret = i915_gem_phys_pwrite(obj, args, file);
849
-
else
847
+
if (i915_gem_object_has_struct_page(obj))
850
848
ret = i915_gem_shmem_pwrite(obj, args);
849
+
else
850
+
ret = i915_gem_phys_pwrite(obj, args, file);
851
851
}
852
852
853
853
i915_gem_object_unpin_pages(obj);
+2
-1
drivers/gpu/drm/i915/i915_gpu_error.c
+2
-1
drivers/gpu/drm/i915/i915_gpu_error.c
···
1852
1852
if (!xchg(&warned, true) &&
1853
1853
ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1854
1854
pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1855
-
pr_info("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1855
+
pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n");
1856
+
pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n");
1856
1857
pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1857
1858
pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n");
1858
1859
pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n",
+14
-7
drivers/gpu/drm/i915/i915_request.c
+14
-7
drivers/gpu/drm/i915/i915_request.c
···
595
595
i915_sw_fence_init(&rq->submit, submit_notify);
596
596
i915_sw_fence_init(&rq->semaphore, semaphore_notify);
597
597
598
+
dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock, 0, 0);
599
+
598
600
rq->file_priv = NULL;
599
601
rq->capture_list = NULL;
600
602
···
655
653
}
656
654
}
657
655
658
-
ret = intel_timeline_get_seqno(tl, rq, &seqno);
659
-
if (ret)
660
-
goto err_free;
661
-
662
656
rq->i915 = ce->engine->i915;
663
657
rq->context = ce;
664
658
rq->engine = ce->engine;
665
659
rq->ring = ce->ring;
666
660
rq->execution_mask = ce->engine->mask;
667
661
662
+
kref_init(&rq->fence.refcount);
663
+
rq->fence.flags = 0;
664
+
rq->fence.error = 0;
665
+
INIT_LIST_HEAD(&rq->fence.cb_list);
666
+
667
+
ret = intel_timeline_get_seqno(tl, rq, &seqno);
668
+
if (ret)
669
+
goto err_free;
670
+
671
+
rq->fence.context = tl->fence_context;
672
+
rq->fence.seqno = seqno;
673
+
668
674
RCU_INIT_POINTER(rq->timeline, tl);
669
675
RCU_INIT_POINTER(rq->hwsp_cacheline, tl->hwsp_cacheline);
670
676
rq->hwsp_seqno = tl->hwsp_seqno;
671
677
672
678
rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
673
-
674
-
dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock,
675
-
tl->fence_context, seqno);
676
679
677
680
/* We bump the ref for the fence chain */
678
681
i915_sw_fence_reinit(&i915_request_get(rq)->submit);
+4
-2
drivers/gpu/drm/i915/i915_scheduler.c
+4
-2
drivers/gpu/drm/i915/i915_scheduler.c
···
423
423
424
424
if (!node_signaled(signal)) {
425
425
INIT_LIST_HEAD(&dep->dfs_link);
426
-
list_add(&dep->wait_link, &signal->waiters_list);
427
-
list_add(&dep->signal_link, &node->signalers_list);
428
426
dep->signaler = signal;
429
427
dep->waiter = node;
430
428
dep->flags = flags;
···
431
433
if (signal->flags & I915_SCHED_HAS_SEMAPHORE_CHAIN &&
432
434
!node_started(signal))
433
435
node->flags |= I915_SCHED_HAS_SEMAPHORE_CHAIN;
436
+
437
+
/* All set, now publish. Beware the lockless walkers. */
438
+
list_add(&dep->signal_link, &node->signalers_list);
439
+
list_add_rcu(&dep->wait_link, &signal->waiters_list);
434
440
435
441
/*
436
442
* As we do not allow WAIT to preempt inflight requests,
+2
-3
drivers/gpu/drm/i915/i915_utils.c
+2
-3
drivers/gpu/drm/i915/i915_utils.c
···
8
8
#include "i915_drv.h"
9
9
#include "i915_utils.h"
10
10
11
-
#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
12
-
#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
13
-
"providing the dmesg log by booting with drm.debug=0xf"
11
+
#define FDO_BUG_URL "https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs"
12
+
#define FDO_BUG_MSG "Please file a bug on drm/i915; see " FDO_BUG_URL " for details."
14
13
15
14
void
16
15
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
+31
-6
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+31
-6
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
···
796
796
return true;
797
797
}
798
798
799
+
#define GBIF_CLIENT_HALT_MASK BIT(0)
800
+
#define GBIF_ARB_HALT_MASK BIT(1)
801
+
802
+
static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu)
803
+
{
804
+
struct msm_gpu *gpu = &adreno_gpu->base;
805
+
806
+
if (!a6xx_has_gbif(adreno_gpu)) {
807
+
gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
808
+
spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
809
+
0xf) == 0xf);
810
+
gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
811
+
812
+
return;
813
+
}
814
+
815
+
/* Halt new client requests on GBIF */
816
+
gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
817
+
spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
818
+
(GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK);
819
+
820
+
/* Halt all AXI requests on GBIF */
821
+
gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
822
+
spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
823
+
(GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK);
824
+
825
+
/* The GBIF halt needs to be explicitly cleared */
826
+
gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
827
+
}
828
+
799
829
/* Gracefully try to shut down the GMU and by extension the GPU */
800
830
static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu)
801
831
{
802
832
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
803
833
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
804
-
struct msm_gpu *gpu = &adreno_gpu->base;
805
834
u32 val;
806
835
807
836
/*
···
848
819
return;
849
820
}
850
821
851
-
/* Clear the VBIF pipe before shutting down */
852
-
gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
853
-
spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 0xf)
854
-
== 0xf);
855
-
gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
822
+
a6xx_bus_clear_pending_transactions(adreno_gpu);
856
823
857
824
/* tell the GMU we want to slumber */
858
825
a6xx_gmu_notify_slumber(gmu);
+6
-59
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+6
-59
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
···
378
378
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
379
379
int ret;
380
380
381
-
/*
382
-
* During a previous slumber, GBIF halt is asserted to ensure
383
-
* no further transaction can go through GPU before GPU
384
-
* headswitch is turned off.
385
-
*
386
-
* This halt is deasserted once headswitch goes off but
387
-
* incase headswitch doesn't goes off clear GBIF halt
388
-
* here to ensure GPU wake-up doesn't fail because of
389
-
* halted GPU transactions.
390
-
*/
391
-
gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
392
-
393
381
/* Make sure the GMU keeps the GPU on while we set it up */
394
382
a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
395
383
···
458
470
/* Select CP0 to always count cycles */
459
471
gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
460
472
461
-
gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1);
462
-
gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1);
463
-
gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1);
464
-
gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21);
473
+
if (adreno_is_a630(adreno_gpu)) {
474
+
gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1);
475
+
gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1);
476
+
gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1);
477
+
gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21);
478
+
}
465
479
466
480
/* Enable fault detection */
467
481
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL,
···
738
748
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_A6XX_CP_RB_CNTL),
739
749
};
740
750
741
-
#define GBIF_CLIENT_HALT_MASK BIT(0)
742
-
#define GBIF_ARB_HALT_MASK BIT(1)
743
-
744
-
static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu)
745
-
{
746
-
struct msm_gpu *gpu = &adreno_gpu->base;
747
-
748
-
if(!a6xx_has_gbif(adreno_gpu)){
749
-
gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
750
-
spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
751
-
0xf) == 0xf);
752
-
gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
753
-
754
-
return;
755
-
}
756
-
757
-
/* Halt new client requests on GBIF */
758
-
gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
759
-
spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
760
-
(GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK);
761
-
762
-
/* Halt all AXI requests on GBIF */
763
-
gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
764
-
spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
765
-
(GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK);
766
-
767
-
/*
768
-
* GMU needs DDR access in slumber path. Deassert GBIF halt now
769
-
* to allow for GMU to access system memory.
770
-
*/
771
-
gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
772
-
}
773
-
774
751
static int a6xx_pm_resume(struct msm_gpu *gpu)
775
752
{
776
753
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
···
761
804
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
762
805
763
806
devfreq_suspend_device(gpu->devfreq.devfreq);
764
-
765
-
/*
766
-
* Make sure the GMU is idle before continuing (because some transitions
767
-
* may use VBIF
768
-
*/
769
-
a6xx_gmu_wait_for_idle(&a6xx_gpu->gmu);
770
-
771
-
/* Clear the VBIF pipe before shutting down */
772
-
/* FIXME: This accesses the GPU - do we need to make sure it is on? */
773
-
a6xx_bus_clear_pending_transactions(adreno_gpu);
774
807
775
808
return a6xx_gmu_stop(a6xx_gpu);
776
809
}
+60
-25
drivers/gpu/drm/msm/adreno/a6xx_hfi.c
+60
-25
drivers/gpu/drm/msm/adreno/a6xx_hfi.c
···
7
7
8
8
#include "a6xx_gmu.h"
9
9
#include "a6xx_gmu.xml.h"
10
+
#include "a6xx_gpu.h"
10
11
11
12
#define HFI_MSG_ID(val) [val] = #val
12
13
···
217
216
NULL, 0);
218
217
}
219
218
220
-
static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
219
+
static void a618_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
221
220
{
222
-
struct a6xx_hfi_msg_bw_table msg = { 0 };
221
+
/* Send a single "off" entry since the 618 GMU doesn't do bus scaling */
222
+
msg->bw_level_num = 1;
223
+
224
+
msg->ddr_cmds_num = 3;
225
+
msg->ddr_wait_bitmask = 0x01;
226
+
227
+
msg->ddr_cmds_addrs[0] = 0x50000;
228
+
msg->ddr_cmds_addrs[1] = 0x5003c;
229
+
msg->ddr_cmds_addrs[2] = 0x5000c;
230
+
231
+
msg->ddr_cmds_data[0][0] = 0x40000000;
232
+
msg->ddr_cmds_data[0][1] = 0x40000000;
233
+
msg->ddr_cmds_data[0][2] = 0x40000000;
223
234
224
235
/*
225
-
* The sdm845 GMU doesn't do bus frequency scaling on its own but it
226
-
* does need at least one entry in the list because it might be accessed
227
-
* when the GMU is shutting down. Send a single "off" entry.
236
+
* These are the CX (CNOC) votes - these are used by the GMU but the
237
+
* votes are known and fixed for the target
228
238
*/
239
+
msg->cnoc_cmds_num = 1;
240
+
msg->cnoc_wait_bitmask = 0x01;
229
241
230
-
msg.bw_level_num = 1;
242
+
msg->cnoc_cmds_addrs[0] = 0x5007c;
243
+
msg->cnoc_cmds_data[0][0] = 0x40000000;
244
+
msg->cnoc_cmds_data[1][0] = 0x60000001;
245
+
}
231
246
232
-
msg.ddr_cmds_num = 3;
233
-
msg.ddr_wait_bitmask = 0x07;
247
+
static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
248
+
{
249
+
/* Send a single "off" entry since the 630 GMU doesn't do bus scaling */
250
+
msg->bw_level_num = 1;
234
251
235
-
msg.ddr_cmds_addrs[0] = 0x50000;
236
-
msg.ddr_cmds_addrs[1] = 0x5005c;
237
-
msg.ddr_cmds_addrs[2] = 0x5000c;
252
+
msg->ddr_cmds_num = 3;
253
+
msg->ddr_wait_bitmask = 0x07;
238
254
239
-
msg.ddr_cmds_data[0][0] = 0x40000000;
240
-
msg.ddr_cmds_data[0][1] = 0x40000000;
241
-
msg.ddr_cmds_data[0][2] = 0x40000000;
255
+
msg->ddr_cmds_addrs[0] = 0x50000;
256
+
msg->ddr_cmds_addrs[1] = 0x5005c;
257
+
msg->ddr_cmds_addrs[2] = 0x5000c;
258
+
259
+
msg->ddr_cmds_data[0][0] = 0x40000000;
260
+
msg->ddr_cmds_data[0][1] = 0x40000000;
261
+
msg->ddr_cmds_data[0][2] = 0x40000000;
242
262
243
263
/*
244
264
* These are the CX (CNOC) votes. This is used but the values for the
245
265
* sdm845 GMU are known and fixed so we can hard code them.
246
266
*/
247
267
248
-
msg.cnoc_cmds_num = 3;
249
-
msg.cnoc_wait_bitmask = 0x05;
268
+
msg->cnoc_cmds_num = 3;
269
+
msg->cnoc_wait_bitmask = 0x05;
250
270
251
-
msg.cnoc_cmds_addrs[0] = 0x50034;
252
-
msg.cnoc_cmds_addrs[1] = 0x5007c;
253
-
msg.cnoc_cmds_addrs[2] = 0x5004c;
271
+
msg->cnoc_cmds_addrs[0] = 0x50034;
272
+
msg->cnoc_cmds_addrs[1] = 0x5007c;
273
+
msg->cnoc_cmds_addrs[2] = 0x5004c;
254
274
255
-
msg.cnoc_cmds_data[0][0] = 0x40000000;
256
-
msg.cnoc_cmds_data[0][1] = 0x00000000;
257
-
msg.cnoc_cmds_data[0][2] = 0x40000000;
275
+
msg->cnoc_cmds_data[0][0] = 0x40000000;
276
+
msg->cnoc_cmds_data[0][1] = 0x00000000;
277
+
msg->cnoc_cmds_data[0][2] = 0x40000000;
258
278
259
-
msg.cnoc_cmds_data[1][0] = 0x60000001;
260
-
msg.cnoc_cmds_data[1][1] = 0x20000001;
261
-
msg.cnoc_cmds_data[1][2] = 0x60000001;
279
+
msg->cnoc_cmds_data[1][0] = 0x60000001;
280
+
msg->cnoc_cmds_data[1][1] = 0x20000001;
281
+
msg->cnoc_cmds_data[1][2] = 0x60000001;
282
+
}
283
+
284
+
285
+
static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
286
+
{
287
+
struct a6xx_hfi_msg_bw_table msg = { 0 };
288
+
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
289
+
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
290
+
291
+
if (adreno_is_a618(adreno_gpu))
292
+
a618_build_bw_table(&msg);
293
+
else
294
+
a6xx_build_bw_table(&msg);
262
295
263
296
return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_BW_TABLE, &msg, sizeof(msg),
264
297
NULL, 0);
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
···
255
255
256
256
INTERLEAVED_RGB_FMT(RGB565,
257
257
0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
258
-
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
258
+
C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
259
259
false, 2, 0,
260
260
DPU_FETCH_LINEAR, 1),
261
261
262
262
INTERLEAVED_RGB_FMT(BGR565,
263
263
0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
264
-
C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
264
+
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
265
265
false, 2, 0,
266
266
DPU_FETCH_LINEAR, 1),
267
267
+57
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
+57
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
···
12
12
13
13
#define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)
14
14
15
+
#define HW_REV 0x0
15
16
#define HW_INTR_STATUS 0x0010
16
17
17
18
/* Max BW defined in KBps */
···
21
20
struct dpu_irq_controller {
22
21
unsigned long enabled_mask;
23
22
struct irq_domain *domain;
23
+
};
24
+
25
+
struct dpu_hw_cfg {
26
+
u32 val;
27
+
u32 offset;
28
+
};
29
+
30
+
struct dpu_mdss_hw_init_handler {
31
+
u32 hw_rev;
32
+
u32 hw_reg_count;
33
+
struct dpu_hw_cfg* hw_cfg;
24
34
};
25
35
26
36
struct dpu_mdss {
···
43
31
struct icc_path *path[2];
44
32
u32 num_paths;
45
33
};
34
+
35
+
static struct dpu_hw_cfg hw_cfg[] = {
36
+
{
37
+
/* UBWC global settings */
38
+
.val = 0x1E,
39
+
.offset = 0x144,
40
+
}
41
+
};
42
+
43
+
static struct dpu_mdss_hw_init_handler cfg_handler[] = {
44
+
{ .hw_rev = DPU_HW_VER_620,
45
+
.hw_reg_count = ARRAY_SIZE(hw_cfg),
46
+
.hw_cfg = hw_cfg
47
+
},
48
+
};
49
+
50
+
static void dpu_mdss_hw_init(struct dpu_mdss *dpu_mdss, u32 hw_rev)
51
+
{
52
+
int i;
53
+
u32 count = 0;
54
+
struct dpu_hw_cfg *hw_cfg = NULL;
55
+
56
+
for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) {
57
+
if (cfg_handler[i].hw_rev == hw_rev) {
58
+
hw_cfg = cfg_handler[i].hw_cfg;
59
+
count = cfg_handler[i].hw_reg_count;
60
+
break;
61
+
}
62
+
}
63
+
64
+
for (i = 0; i < count; i++ ) {
65
+
writel_relaxed(hw_cfg->val,
66
+
dpu_mdss->mmio + hw_cfg->offset);
67
+
hw_cfg++;
68
+
}
69
+
70
+
return;
71
+
}
46
72
47
73
static int dpu_mdss_parse_data_bus_icc_path(struct drm_device *dev,
48
74
struct dpu_mdss *dpu_mdss)
···
224
174
struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
225
175
struct dss_module_power *mp = &dpu_mdss->mp;
226
176
int ret;
177
+
u32 mdss_rev;
227
178
228
179
dpu_mdss_icc_request_bw(mdss);
229
180
230
181
ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
231
-
if (ret)
182
+
if (ret) {
232
183
DPU_ERROR("clock enable failed, ret:%d\n", ret);
184
+
return ret;
185
+
}
186
+
187
+
mdss_rev = readl_relaxed(dpu_mdss->mmio + HW_REV);
188
+
dpu_mdss_hw_init(dpu_mdss, mdss_rev);
233
189
234
190
return ret;
235
191
}
+2
-2
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+2
-2
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
···
1109
1109
ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
1110
1110
msecs_to_jiffies(50));
1111
1111
if (ret == 0)
1112
-
dev_warn(dev->dev, "pp done time out, lm=%d\n",
1113
-
mdp5_cstate->pipeline.mixer->lm);
1112
+
dev_warn_ratelimited(dev->dev, "pp done time out, lm=%d\n",
1113
+
mdp5_cstate->pipeline.mixer->lm);
1114
1114
}
1115
1115
1116
1116
static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)
+6
-1
drivers/gpu/drm/msm/dsi/dsi_manager.c
+6
-1
drivers/gpu/drm/msm/dsi/dsi_manager.c
···
336
336
return num;
337
337
}
338
338
339
-
static int dsi_mgr_connector_mode_valid(struct drm_connector *connector,
339
+
static enum drm_mode_status dsi_mgr_connector_mode_valid(struct drm_connector *connector,
340
340
struct drm_display_mode *mode)
341
341
{
342
342
int id = dsi_mgr_connector_get_id(connector);
···
506
506
struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1);
507
507
struct mipi_dsi_host *host = msm_dsi->host;
508
508
struct drm_panel *panel = msm_dsi->panel;
509
+
struct msm_dsi_pll *src_pll;
509
510
bool is_dual_dsi = IS_DUAL_DSI();
510
511
int ret;
511
512
···
539
538
pr_err("%s: Panel %d unprepare failed,%d\n", __func__,
540
539
id, ret);
541
540
}
541
+
542
+
/* Save PLL status if it is a clock source */
543
+
src_pll = msm_dsi_phy_get_pll(msm_dsi->phy);
544
+
msm_dsi_pll_save_state(src_pll);
542
545
543
546
ret = msm_dsi_host_power_off(host);
544
547
if (ret)
-4
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
-4
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+6
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
+6
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
···
411
411
if (pll_10nm->slave)
412
412
dsi_pll_enable_pll_bias(pll_10nm->slave);
413
413
414
+
rc = dsi_pll_10nm_vco_set_rate(hw,pll_10nm->vco_current_rate, 0);
415
+
if (rc) {
416
+
pr_err("vco_set_rate failed, rc=%d\n", rc);
417
+
return rc;
418
+
}
419
+
414
420
/* Start PLL */
415
421
pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL,
416
422
0x01);
+2
drivers/gpu/drm/nouveau/dispnv50/wndw.c
+2
drivers/gpu/drm/nouveau/dispnv50/wndw.c
···
458
458
asyw->clr.ntfy = armw->ntfy.handle != 0;
459
459
asyw->clr.sema = armw->sema.handle != 0;
460
460
asyw->clr.xlut = armw->xlut.handle != 0;
461
+
if (asyw->clr.xlut && asyw->visible)
462
+
asyw->set.xlut = asyw->xlut.handle != 0;
461
463
asyw->clr.csc = armw->csc.valid;
462
464
if (wndw->func->image_clr)
463
465
asyw->clr.image = armw->image.handle[0] != 0;
+4
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+4
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
···
2579
2579
static const struct nvkm_device_chip
2580
2580
nv167_chipset = {
2581
2581
.name = "TU117",
2582
+
.acr = tu102_acr_new,
2582
2583
.bar = tu102_bar_new,
2583
2584
.bios = nvkm_bios_new,
2584
2585
.bus = gf100_bus_new,
···
2608
2607
.disp = tu102_disp_new,
2609
2608
.dma = gv100_dma_new,
2610
2609
.fifo = tu102_fifo_new,
2610
+
.gr = tu102_gr_new,
2611
2611
.nvdec[0] = gm107_nvdec_new,
2612
2612
.nvenc[0] = gm107_nvenc_new,
2613
2613
.sec2 = tu102_sec2_new,
···
2617
2615
static const struct nvkm_device_chip
2618
2616
nv168_chipset = {
2619
2617
.name = "TU116",
2618
+
.acr = tu102_acr_new,
2620
2619
.bar = tu102_bar_new,
2621
2620
.bios = nvkm_bios_new,
2622
2621
.bus = gf100_bus_new,
···
2646
2643
.disp = tu102_disp_new,
2647
2644
.dma = gv100_dma_new,
2648
2645
.fifo = tu102_fifo_new,
2646
+
.gr = tu102_gr_new,
2649
2647
.nvdec[0] = gm107_nvdec_new,
2650
2648
.nvenc[0] = gm107_nvenc_new,
2651
2649
.sec2 = tu102_sec2_new,
+26
drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c
+26
drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c
···
164
164
MODULE_FIRMWARE("nvidia/tu106/gr/sw_bundle_init.bin");
165
165
MODULE_FIRMWARE("nvidia/tu106/gr/sw_method_init.bin");
166
166
167
+
MODULE_FIRMWARE("nvidia/tu117/gr/fecs_bl.bin");
168
+
MODULE_FIRMWARE("nvidia/tu117/gr/fecs_inst.bin");
169
+
MODULE_FIRMWARE("nvidia/tu117/gr/fecs_data.bin");
170
+
MODULE_FIRMWARE("nvidia/tu117/gr/fecs_sig.bin");
171
+
MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_bl.bin");
172
+
MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_inst.bin");
173
+
MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_data.bin");
174
+
MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_sig.bin");
175
+
MODULE_FIRMWARE("nvidia/tu117/gr/sw_ctx.bin");
176
+
MODULE_FIRMWARE("nvidia/tu117/gr/sw_nonctx.bin");
177
+
MODULE_FIRMWARE("nvidia/tu117/gr/sw_bundle_init.bin");
178
+
MODULE_FIRMWARE("nvidia/tu117/gr/sw_method_init.bin");
179
+
180
+
MODULE_FIRMWARE("nvidia/tu116/gr/fecs_bl.bin");
181
+
MODULE_FIRMWARE("nvidia/tu116/gr/fecs_inst.bin");
182
+
MODULE_FIRMWARE("nvidia/tu116/gr/fecs_data.bin");
183
+
MODULE_FIRMWARE("nvidia/tu116/gr/fecs_sig.bin");
184
+
MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_bl.bin");
185
+
MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_inst.bin");
186
+
MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_data.bin");
187
+
MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_sig.bin");
188
+
MODULE_FIRMWARE("nvidia/tu116/gr/sw_ctx.bin");
189
+
MODULE_FIRMWARE("nvidia/tu116/gr/sw_nonctx.bin");
190
+
MODULE_FIRMWARE("nvidia/tu116/gr/sw_bundle_init.bin");
191
+
MODULE_FIRMWARE("nvidia/tu116/gr/sw_method_init.bin");
192
+
167
193
static const struct gf100_gr_fwif
168
194
tu102_gr_fwif[] = {
169
195
{ 0, gm200_gr_load, &tu102_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr },
+14
drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c
+14
drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c
···
107
107
MODULE_FIRMWARE("nvidia/tu106/acr/unload_bl.bin");
108
108
MODULE_FIRMWARE("nvidia/tu106/acr/ucode_unload.bin");
109
109
110
+
MODULE_FIRMWARE("nvidia/tu116/acr/unload_bl.bin");
111
+
MODULE_FIRMWARE("nvidia/tu116/acr/ucode_unload.bin");
112
+
113
+
MODULE_FIRMWARE("nvidia/tu117/acr/unload_bl.bin");
114
+
MODULE_FIRMWARE("nvidia/tu117/acr/ucode_unload.bin");
115
+
110
116
static const struct nvkm_acr_hsf_fwif
111
117
tu102_acr_unload_fwif[] = {
112
118
{ 0, nvkm_acr_hsfw_load, &gp108_acr_unload_0 },
···
136
130
MODULE_FIRMWARE("nvidia/tu102/acr/ucode_asb.bin");
137
131
MODULE_FIRMWARE("nvidia/tu104/acr/ucode_asb.bin");
138
132
MODULE_FIRMWARE("nvidia/tu106/acr/ucode_asb.bin");
133
+
MODULE_FIRMWARE("nvidia/tu116/acr/ucode_asb.bin");
134
+
MODULE_FIRMWARE("nvidia/tu117/acr/ucode_asb.bin");
139
135
140
136
static const struct nvkm_acr_hsf_fwif
141
137
tu102_acr_asb_fwif[] = {
···
161
153
162
154
MODULE_FIRMWARE("nvidia/tu106/acr/bl.bin");
163
155
MODULE_FIRMWARE("nvidia/tu106/acr/ucode_ahesasc.bin");
156
+
157
+
MODULE_FIRMWARE("nvidia/tu116/acr/bl.bin");
158
+
MODULE_FIRMWARE("nvidia/tu116/acr/ucode_ahesasc.bin");
159
+
160
+
MODULE_FIRMWARE("nvidia/tu117/acr/bl.bin");
161
+
MODULE_FIRMWARE("nvidia/tu117/acr/ucode_ahesasc.bin");
164
162
165
163
static const struct nvkm_acr_hsf_fwif
166
164
tu102_acr_ahesasc_fwif[] = {
+2
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c
+2
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c
+1
-5
drivers/gpu/drm/panfrost/panfrost_job.c
+1
-5
drivers/gpu/drm/panfrost/panfrost_job.c
···
280
280
}
281
281
282
282
if (job->bos) {
283
-
struct panfrost_gem_object *bo;
284
-
285
-
for (i = 0; i < job->bo_count; i++) {
286
-
bo = to_panfrost_bo(job->bos[i]);
283
+
for (i = 0; i < job->bo_count; i++)
287
284
drm_gem_object_put_unlocked(job->bos[i]);
288
-
}
289
285
290
286
kvfree(job->bos);
291
287
}
+6
-1
drivers/gpu/drm/panfrost/panfrost_mmu.c
+6
-1
drivers/gpu/drm/panfrost/panfrost_mmu.c
···
151
151
as = mmu->as;
152
152
if (as >= 0) {
153
153
int en = atomic_inc_return(&mmu->as_count);
154
-
WARN_ON(en >= NUM_JOB_SLOTS);
154
+
155
+
/*
156
+
* AS can be retained by active jobs or a perfcnt context,
157
+
* hence the '+ 1' here.
158
+
*/
159
+
WARN_ON(en >= (NUM_JOB_SLOTS + 1));
155
160
156
161
list_move(&mmu->list, &pfdev->as_lru_list);
157
162
goto out;
+4
-7
drivers/gpu/drm/panfrost/panfrost_perfcnt.c
+4
-7
drivers/gpu/drm/panfrost/panfrost_perfcnt.c
···
73
73
struct panfrost_file_priv *user = file_priv->driver_priv;
74
74
struct panfrost_perfcnt *perfcnt = pfdev->perfcnt;
75
75
struct drm_gem_shmem_object *bo;
76
-
u32 cfg;
76
+
u32 cfg, as;
77
77
int ret;
78
78
79
79
if (user == perfcnt->user)
···
126
126
127
127
perfcnt->user = user;
128
128
129
-
/*
130
-
* Always use address space 0 for now.
131
-
* FIXME: this needs to be updated when we start using different
132
-
* address space.
133
-
*/
134
-
cfg = GPU_PERFCNT_CFG_AS(0) |
129
+
as = panfrost_mmu_as_get(pfdev, perfcnt->mapping->mmu);
130
+
cfg = GPU_PERFCNT_CFG_AS(as) |
135
131
GPU_PERFCNT_CFG_MODE(GPU_PERFCNT_CFG_MODE_MANUAL);
136
132
137
133
/*
···
191
195
drm_gem_shmem_vunmap(&perfcnt->mapping->obj->base.base, perfcnt->buf);
192
196
perfcnt->buf = NULL;
193
197
panfrost_gem_close(&perfcnt->mapping->obj->base.base, file_priv);
198
+
panfrost_mmu_as_put(pfdev, perfcnt->mapping->mmu);
194
199
panfrost_gem_mapping_put(perfcnt->mapping);
195
200
perfcnt->mapping = NULL;
196
201
pm_runtime_mark_last_busy(pfdev->dev);
+1
drivers/gpu/drm/selftests/drm_cmdline_selftests.h
+1
drivers/gpu/drm/selftests/drm_cmdline_selftests.h
···
53
53
cmdline_test(drm_cmdline_test_rotate_90)
54
54
cmdline_test(drm_cmdline_test_rotate_180)
55
55
cmdline_test(drm_cmdline_test_rotate_270)
56
+
cmdline_test(drm_cmdline_test_rotate_multiple)
56
57
cmdline_test(drm_cmdline_test_rotate_invalid_val)
57
58
cmdline_test(drm_cmdline_test_rotate_truncated)
58
59
cmdline_test(drm_cmdline_test_hmirror)
+13
-2
drivers/gpu/drm/selftests/test-drm_cmdline_parser.c
+13
-2
drivers/gpu/drm/selftests/test-drm_cmdline_parser.c
···
856
856
return 0;
857
857
}
858
858
859
+
static int drm_cmdline_test_rotate_multiple(void *ignored)
860
+
{
861
+
struct drm_cmdline_mode mode = { };
862
+
863
+
FAIL_ON(drm_mode_parse_command_line_for_connector("720x480,rotate=0,rotate=90",
864
+
&no_connector,
865
+
&mode));
866
+
867
+
return 0;
868
+
}
869
+
859
870
static int drm_cmdline_test_rotate_invalid_val(void *ignored)
860
871
{
861
872
struct drm_cmdline_mode mode = { };
···
899
888
FAIL_ON(!mode.specified);
900
889
FAIL_ON(mode.xres != 720);
901
890
FAIL_ON(mode.yres != 480);
902
-
FAIL_ON(mode.rotation_reflection != DRM_MODE_REFLECT_X);
891
+
FAIL_ON(mode.rotation_reflection != (DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_X));
903
892
904
893
FAIL_ON(mode.refresh_specified);
905
894
···
924
913
FAIL_ON(!mode.specified);
925
914
FAIL_ON(mode.xres != 720);
926
915
FAIL_ON(mode.yres != 480);
927
-
FAIL_ON(mode.rotation_reflection != DRM_MODE_REFLECT_Y);
916
+
FAIL_ON(mode.rotation_reflection != (DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_Y));
928
917
929
918
FAIL_ON(mode.refresh_specified);
930
919