tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
"A smallish batch of fixes, a little more than expected this late, but
all fixes are contained to their platforms and seem reasonably low
risk:

- a somewhat large SMP fix for ux500 that still seemed warranted to
include here
- OMAP DT fixes for pbias regulator specification that broke due to
some DT reshuffling
- PCIe IRQ routing bugfix for i.MX
- networking fixes for keystone
- runtime PM for OMAP GPMC
- a couple of error path bug fixes for exynos"

* tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: dts: keystone: Fix the mdio bindings by moving it to soc specific file
ARM: dts: keystone: fix the clock node for mdio
memory: omap-gpmc: Don't try to save uninitialized GPMC context
ARM: imx6: correct i.MX6 PCIe interrupt routing
ARM: ux500: add an SMP enablement type and move cpu nodes
ARM: dts: dra7: Fix broken pbias device creation
ARM: dts: OMAP5: Fix broken pbias device creation
ARM: dts: OMAP4: Fix broken pbias device creation
ARM: dts: omap243x: Fix broken pbias device creation
ARM: EXYNOS: fix double of_node_put() on error path
ARM: EXYNOS: Fix potentian kfree() of ro memory

Linus Torvalds 8916e0b0 0f405bf7

+79 -56
+1
Documentation/devicetree/bindings/arm/cpus.txt
··· 199 199 "qcom,kpss-acc-v1" 200 200 "qcom,kpss-acc-v2" 201 201 "rockchip,rk3066-smp" 202 + "ste,dbx500-smp" 202 203 203 204 - cpu-release-addr 204 205 Usage: required for systems that have an "enable-method"
+1 -1
arch/arm/boot/dts/dra7.dtsi
··· 116 116 ranges = <0 0x2000 0x2000>; 117 117 118 118 scm_conf: scm_conf@0 { 119 - compatible = "syscon"; 119 + compatible = "syscon", "simple-bus"; 120 120 reg = <0x0 0x1400>; 121 121 #address-cells = <1>; 122 122 #size-cells = <1>;
+4 -4
arch/arm/boot/dts/imx6qdl.dtsi
··· 181 181 interrupt-names = "msi"; 182 182 #interrupt-cells = <1>; 183 183 interrupt-map-mask = <0 0 0 0x7>; 184 - interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 185 - <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 186 - <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 187 - <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 184 + interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 185 + <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 186 + <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 187 + <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 188 188 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 189 189 <&clks IMX6QDL_CLK_LVDS1_GATE>, 190 190 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
+11 -4
arch/arm/boot/dts/k2e.dtsi
··· 131 131 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>; 132 132 }; 133 133 }; 134 + 135 + mdio: mdio@24200f00 { 136 + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; 137 + #address-cells = <1>; 138 + #size-cells = <0>; 139 + reg = <0x24200f00 0x100>; 140 + status = "disabled"; 141 + clocks = <&clkcpgmac>; 142 + clock-names = "fck"; 143 + bus_freq = <2500000>; 144 + }; 134 145 /include/ "k2e-netcp.dtsi" 135 146 }; 136 - }; 137 - 138 - &mdio { 139 - reg = <0x24200f00 0x100>; 140 147 };
+11
arch/arm/boot/dts/k2hk.dtsi
··· 98 98 #gpio-cells = <2>; 99 99 gpio,syscon-dev = <&devctrl 0x25c>; 100 100 }; 101 + 102 + mdio: mdio@02090300 { 103 + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; 104 + #address-cells = <1>; 105 + #size-cells = <0>; 106 + reg = <0x02090300 0x100>; 107 + status = "disabled"; 108 + clocks = <&clkcpgmac>; 109 + clock-names = "fck"; 110 + bus_freq = <2500000>; 111 + }; 101 112 /include/ "k2hk-netcp.dtsi" 102 113 }; 103 114 };
+11 -5
arch/arm/boot/dts/k2l.dtsi
··· 29 29 }; 30 30 31 31 soc { 32 - 33 32 /include/ "k2l-clocks.dtsi" 34 33 35 34 uart2: serial@02348400 { ··· 78 79 #gpio-cells = <2>; 79 80 gpio,syscon-dev = <&devctrl 0x24c>; 80 81 }; 82 + 83 + mdio: mdio@26200f00 { 84 + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; 85 + #address-cells = <1>; 86 + #size-cells = <0>; 87 + reg = <0x26200f00 0x100>; 88 + status = "disabled"; 89 + clocks = <&clkcpgmac>; 90 + clock-names = "fck"; 91 + bus_freq = <2500000>; 92 + }; 81 93 /include/ "k2l-netcp.dtsi" 82 94 }; 83 95 }; ··· 105 95 ti,davinci-spi-num-cs = <5>; 106 96 /* Pin muxed. Enabled and configured by Bootloader */ 107 97 status = "disabled"; 108 - }; 109 - 110 - &mdio { 111 - reg = <0x26200f00 0x100>; 112 98 };
-11
arch/arm/boot/dts/keystone.dtsi
··· 267 267 1 0 0x21000A00 0x00000100>; 268 268 }; 269 269 270 - mdio: mdio@02090300 { 271 - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; 272 - #address-cells = <1>; 273 - #size-cells = <0>; 274 - reg = <0x02090300 0x100>; 275 - status = "disabled"; 276 - clocks = <&clkpa>; 277 - clock-names = "fck"; 278 - bus_freq = <2500000>; 279 - }; 280 - 281 270 kirq0: keystone_irq@26202a0 { 282 271 compatible = "ti,keystone-irq"; 283 272 interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
+2 -1
arch/arm/boot/dts/omap2430.dtsi
··· 51 51 }; 52 52 53 53 scm_conf: scm_conf@270 { 54 - compatible = "syscon"; 54 + compatible = "syscon", 55 + "simple-bus"; 55 56 reg = <0x270 0x240>; 56 57 #address-cells = <1>; 57 58 #size-cells = <1>;
+2 -1
arch/arm/boot/dts/omap4.dtsi
··· 191 191 }; 192 192 193 193 omap4_padconf_global: omap4_padconf_global@5a0 { 194 - compatible = "syscon"; 194 + compatible = "syscon", 195 + "simple-bus"; 195 196 reg = <0x5a0 0x170>; 196 197 #address-cells = <1>; 197 198 #size-cells = <1>;
+2 -1
arch/arm/boot/dts/omap5.dtsi
··· 180 180 }; 181 181 182 182 omap5_padconf_global: omap5_padconf_global@5a0 { 183 - compatible = "syscon"; 183 + compatible = "syscon", 184 + "simple-bus"; 184 185 reg = <0x5a0 0xec>; 185 186 #address-cells = <1>; 186 187 #size-cells = <1>;
+27 -26
arch/arm/boot/dts/ste-dbx5x0.dtsi
··· 15 15 #include "skeleton.dtsi" 16 16 17 17 / { 18 + cpus { 19 + #address-cells = <1>; 20 + #size-cells = <0>; 21 + enable-method = "ste,dbx500-smp"; 22 + 23 + cpu-map { 24 + cluster0 { 25 + core0 { 26 + cpu = <&CPU0>; 27 + }; 28 + core1 { 29 + cpu = <&CPU1>; 30 + }; 31 + }; 32 + }; 33 + CPU0: cpu@300 { 34 + device_type = "cpu"; 35 + compatible = "arm,cortex-a9"; 36 + reg = <0x300>; 37 + }; 38 + CPU1: cpu@301 { 39 + device_type = "cpu"; 40 + compatible = "arm,cortex-a9"; 41 + reg = <0x301>; 42 + }; 43 + }; 44 + 18 45 soc { 19 46 #address-cells = <1>; 20 47 #size-cells = <1>; 21 48 compatible = "stericsson,db8500"; 22 49 interrupt-parent = <&intc>; 23 50 ranges; 24 - 25 - cpus { 26 - #address-cells = <1>; 27 - #size-cells = <0>; 28 - 29 - cpu-map { 30 - cluster0 { 31 - core0 { 32 - cpu = <&CPU0>; 33 - }; 34 - core1 { 35 - cpu = <&CPU1>; 36 - }; 37 - }; 38 - }; 39 - CPU0: cpu@0 { 40 - device_type = "cpu"; 41 - compatible = "arm,cortex-a9"; 42 - reg = <0>; 43 - }; 44 - CPU1: cpu@1 { 45 - device_type = "cpu"; 46 - compatible = "arm,cortex-a9"; 47 - reg = <1>; 48 - }; 49 - }; 50 51 51 52 ptm@801ae000 { 52 53 compatible = "arm,coresight-etm3x", "arm,primecell";
+1 -2
arch/arm/mach-exynos/pm_domains.c
··· 146 146 pd->base = of_iomap(np, 0); 147 147 if (!pd->base) { 148 148 pr_warn("%s: failed to map memory\n", __func__); 149 - kfree(pd->pd.name); 149 + kfree_const(pd->pd.name); 150 150 kfree(pd); 151 - of_node_put(np); 152 151 continue; 153 152 } 154 153
+6
drivers/memory/omap-gpmc.c
··· 2245 2245 { 2246 2246 int i; 2247 2247 2248 + if (!gpmc_base) 2249 + return; 2250 + 2248 2251 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); 2249 2252 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE); 2250 2253 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); ··· 2279 2276 void omap3_gpmc_restore_context(void) 2280 2277 { 2281 2278 int i; 2279 + 2280 + if (!gpmc_base) 2281 + return; 2282 2282 2283 2283 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig); 2284 2284 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);