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drm/xe/lrc: Refactor context init into xe_lrc_ctx_init()

Currently xe_lrc_init() does two things.

1. Allocates LRC bo based on exec queue parameters.
2. Initializes LRC bo with actual context details.

Introduce xe_lrc_ctx_init() and split these two implementations for
better maintainability.

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260302082757.3516577-1-raag.jadav@intel.com

authored by

Raag Jadav and committed by
Matthew Brost 89340099 2b37c401

+79 -63
+79 -63
drivers/gpu/drm/xe/xe_lrc.c
··· 1438 1438 lrc->desc |= FIELD_PREP(LRC_PRIORITY, xe_multi_queue_prio_to_lrc(lrc, priority)); 1439 1439 } 1440 1440 1441 - static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, 1442 - struct xe_vm *vm, void *replay_state, u32 ring_size, 1443 - u16 msix_vec, 1444 - u32 init_flags) 1441 + static int xe_lrc_ctx_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, struct xe_vm *vm, 1442 + void *replay_state, u16 msix_vec, u32 init_flags) 1445 1443 { 1446 1444 struct xe_gt *gt = hwe->gt; 1447 - const u32 lrc_size = xe_gt_lrc_size(gt, hwe->class); 1448 - u32 bo_size = ring_size + lrc_size + LRC_WA_BB_SIZE; 1449 1445 struct xe_tile *tile = gt_to_tile(gt); 1450 1446 struct xe_device *xe = gt_to_xe(gt); 1451 - struct xe_bo *seqno_bo; 1452 1447 struct iosys_map map; 1453 1448 u32 arb_enable; 1454 - u32 bo_flags; 1455 1449 int err; 1456 - 1457 - kref_init(&lrc->refcount); 1458 - lrc->gt = gt; 1459 - lrc->replay_size = xe_gt_lrc_hang_replay_size(gt, hwe->class); 1460 - lrc->size = lrc_size; 1461 - lrc->flags = 0; 1462 - lrc->ring.size = ring_size; 1463 - lrc->ring.tail = 0; 1464 - 1465 - if (gt_engine_needs_indirect_ctx(gt, hwe->class)) { 1466 - lrc->flags |= XE_LRC_FLAG_INDIRECT_CTX; 1467 - bo_size += LRC_INDIRECT_CTX_BO_SIZE; 1468 - } 1469 - 1470 - if (xe_gt_has_indirect_ring_state(gt)) 1471 - lrc->flags |= XE_LRC_FLAG_INDIRECT_RING_STATE; 1472 - 1473 - bo_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) | XE_BO_FLAG_GGTT | 1474 - XE_BO_FLAG_GGTT_INVALIDATE; 1475 - 1476 - if ((vm && vm->xef) || init_flags & XE_LRC_CREATE_USER_CTX) /* userspace */ 1477 - bo_flags |= XE_BO_FLAG_PINNED_LATE_RESTORE | XE_BO_FLAG_FORCE_USER_VRAM; 1478 - 1479 - lrc->bo = xe_bo_create_pin_map_novm(xe, tile, 1480 - bo_size, 1481 - ttm_bo_type_kernel, 1482 - bo_flags, false); 1483 - if (IS_ERR(lrc->bo)) 1484 - return PTR_ERR(lrc->bo); 1485 - 1486 - seqno_bo = xe_bo_create_pin_map_novm(xe, tile, PAGE_SIZE, 1487 - ttm_bo_type_kernel, 1488 - XE_BO_FLAG_GGTT | 1489 - XE_BO_FLAG_GGTT_INVALIDATE | 1490 - XE_BO_FLAG_SYSTEM, false); 1491 - if (IS_ERR(seqno_bo)) { 1492 - err = PTR_ERR(seqno_bo); 1493 - goto err_lrc_finish; 1494 - } 1495 - lrc->seqno_bo = seqno_bo; 1496 - 1497 - xe_hw_fence_ctx_init(&lrc->fence_ctx, hwe->gt, 1498 - hwe->fence_irq, hwe->name); 1499 1450 1500 1451 /* 1501 1452 * Init Per-Process of HW status Page, LRC / context state to known ··· 1459 1508 xe_map_memset(xe, &map, 0, 0, LRC_PPHWSP_SIZE); /* PPHWSP */ 1460 1509 xe_map_memcpy_to(xe, &map, LRC_PPHWSP_SIZE, 1461 1510 gt->default_lrc[hwe->class] + LRC_PPHWSP_SIZE, 1462 - lrc_size - LRC_PPHWSP_SIZE); 1511 + lrc->size - LRC_PPHWSP_SIZE); 1463 1512 if (replay_state) 1464 1513 xe_map_memcpy_to(xe, &map, LRC_PPHWSP_SIZE, 1465 1514 replay_state, lrc->replay_size); ··· 1467 1516 void *init_data = empty_lrc_data(hwe); 1468 1517 1469 1518 if (!init_data) { 1470 - err = -ENOMEM; 1471 - goto err_lrc_finish; 1519 + return -ENOMEM; 1472 1520 } 1473 1521 1474 - xe_map_memcpy_to(xe, &map, 0, init_data, lrc_size); 1522 + xe_map_memcpy_to(xe, &map, 0, init_data, lrc->size); 1475 1523 kfree(init_data); 1476 1524 } 1477 1525 1478 - if (vm) { 1526 + if (vm) 1479 1527 xe_lrc_set_ppgtt(lrc, vm); 1480 - 1481 - if (vm->xef) 1482 - xe_drm_client_add_bo(vm->xef->client, lrc->bo); 1483 - } 1484 1528 1485 1529 if (xe_device_has_msix(xe)) { 1486 1530 xe_lrc_write_ctx_reg(lrc, CTX_INT_STATUS_REPORT_PTR, ··· 1492 1546 xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_START, 1493 1547 __xe_lrc_ring_ggtt_addr(lrc)); 1494 1548 xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_START_UDW, 0); 1495 - xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_HEAD, 0); 1549 + 1550 + /* Match head and tail pointers */ 1551 + xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_HEAD, lrc->ring.tail); 1496 1552 xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_TAIL, lrc->ring.tail); 1553 + 1497 1554 xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_CTL, 1498 1555 RING_CTL_SIZE(lrc->ring.size) | RING_VALID); 1499 1556 } else { 1500 1557 xe_lrc_write_ctx_reg(lrc, CTX_RING_START, __xe_lrc_ring_ggtt_addr(lrc)); 1501 - xe_lrc_write_ctx_reg(lrc, CTX_RING_HEAD, 0); 1558 + 1559 + /* Match head and tail pointers */ 1560 + xe_lrc_write_ctx_reg(lrc, CTX_RING_HEAD, lrc->ring.tail); 1502 1561 xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail); 1562 + 1503 1563 xe_lrc_write_ctx_reg(lrc, CTX_RING_CTL, 1504 1564 RING_CTL_SIZE(lrc->ring.size) | RING_VALID); 1505 1565 } ··· 1554 1602 1555 1603 err = setup_wa_bb(lrc, hwe); 1556 1604 if (err) 1557 - goto err_lrc_finish; 1605 + return err; 1558 1606 1559 1607 err = setup_indirect_ctx(lrc, hwe); 1608 + 1609 + return err; 1610 + } 1611 + 1612 + static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, struct xe_vm *vm, 1613 + void *replay_state, u32 ring_size, u16 msix_vec, u32 init_flags) 1614 + { 1615 + struct xe_gt *gt = hwe->gt; 1616 + const u32 lrc_size = xe_gt_lrc_size(gt, hwe->class); 1617 + u32 bo_size = ring_size + lrc_size + LRC_WA_BB_SIZE; 1618 + struct xe_tile *tile = gt_to_tile(gt); 1619 + struct xe_device *xe = gt_to_xe(gt); 1620 + struct xe_bo *bo; 1621 + u32 bo_flags; 1622 + int err; 1623 + 1624 + kref_init(&lrc->refcount); 1625 + lrc->gt = gt; 1626 + lrc->replay_size = xe_gt_lrc_hang_replay_size(gt, hwe->class); 1627 + lrc->size = lrc_size; 1628 + lrc->flags = 0; 1629 + lrc->ring.size = ring_size; 1630 + lrc->ring.tail = 0; 1631 + 1632 + if (gt_engine_needs_indirect_ctx(gt, hwe->class)) { 1633 + lrc->flags |= XE_LRC_FLAG_INDIRECT_CTX; 1634 + bo_size += LRC_INDIRECT_CTX_BO_SIZE; 1635 + } 1636 + 1637 + if (xe_gt_has_indirect_ring_state(gt)) 1638 + lrc->flags |= XE_LRC_FLAG_INDIRECT_RING_STATE; 1639 + 1640 + bo_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) | XE_BO_FLAG_GGTT | 1641 + XE_BO_FLAG_GGTT_INVALIDATE; 1642 + 1643 + if ((vm && vm->xef) || init_flags & XE_LRC_CREATE_USER_CTX) /* userspace */ 1644 + bo_flags |= XE_BO_FLAG_PINNED_LATE_RESTORE | XE_BO_FLAG_FORCE_USER_VRAM; 1645 + 1646 + bo = xe_bo_create_pin_map_novm(xe, tile, bo_size, 1647 + ttm_bo_type_kernel, 1648 + bo_flags, false); 1649 + if (IS_ERR(lrc->bo)) 1650 + return PTR_ERR(lrc->bo); 1651 + 1652 + lrc->bo = bo; 1653 + 1654 + bo = xe_bo_create_pin_map_novm(xe, tile, PAGE_SIZE, 1655 + ttm_bo_type_kernel, 1656 + XE_BO_FLAG_GGTT | 1657 + XE_BO_FLAG_GGTT_INVALIDATE | 1658 + XE_BO_FLAG_SYSTEM, false); 1659 + if (IS_ERR(bo)) { 1660 + err = PTR_ERR(bo); 1661 + goto err_lrc_finish; 1662 + } 1663 + lrc->seqno_bo = bo; 1664 + 1665 + xe_hw_fence_ctx_init(&lrc->fence_ctx, hwe->gt, 1666 + hwe->fence_irq, hwe->name); 1667 + 1668 + err = xe_lrc_ctx_init(lrc, hwe, vm, replay_state, msix_vec, init_flags); 1560 1669 if (err) 1561 1670 goto err_lrc_finish; 1671 + 1672 + if (vm && vm->xef) 1673 + xe_drm_client_add_bo(vm->xef->client, lrc->bo); 1562 1674 1563 1675 return 0; 1564 1676