Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull more kvm updates from Paolo Bonzini:
"Mostly the PPC part of the release, but also switching to Arnd's fix
for the hyperv config issue and a typo fix.
Main PPC changes:
- reimplement the MMIO instruction emulation
- transactional memory support for PR KVM
- improve radix page table handling"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (63 commits)
KVM: x86: VMX: redo fix for link error without CONFIG_HYPERV
KVM: x86: fix typo at kvm_arch_hardware_setup comment
KVM: PPC: Book3S PR: Fix failure status setting in tabort. emulation
KVM: PPC: Book3S PR: Enable use on POWER9 bare-metal hosts in HPT mode
KVM: PPC: Book3S PR: Don't let PAPR guest set MSR hypervisor bit
KVM: PPC: Book3S PR: Fix failure status setting in treclaim. emulation
KVM: PPC: Book3S PR: Fix MSR setting when delivering interrupts
KVM: PPC: Book3S PR: Handle additional interrupt types
KVM: PPC: Book3S PR: Enable kvmppc_get/set_one_reg_pr() for HTM registers
KVM: PPC: Book3S: Remove load/put vcpu for KVM_GET_REGS/KVM_SET_REGS
KVM: PPC: Remove load/put vcpu for KVM_GET/SET_ONE_REG ioctl
KVM: PPC: Move vcpu_load/vcpu_put down to each ioctl case in kvm_arch_vcpu_ioctl
KVM: PPC: Book3S PR: Enable HTM for PR KVM for KVM_CHECK_EXTENSION ioctl
KVM: PPC: Book3S PR: Support TAR handling for PR KVM HTM
KVM: PPC: Book3S PR: Add guard code to prevent returning to guest with PR=0 and Transactional state
KVM: PPC: Book3S PR: Add emulation for tabort. in privileged state
KVM: PPC: Book3S PR: Add emulation for trechkpt.
KVM: PPC: Book3S PR: Add emulation for treclaim.
KVM: PPC: Book3S PR: Restore NV regs after emulating mfspr from TM SPRs
KVM: PPC: Book3S PR: Always fail transactions in guest privileged state
...
+2343
-1263
+6
arch/powerpc/include/asm/asm-prototypes.h
+6
arch/powerpc/include/asm/asm-prototypes.h
···
134
134
void pnv_power9_force_smt4_catch(void);
135
135
void pnv_power9_force_smt4_release(void);
136
136
137
+
/* Transaction memory related */
137
138
void tm_enable(void);
138
139
void tm_disable(void);
139
140
void tm_abort(uint8_t cause);
141
+
142
+
struct kvm_vcpu;
143
+
void _kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu, u64 guest_msr);
144
+
void _kvmppc_save_tm_pr(struct kvm_vcpu *vcpu, u64 guest_msr);
145
+
140
146
#endif /* _ASM_POWERPC_ASM_PROTOTYPES_H */
+27
-10
arch/powerpc/include/asm/kvm_book3s.h
+27
-10
arch/powerpc/include/asm/kvm_book3s.h
···
104
104
ulong vtb; /* virtual timebase */
105
105
ulong conferring_threads;
106
106
unsigned int halt_poll_ns;
107
+
atomic_t online_count;
107
108
};
108
109
109
110
struct kvmppc_vcpu_book3s {
···
210
209
extern void kvmppc_book3s_dequeue_irqprio(struct kvm_vcpu *vcpu,
211
210
unsigned int vec);
212
211
extern void kvmppc_inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 flags);
212
+
extern void kvmppc_trigger_fac_interrupt(struct kvm_vcpu *vcpu, ulong fac);
213
213
extern void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat,
214
214
bool upper, u32 val);
215
215
extern void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr);
···
258
256
extern int kvmppc_hcall_impl_hv_realmode(unsigned long cmd);
259
257
extern void kvmppc_copy_to_svcpu(struct kvm_vcpu *vcpu);
260
258
extern void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu);
259
+
260
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
261
+
void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu);
262
+
void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu);
263
+
void kvmppc_save_tm_sprs(struct kvm_vcpu *vcpu);
264
+
void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu);
265
+
#else
266
+
static inline void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu) {}
267
+
static inline void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu) {}
268
+
static inline void kvmppc_save_tm_sprs(struct kvm_vcpu *vcpu) {}
269
+
static inline void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu) {}
270
+
#endif
271
+
272
+
void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac);
273
+
261
274
extern int kvm_irq_bypass;
262
275
263
276
static inline struct kvmppc_vcpu_book3s *to_book3s(struct kvm_vcpu *vcpu)
···
291
274
292
275
static inline void kvmppc_set_gpr(struct kvm_vcpu *vcpu, int num, ulong val)
293
276
{
294
-
vcpu->arch.gpr[num] = val;
277
+
vcpu->arch.regs.gpr[num] = val;
295
278
}
296
279
297
280
static inline ulong kvmppc_get_gpr(struct kvm_vcpu *vcpu, int num)
298
281
{
299
-
return vcpu->arch.gpr[num];
282
+
return vcpu->arch.regs.gpr[num];
300
283
}
301
284
302
285
static inline void kvmppc_set_cr(struct kvm_vcpu *vcpu, u32 val)
···
311
294
312
295
static inline void kvmppc_set_xer(struct kvm_vcpu *vcpu, ulong val)
313
296
{
314
-
vcpu->arch.xer = val;
297
+
vcpu->arch.regs.xer = val;
315
298
}
316
299
317
300
static inline ulong kvmppc_get_xer(struct kvm_vcpu *vcpu)
318
301
{
319
-
return vcpu->arch.xer;
302
+
return vcpu->arch.regs.xer;
320
303
}
321
304
322
305
static inline void kvmppc_set_ctr(struct kvm_vcpu *vcpu, ulong val)
323
306
{
324
-
vcpu->arch.ctr = val;
307
+
vcpu->arch.regs.ctr = val;
325
308
}
326
309
327
310
static inline ulong kvmppc_get_ctr(struct kvm_vcpu *vcpu)
328
311
{
329
-
return vcpu->arch.ctr;
312
+
return vcpu->arch.regs.ctr;
330
313
}
331
314
332
315
static inline void kvmppc_set_lr(struct kvm_vcpu *vcpu, ulong val)
333
316
{
334
-
vcpu->arch.lr = val;
317
+
vcpu->arch.regs.link = val;
335
318
}
336
319
337
320
static inline ulong kvmppc_get_lr(struct kvm_vcpu *vcpu)
338
321
{
339
-
return vcpu->arch.lr;
322
+
return vcpu->arch.regs.link;
340
323
}
341
324
342
325
static inline void kvmppc_set_pc(struct kvm_vcpu *vcpu, ulong val)
343
326
{
344
-
vcpu->arch.pc = val;
327
+
vcpu->arch.regs.nip = val;
345
328
}
346
329
347
330
static inline ulong kvmppc_get_pc(struct kvm_vcpu *vcpu)
348
331
{
349
-
return vcpu->arch.pc;
332
+
return vcpu->arch.regs.nip;
350
333
}
351
334
352
335
static inline u64 kvmppc_get_msr(struct kvm_vcpu *vcpu);
+10
-10
arch/powerpc/include/asm/kvm_book3s_64.h
+10
-10
arch/powerpc/include/asm/kvm_book3s_64.h
···
483
483
static inline void copy_from_checkpoint(struct kvm_vcpu *vcpu)
484
484
{
485
485
vcpu->arch.cr = vcpu->arch.cr_tm;
486
-
vcpu->arch.xer = vcpu->arch.xer_tm;
487
-
vcpu->arch.lr = vcpu->arch.lr_tm;
488
-
vcpu->arch.ctr = vcpu->arch.ctr_tm;
486
+
vcpu->arch.regs.xer = vcpu->arch.xer_tm;
487
+
vcpu->arch.regs.link = vcpu->arch.lr_tm;
488
+
vcpu->arch.regs.ctr = vcpu->arch.ctr_tm;
489
489
vcpu->arch.amr = vcpu->arch.amr_tm;
490
490
vcpu->arch.ppr = vcpu->arch.ppr_tm;
491
491
vcpu->arch.dscr = vcpu->arch.dscr_tm;
492
492
vcpu->arch.tar = vcpu->arch.tar_tm;
493
-
memcpy(vcpu->arch.gpr, vcpu->arch.gpr_tm,
494
-
sizeof(vcpu->arch.gpr));
493
+
memcpy(vcpu->arch.regs.gpr, vcpu->arch.gpr_tm,
494
+
sizeof(vcpu->arch.regs.gpr));
495
495
vcpu->arch.fp = vcpu->arch.fp_tm;
496
496
vcpu->arch.vr = vcpu->arch.vr_tm;
497
497
vcpu->arch.vrsave = vcpu->arch.vrsave_tm;
···
500
500
static inline void copy_to_checkpoint(struct kvm_vcpu *vcpu)
501
501
{
502
502
vcpu->arch.cr_tm = vcpu->arch.cr;
503
-
vcpu->arch.xer_tm = vcpu->arch.xer;
504
-
vcpu->arch.lr_tm = vcpu->arch.lr;
505
-
vcpu->arch.ctr_tm = vcpu->arch.ctr;
503
+
vcpu->arch.xer_tm = vcpu->arch.regs.xer;
504
+
vcpu->arch.lr_tm = vcpu->arch.regs.link;
505
+
vcpu->arch.ctr_tm = vcpu->arch.regs.ctr;
506
506
vcpu->arch.amr_tm = vcpu->arch.amr;
507
507
vcpu->arch.ppr_tm = vcpu->arch.ppr;
508
508
vcpu->arch.dscr_tm = vcpu->arch.dscr;
509
509
vcpu->arch.tar_tm = vcpu->arch.tar;
510
-
memcpy(vcpu->arch.gpr_tm, vcpu->arch.gpr,
511
-
sizeof(vcpu->arch.gpr));
510
+
memcpy(vcpu->arch.gpr_tm, vcpu->arch.regs.gpr,
511
+
sizeof(vcpu->arch.regs.gpr));
512
512
vcpu->arch.fp_tm = vcpu->arch.fp;
513
513
vcpu->arch.vr_tm = vcpu->arch.vr;
514
514
vcpu->arch.vrsave_tm = vcpu->arch.vrsave;
+10
-10
arch/powerpc/include/asm/kvm_booke.h
+10
-10
arch/powerpc/include/asm/kvm_booke.h
···
36
36
37
37
static inline void kvmppc_set_gpr(struct kvm_vcpu *vcpu, int num, ulong val)
38
38
{
39
-
vcpu->arch.gpr[num] = val;
39
+
vcpu->arch.regs.gpr[num] = val;
40
40
}
41
41
42
42
static inline ulong kvmppc_get_gpr(struct kvm_vcpu *vcpu, int num)
43
43
{
44
-
return vcpu->arch.gpr[num];
44
+
return vcpu->arch.regs.gpr[num];
45
45
}
46
46
47
47
static inline void kvmppc_set_cr(struct kvm_vcpu *vcpu, u32 val)
···
56
56
57
57
static inline void kvmppc_set_xer(struct kvm_vcpu *vcpu, ulong val)
58
58
{
59
-
vcpu->arch.xer = val;
59
+
vcpu->arch.regs.xer = val;
60
60
}
61
61
62
62
static inline ulong kvmppc_get_xer(struct kvm_vcpu *vcpu)
63
63
{
64
-
return vcpu->arch.xer;
64
+
return vcpu->arch.regs.xer;
65
65
}
66
66
67
67
static inline bool kvmppc_need_byteswap(struct kvm_vcpu *vcpu)
···
72
72
73
73
static inline void kvmppc_set_ctr(struct kvm_vcpu *vcpu, ulong val)
74
74
{
75
-
vcpu->arch.ctr = val;
75
+
vcpu->arch.regs.ctr = val;
76
76
}
77
77
78
78
static inline ulong kvmppc_get_ctr(struct kvm_vcpu *vcpu)
79
79
{
80
-
return vcpu->arch.ctr;
80
+
return vcpu->arch.regs.ctr;
81
81
}
82
82
83
83
static inline void kvmppc_set_lr(struct kvm_vcpu *vcpu, ulong val)
84
84
{
85
-
vcpu->arch.lr = val;
85
+
vcpu->arch.regs.link = val;
86
86
}
87
87
88
88
static inline ulong kvmppc_get_lr(struct kvm_vcpu *vcpu)
89
89
{
90
-
return vcpu->arch.lr;
90
+
return vcpu->arch.regs.link;
91
91
}
92
92
93
93
static inline void kvmppc_set_pc(struct kvm_vcpu *vcpu, ulong val)
94
94
{
95
-
vcpu->arch.pc = val;
95
+
vcpu->arch.regs.nip = val;
96
96
}
97
97
98
98
static inline ulong kvmppc_get_pc(struct kvm_vcpu *vcpu)
99
99
{
100
-
return vcpu->arch.pc;
100
+
return vcpu->arch.regs.nip;
101
101
}
102
102
103
103
static inline ulong kvmppc_get_fault_dar(struct kvm_vcpu *vcpu)
+12
-9
arch/powerpc/include/asm/kvm_host.h
+12
-9
arch/powerpc/include/asm/kvm_host.h
···
269
269
unsigned long host_lpcr;
270
270
unsigned long sdr1;
271
271
unsigned long host_sdr1;
272
-
int tlbie_lock;
273
272
unsigned long lpcr;
274
273
unsigned long vrma_slb_v;
275
274
int mmu_ready;
···
453
454
#define KVMPPC_VSX_COPY_WORD 1
454
455
#define KVMPPC_VSX_COPY_DWORD 2
455
456
#define KVMPPC_VSX_COPY_DWORD_LOAD_DUMP 3
457
+
#define KVMPPC_VSX_COPY_WORD_LOAD_DUMP 4
458
+
459
+
#define KVMPPC_VMX_COPY_BYTE 8
460
+
#define KVMPPC_VMX_COPY_HWORD 9
461
+
#define KVMPPC_VMX_COPY_WORD 10
462
+
#define KVMPPC_VMX_COPY_DWORD 11
456
463
457
464
struct openpic;
458
465
···
491
486
struct kvmppc_book3s_shadow_vcpu *shadow_vcpu;
492
487
#endif
493
488
494
-
ulong gpr[32];
489
+
struct pt_regs regs;
495
490
496
491
struct thread_fp_state fp;
497
492
···
526
521
u32 qpr[32];
527
522
#endif
528
523
529
-
ulong pc;
530
-
ulong ctr;
531
-
ulong lr;
532
524
#ifdef CONFIG_PPC_BOOK3S
533
525
ulong tar;
534
526
#endif
535
527
536
-
ulong xer;
537
528
u32 cr;
538
529
539
530
#ifdef CONFIG_PPC_BOOK3S
···
627
626
628
627
struct thread_vr_state vr_tm;
629
628
u32 vrsave_tm; /* also USPRG0 */
630
-
631
629
#endif
632
630
633
631
#ifdef CONFIG_KVM_EXIT_TIMING
···
681
681
* Number of simulations for vsx.
682
682
* If we use 2*8bytes to simulate 1*16bytes,
683
683
* then the number should be 2 and
684
-
* mmio_vsx_copy_type=KVMPPC_VSX_COPY_DWORD.
684
+
* mmio_copy_type=KVMPPC_VSX_COPY_DWORD.
685
685
* If we use 4*4bytes to simulate 1*16bytes,
686
686
* the number should be 4 and
687
687
* mmio_vsx_copy_type=KVMPPC_VSX_COPY_WORD.
688
688
*/
689
689
u8 mmio_vsx_copy_nums;
690
690
u8 mmio_vsx_offset;
691
-
u8 mmio_vsx_copy_type;
692
691
u8 mmio_vsx_tx_sx_enabled;
693
692
u8 mmio_vmx_copy_nums;
693
+
u8 mmio_vmx_offset;
694
+
u8 mmio_copy_type;
694
695
u8 osi_needed;
695
696
u8 osi_enabled;
696
697
u8 papr_enabled;
···
773
772
u64 busy_preempt;
774
773
775
774
u32 emul_inst;
775
+
776
+
u32 online;
776
777
#endif
777
778
778
779
#ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
+10
-7
arch/powerpc/include/asm/kvm_ppc.h
+10
-7
arch/powerpc/include/asm/kvm_ppc.h
···
52
52
EMULATE_EXIT_USER, /* emulation requires exit to user-space */
53
53
};
54
54
55
-
enum instruction_type {
55
+
enum instruction_fetch_type {
56
56
INST_GENERIC,
57
57
INST_SC, /* system call */
58
58
};
···
81
81
extern int kvmppc_handle_vsx_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
82
82
unsigned int rt, unsigned int bytes,
83
83
int is_default_endian, int mmio_sign_extend);
84
-
extern int kvmppc_handle_load128_by2x64(struct kvm_run *run,
85
-
struct kvm_vcpu *vcpu, unsigned int rt, int is_default_endian);
86
-
extern int kvmppc_handle_store128_by2x64(struct kvm_run *run,
87
-
struct kvm_vcpu *vcpu, unsigned int rs, int is_default_endian);
84
+
extern int kvmppc_handle_vmx_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
85
+
unsigned int rt, unsigned int bytes, int is_default_endian);
86
+
extern int kvmppc_handle_vmx_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
87
+
unsigned int rs, unsigned int bytes, int is_default_endian);
88
88
extern int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
89
89
u64 val, unsigned int bytes,
90
90
int is_default_endian);
···
93
93
int is_default_endian);
94
94
95
95
extern int kvmppc_load_last_inst(struct kvm_vcpu *vcpu,
96
-
enum instruction_type type, u32 *inst);
96
+
enum instruction_fetch_type type, u32 *inst);
97
97
98
98
extern int kvmppc_ld(struct kvm_vcpu *vcpu, ulong *eaddr, int size, void *ptr,
99
99
bool data);
···
265
265
vector128 vval;
266
266
u64 vsxval[2];
267
267
u32 vsx32val[4];
268
+
u16 vsx16val[8];
269
+
u8 vsx8val[16];
268
270
struct {
269
271
u64 addr;
270
272
u64 length;
···
326
324
int (*get_rmmu_info)(struct kvm *kvm, struct kvm_ppc_rmmu_info *info);
327
325
int (*set_smt_mode)(struct kvm *kvm, unsigned long mode,
328
326
unsigned long flags);
327
+
void (*giveup_ext)(struct kvm_vcpu *vcpu, ulong msr);
329
328
};
330
329
331
330
extern struct kvmppc_ops *kvmppc_hv_ops;
332
331
extern struct kvmppc_ops *kvmppc_pr_ops;
333
332
334
333
static inline int kvmppc_get_last_inst(struct kvm_vcpu *vcpu,
335
-
enum instruction_type type, u32 *inst)
334
+
enum instruction_fetch_type type, u32 *inst)
336
335
{
337
336
int ret = EMULATE_DONE;
338
337
u32 fetched_inst;
+1
arch/powerpc/include/asm/reg.h
+1
arch/powerpc/include/asm/reg.h
···
385
385
#define SPRN_PSSCR 0x357 /* Processor Stop Status and Control Register (ISA 3.0) */
386
386
#define SPRN_PSSCR_PR 0x337 /* PSSCR ISA 3.0, privileged mode access */
387
387
#define SPRN_PMCR 0x374 /* Power Management Control Register */
388
+
#define SPRN_RWMR 0x375 /* Region-Weighting Mode Register */
388
389
389
390
/* HFSCR and FSCR bit numbers are the same */
390
391
#define FSCR_SCV_LG 12 /* Enable System Call Vectored */
+1
arch/powerpc/include/uapi/asm/kvm.h
+1
arch/powerpc/include/uapi/asm/kvm.h
···
633
633
#define KVM_REG_PPC_PSSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbd)
634
634
635
635
#define KVM_REG_PPC_DEC_EXPIRY (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbe)
636
+
#define KVM_REG_PPC_ONLINE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbf)
636
637
637
638
/* Transactional Memory checkpointed state:
638
639
* This is all GPRs, all VSX regs and a subset of SPRs
+9
-9
arch/powerpc/kernel/asm-offsets.c
+9
-9
arch/powerpc/kernel/asm-offsets.c
···
426
426
OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack);
427
427
OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid);
428
428
OFFSET(VCPU_GUEST_PID, kvm_vcpu, arch.pid);
429
-
OFFSET(VCPU_GPRS, kvm_vcpu, arch.gpr);
429
+
OFFSET(VCPU_GPRS, kvm_vcpu, arch.regs.gpr);
430
430
OFFSET(VCPU_VRSAVE, kvm_vcpu, arch.vrsave);
431
431
OFFSET(VCPU_FPRS, kvm_vcpu, arch.fp.fpr);
432
432
#ifdef CONFIG_ALTIVEC
433
433
OFFSET(VCPU_VRS, kvm_vcpu, arch.vr.vr);
434
434
#endif
435
-
OFFSET(VCPU_XER, kvm_vcpu, arch.xer);
436
-
OFFSET(VCPU_CTR, kvm_vcpu, arch.ctr);
437
-
OFFSET(VCPU_LR, kvm_vcpu, arch.lr);
435
+
OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
436
+
OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
437
+
OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
438
438
#ifdef CONFIG_PPC_BOOK3S
439
439
OFFSET(VCPU_TAR, kvm_vcpu, arch.tar);
440
440
#endif
441
441
OFFSET(VCPU_CR, kvm_vcpu, arch.cr);
442
-
OFFSET(VCPU_PC, kvm_vcpu, arch.pc);
442
+
OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
443
443
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
444
444
OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs.msr);
445
445
OFFSET(VCPU_SRR0, kvm_vcpu, arch.shregs.srr0);
···
696
696
697
697
#else /* CONFIG_PPC_BOOK3S */
698
698
OFFSET(VCPU_CR, kvm_vcpu, arch.cr);
699
-
OFFSET(VCPU_XER, kvm_vcpu, arch.xer);
700
-
OFFSET(VCPU_LR, kvm_vcpu, arch.lr);
701
-
OFFSET(VCPU_CTR, kvm_vcpu, arch.ctr);
702
-
OFFSET(VCPU_PC, kvm_vcpu, arch.pc);
699
+
OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
700
+
OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
701
+
OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
702
+
OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
703
703
OFFSET(VCPU_SPRG9, kvm_vcpu, arch.sprg9);
704
704
OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
705
705
OFFSET(VCPU_FAULT_DEAR, kvm_vcpu, arch.fault_dear);
+3
arch/powerpc/kvm/Makefile
+3
arch/powerpc/kvm/Makefile
+7
-16
arch/powerpc/kvm/book3s.c
+7
-16
arch/powerpc/kvm/book3s.c
···
134
134
{
135
135
kvmppc_unfixup_split_real(vcpu);
136
136
kvmppc_set_srr0(vcpu, kvmppc_get_pc(vcpu));
137
-
kvmppc_set_srr1(vcpu, kvmppc_get_msr(vcpu) | flags);
137
+
kvmppc_set_srr1(vcpu, (kvmppc_get_msr(vcpu) & ~0x783f0000ul) | flags);
138
138
kvmppc_set_pc(vcpu, kvmppc_interrupt_offset(vcpu) + vec);
139
139
vcpu->arch.mmu.reset_msr(vcpu);
140
140
}
···
256
256
{
257
257
kvmppc_set_dar(vcpu, dar);
258
258
kvmppc_set_dsisr(vcpu, flags);
259
-
kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_DATA_STORAGE);
259
+
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_DATA_STORAGE, 0);
260
260
}
261
-
EXPORT_SYMBOL_GPL(kvmppc_core_queue_data_storage); /* used by kvm_hv */
261
+
EXPORT_SYMBOL_GPL(kvmppc_core_queue_data_storage);
262
262
263
263
void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu, ulong flags)
264
264
{
265
-
u64 msr = kvmppc_get_msr(vcpu);
266
-
msr &= ~(SRR1_ISI_NOPT | SRR1_ISI_N_OR_G | SRR1_ISI_PROT);
267
-
msr |= flags & (SRR1_ISI_NOPT | SRR1_ISI_N_OR_G | SRR1_ISI_PROT);
268
-
kvmppc_set_msr_fast(vcpu, msr);
269
-
kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_INST_STORAGE);
265
+
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_INST_STORAGE, flags);
270
266
}
267
+
EXPORT_SYMBOL_GPL(kvmppc_core_queue_inst_storage);
271
268
272
269
static int kvmppc_book3s_irqprio_deliver(struct kvm_vcpu *vcpu,
273
270
unsigned int priority)
···
447
450
return r;
448
451
}
449
452
450
-
int kvmppc_load_last_inst(struct kvm_vcpu *vcpu, enum instruction_type type,
451
-
u32 *inst)
453
+
int kvmppc_load_last_inst(struct kvm_vcpu *vcpu,
454
+
enum instruction_fetch_type type, u32 *inst)
452
455
{
453
456
ulong pc = kvmppc_get_pc(vcpu);
454
457
int r;
···
506
509
{
507
510
int i;
508
511
509
-
vcpu_load(vcpu);
510
-
511
512
regs->pc = kvmppc_get_pc(vcpu);
512
513
regs->cr = kvmppc_get_cr(vcpu);
513
514
regs->ctr = kvmppc_get_ctr(vcpu);
···
527
532
for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
528
533
regs->gpr[i] = kvmppc_get_gpr(vcpu, i);
529
534
530
-
vcpu_put(vcpu);
531
535
return 0;
532
536
}
533
537
534
538
int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
535
539
{
536
540
int i;
537
-
538
-
vcpu_load(vcpu);
539
541
540
542
kvmppc_set_pc(vcpu, regs->pc);
541
543
kvmppc_set_cr(vcpu, regs->cr);
···
554
562
for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
555
563
kvmppc_set_gpr(vcpu, i, regs->gpr[i]);
556
564
557
-
vcpu_put(vcpu);
558
565
return 0;
559
566
}
560
567
+6
arch/powerpc/kvm/book3s.h
+6
arch/powerpc/kvm/book3s.h
···
31
31
extern int kvmppc_book3s_init_pr(void);
32
32
extern void kvmppc_book3s_exit_pr(void);
33
33
34
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
35
+
extern void kvmppc_emulate_tabort(struct kvm_vcpu *vcpu, int ra_val);
36
+
#else
37
+
static inline void kvmppc_emulate_tabort(struct kvm_vcpu *vcpu, int ra_val) {}
38
+
#endif
39
+
34
40
#endif
+1
-1
arch/powerpc/kvm/book3s_32_mmu.c
+1
-1
arch/powerpc/kvm/book3s_32_mmu.c
+10
-1
arch/powerpc/kvm/book3s_64_mmu.c
+10
-1
arch/powerpc/kvm/book3s_64_mmu.c
···
38
38
39
39
static void kvmppc_mmu_book3s_64_reset_msr(struct kvm_vcpu *vcpu)
40
40
{
41
-
kvmppc_set_msr(vcpu, vcpu->arch.intr_msr);
41
+
unsigned long msr = vcpu->arch.intr_msr;
42
+
unsigned long cur_msr = kvmppc_get_msr(vcpu);
43
+
44
+
/* If transactional, change to suspend mode on IRQ delivery */
45
+
if (MSR_TM_TRANSACTIONAL(cur_msr))
46
+
msr |= MSR_TS_S;
47
+
else
48
+
msr |= cur_msr & MSR_TS_MASK;
49
+
50
+
kvmppc_set_msr(vcpu, msr);
42
51
}
43
52
44
53
static struct kvmppc_slb *kvmppc_mmu_book3s_64_find_slbe(
+3
arch/powerpc/kvm/book3s_64_mmu_hv.c
+3
arch/powerpc/kvm/book3s_64_mmu_hv.c
+220
-126
arch/powerpc/kvm/book3s_64_mmu_radix.c
+220
-126
arch/powerpc/kvm/book3s_64_mmu_radix.c
···
139
139
return 0;
140
140
}
141
141
142
-
#ifdef CONFIG_PPC_64K_PAGES
143
-
#define MMU_BASE_PSIZE MMU_PAGE_64K
144
-
#else
145
-
#define MMU_BASE_PSIZE MMU_PAGE_4K
146
-
#endif
147
-
148
142
static void kvmppc_radix_tlbie_page(struct kvm *kvm, unsigned long addr,
149
143
unsigned int pshift)
150
144
{
151
-
int psize = MMU_BASE_PSIZE;
145
+
unsigned long psize = PAGE_SIZE;
152
146
153
-
if (pshift >= PUD_SHIFT)
154
-
psize = MMU_PAGE_1G;
155
-
else if (pshift >= PMD_SHIFT)
156
-
psize = MMU_PAGE_2M;
157
-
addr &= ~0xfffUL;
158
-
addr |= mmu_psize_defs[psize].ap << 5;
159
-
asm volatile("ptesync": : :"memory");
160
-
asm volatile(PPC_TLBIE_5(%0, %1, 0, 0, 1)
161
-
: : "r" (addr), "r" (kvm->arch.lpid) : "memory");
162
-
if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG))
163
-
asm volatile(PPC_TLBIE_5(%0, %1, 0, 0, 1)
164
-
: : "r" (addr), "r" (kvm->arch.lpid) : "memory");
165
-
asm volatile("eieio ; tlbsync ; ptesync": : :"memory");
147
+
if (pshift)
148
+
psize = 1UL << pshift;
149
+
150
+
addr &= ~(psize - 1);
151
+
radix__flush_tlb_lpid_page(kvm->arch.lpid, addr, psize);
166
152
}
167
153
168
-
static void kvmppc_radix_flush_pwc(struct kvm *kvm, unsigned long addr)
154
+
static void kvmppc_radix_flush_pwc(struct kvm *kvm)
169
155
{
170
-
unsigned long rb = 0x2 << PPC_BITLSHIFT(53); /* IS = 2 */
171
-
172
-
asm volatile("ptesync": : :"memory");
173
-
/* RIC=1 PRS=0 R=1 IS=2 */
174
-
asm volatile(PPC_TLBIE_5(%0, %1, 1, 0, 1)
175
-
: : "r" (rb), "r" (kvm->arch.lpid) : "memory");
176
-
asm volatile("eieio ; tlbsync ; ptesync": : :"memory");
156
+
radix__flush_pwc_lpid(kvm->arch.lpid);
177
157
}
178
158
179
-
unsigned long kvmppc_radix_update_pte(struct kvm *kvm, pte_t *ptep,
159
+
static unsigned long kvmppc_radix_update_pte(struct kvm *kvm, pte_t *ptep,
180
160
unsigned long clr, unsigned long set,
181
161
unsigned long addr, unsigned int shift)
182
162
{
···
208
228
kmem_cache_free(kvm_pmd_cache, pmdp);
209
229
}
210
230
231
+
static void kvmppc_unmap_pte(struct kvm *kvm, pte_t *pte,
232
+
unsigned long gpa, unsigned int shift)
233
+
234
+
{
235
+
unsigned long page_size = 1ul << shift;
236
+
unsigned long old;
237
+
238
+
old = kvmppc_radix_update_pte(kvm, pte, ~0UL, 0, gpa, shift);
239
+
kvmppc_radix_tlbie_page(kvm, gpa, shift);
240
+
if (old & _PAGE_DIRTY) {
241
+
unsigned long gfn = gpa >> PAGE_SHIFT;
242
+
struct kvm_memory_slot *memslot;
243
+
244
+
memslot = gfn_to_memslot(kvm, gfn);
245
+
if (memslot && memslot->dirty_bitmap)
246
+
kvmppc_update_dirty_map(memslot, gfn, page_size);
247
+
}
248
+
}
249
+
250
+
/*
251
+
* kvmppc_free_p?d are used to free existing page tables, and recursively
252
+
* descend and clear and free children.
253
+
* Callers are responsible for flushing the PWC.
254
+
*
255
+
* When page tables are being unmapped/freed as part of page fault path
256
+
* (full == false), ptes are not expected. There is code to unmap them
257
+
* and emit a warning if encountered, but there may already be data
258
+
* corruption due to the unexpected mappings.
259
+
*/
260
+
static void kvmppc_unmap_free_pte(struct kvm *kvm, pte_t *pte, bool full)
261
+
{
262
+
if (full) {
263
+
memset(pte, 0, sizeof(long) << PTE_INDEX_SIZE);
264
+
} else {
265
+
pte_t *p = pte;
266
+
unsigned long it;
267
+
268
+
for (it = 0; it < PTRS_PER_PTE; ++it, ++p) {
269
+
if (pte_val(*p) == 0)
270
+
continue;
271
+
WARN_ON_ONCE(1);
272
+
kvmppc_unmap_pte(kvm, p,
273
+
pte_pfn(*p) << PAGE_SHIFT,
274
+
PAGE_SHIFT);
275
+
}
276
+
}
277
+
278
+
kvmppc_pte_free(pte);
279
+
}
280
+
281
+
static void kvmppc_unmap_free_pmd(struct kvm *kvm, pmd_t *pmd, bool full)
282
+
{
283
+
unsigned long im;
284
+
pmd_t *p = pmd;
285
+
286
+
for (im = 0; im < PTRS_PER_PMD; ++im, ++p) {
287
+
if (!pmd_present(*p))
288
+
continue;
289
+
if (pmd_is_leaf(*p)) {
290
+
if (full) {
291
+
pmd_clear(p);
292
+
} else {
293
+
WARN_ON_ONCE(1);
294
+
kvmppc_unmap_pte(kvm, (pte_t *)p,
295
+
pte_pfn(*(pte_t *)p) << PAGE_SHIFT,
296
+
PMD_SHIFT);
297
+
}
298
+
} else {
299
+
pte_t *pte;
300
+
301
+
pte = pte_offset_map(p, 0);
302
+
kvmppc_unmap_free_pte(kvm, pte, full);
303
+
pmd_clear(p);
304
+
}
305
+
}
306
+
kvmppc_pmd_free(pmd);
307
+
}
308
+
309
+
static void kvmppc_unmap_free_pud(struct kvm *kvm, pud_t *pud)
310
+
{
311
+
unsigned long iu;
312
+
pud_t *p = pud;
313
+
314
+
for (iu = 0; iu < PTRS_PER_PUD; ++iu, ++p) {
315
+
if (!pud_present(*p))
316
+
continue;
317
+
if (pud_huge(*p)) {
318
+
pud_clear(p);
319
+
} else {
320
+
pmd_t *pmd;
321
+
322
+
pmd = pmd_offset(p, 0);
323
+
kvmppc_unmap_free_pmd(kvm, pmd, true);
324
+
pud_clear(p);
325
+
}
326
+
}
327
+
pud_free(kvm->mm, pud);
328
+
}
329
+
330
+
void kvmppc_free_radix(struct kvm *kvm)
331
+
{
332
+
unsigned long ig;
333
+
pgd_t *pgd;
334
+
335
+
if (!kvm->arch.pgtable)
336
+
return;
337
+
pgd = kvm->arch.pgtable;
338
+
for (ig = 0; ig < PTRS_PER_PGD; ++ig, ++pgd) {
339
+
pud_t *pud;
340
+
341
+
if (!pgd_present(*pgd))
342
+
continue;
343
+
pud = pud_offset(pgd, 0);
344
+
kvmppc_unmap_free_pud(kvm, pud);
345
+
pgd_clear(pgd);
346
+
}
347
+
pgd_free(kvm->mm, kvm->arch.pgtable);
348
+
kvm->arch.pgtable = NULL;
349
+
}
350
+
351
+
static void kvmppc_unmap_free_pmd_entry_table(struct kvm *kvm, pmd_t *pmd,
352
+
unsigned long gpa)
353
+
{
354
+
pte_t *pte = pte_offset_kernel(pmd, 0);
355
+
356
+
/*
357
+
* Clearing the pmd entry then flushing the PWC ensures that the pte
358
+
* page no longer be cached by the MMU, so can be freed without
359
+
* flushing the PWC again.
360
+
*/
361
+
pmd_clear(pmd);
362
+
kvmppc_radix_flush_pwc(kvm);
363
+
364
+
kvmppc_unmap_free_pte(kvm, pte, false);
365
+
}
366
+
367
+
static void kvmppc_unmap_free_pud_entry_table(struct kvm *kvm, pud_t *pud,
368
+
unsigned long gpa)
369
+
{
370
+
pmd_t *pmd = pmd_offset(pud, 0);
371
+
372
+
/*
373
+
* Clearing the pud entry then flushing the PWC ensures that the pmd
374
+
* page and any children pte pages will no longer be cached by the MMU,
375
+
* so can be freed without flushing the PWC again.
376
+
*/
377
+
pud_clear(pud);
378
+
kvmppc_radix_flush_pwc(kvm);
379
+
380
+
kvmppc_unmap_free_pmd(kvm, pmd, false);
381
+
}
382
+
383
+
/*
384
+
* There are a number of bits which may differ between different faults to
385
+
* the same partition scope entry. RC bits, in the course of cleaning and
386
+
* aging. And the write bit can change, either the access could have been
387
+
* upgraded, or a read fault could happen concurrently with a write fault
388
+
* that sets those bits first.
389
+
*/
390
+
#define PTE_BITS_MUST_MATCH (~(_PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED))
391
+
211
392
static int kvmppc_create_pte(struct kvm *kvm, pte_t pte, unsigned long gpa,
212
393
unsigned int level, unsigned long mmu_seq)
213
394
{
···
376
235
pud_t *pud, *new_pud = NULL;
377
236
pmd_t *pmd, *new_pmd = NULL;
378
237
pte_t *ptep, *new_ptep = NULL;
379
-
unsigned long old;
380
238
int ret;
381
239
382
240
/* Traverse the guest's 2nd-level tree, allocate new levels needed */
···
413
273
if (pud_huge(*pud)) {
414
274
unsigned long hgpa = gpa & PUD_MASK;
415
275
276
+
/* Check if we raced and someone else has set the same thing */
277
+
if (level == 2) {
278
+
if (pud_raw(*pud) == pte_raw(pte)) {
279
+
ret = 0;
280
+
goto out_unlock;
281
+
}
282
+
/* Valid 1GB page here already, add our extra bits */
283
+
WARN_ON_ONCE((pud_val(*pud) ^ pte_val(pte)) &
284
+
PTE_BITS_MUST_MATCH);
285
+
kvmppc_radix_update_pte(kvm, (pte_t *)pud,
286
+
0, pte_val(pte), hgpa, PUD_SHIFT);
287
+
ret = 0;
288
+
goto out_unlock;
289
+
}
416
290
/*
417
291
* If we raced with another CPU which has just put
418
292
* a 1GB pte in after we saw a pmd page, try again.
419
293
*/
420
-
if (level <= 1 && !new_pmd) {
294
+
if (!new_pmd) {
421
295
ret = -EAGAIN;
422
296
goto out_unlock;
423
297
}
424
-
/* Check if we raced and someone else has set the same thing */
425
-
if (level == 2 && pud_raw(*pud) == pte_raw(pte)) {
426
-
ret = 0;
427
-
goto out_unlock;
428
-
}
429
298
/* Valid 1GB page here already, remove it */
430
-
old = kvmppc_radix_update_pte(kvm, (pte_t *)pud,
431
-
~0UL, 0, hgpa, PUD_SHIFT);
432
-
kvmppc_radix_tlbie_page(kvm, hgpa, PUD_SHIFT);
433
-
if (old & _PAGE_DIRTY) {
434
-
unsigned long gfn = hgpa >> PAGE_SHIFT;
435
-
struct kvm_memory_slot *memslot;
436
-
memslot = gfn_to_memslot(kvm, gfn);
437
-
if (memslot && memslot->dirty_bitmap)
438
-
kvmppc_update_dirty_map(memslot,
439
-
gfn, PUD_SIZE);
440
-
}
299
+
kvmppc_unmap_pte(kvm, (pte_t *)pud, hgpa, PUD_SHIFT);
441
300
}
442
301
if (level == 2) {
443
302
if (!pud_none(*pud)) {
444
303
/*
445
304
* There's a page table page here, but we wanted to
446
305
* install a large page, so remove and free the page
447
-
* table page. new_pmd will be NULL since level == 2.
306
+
* table page.
448
307
*/
449
-
new_pmd = pmd_offset(pud, 0);
450
-
pud_clear(pud);
451
-
kvmppc_radix_flush_pwc(kvm, gpa);
308
+
kvmppc_unmap_free_pud_entry_table(kvm, pud, gpa);
452
309
}
453
310
kvmppc_radix_set_pte_at(kvm, gpa, (pte_t *)pud, pte);
454
311
ret = 0;
···
461
324
if (pmd_is_leaf(*pmd)) {
462
325
unsigned long lgpa = gpa & PMD_MASK;
463
326
327
+
/* Check if we raced and someone else has set the same thing */
328
+
if (level == 1) {
329
+
if (pmd_raw(*pmd) == pte_raw(pte)) {
330
+
ret = 0;
331
+
goto out_unlock;
332
+
}
333
+
/* Valid 2MB page here already, add our extra bits */
334
+
WARN_ON_ONCE((pmd_val(*pmd) ^ pte_val(pte)) &
335
+
PTE_BITS_MUST_MATCH);
336
+
kvmppc_radix_update_pte(kvm, pmdp_ptep(pmd),
337
+
0, pte_val(pte), lgpa, PMD_SHIFT);
338
+
ret = 0;
339
+
goto out_unlock;
340
+
}
341
+
464
342
/*
465
343
* If we raced with another CPU which has just put
466
344
* a 2MB pte in after we saw a pte page, try again.
467
345
*/
468
-
if (level == 0 && !new_ptep) {
346
+
if (!new_ptep) {
469
347
ret = -EAGAIN;
470
348
goto out_unlock;
471
349
}
472
-
/* Check if we raced and someone else has set the same thing */
473
-
if (level == 1 && pmd_raw(*pmd) == pte_raw(pte)) {
474
-
ret = 0;
475
-
goto out_unlock;
476
-
}
477
350
/* Valid 2MB page here already, remove it */
478
-
old = kvmppc_radix_update_pte(kvm, pmdp_ptep(pmd),
479
-
~0UL, 0, lgpa, PMD_SHIFT);
480
-
kvmppc_radix_tlbie_page(kvm, lgpa, PMD_SHIFT);
481
-
if (old & _PAGE_DIRTY) {
482
-
unsigned long gfn = lgpa >> PAGE_SHIFT;
483
-
struct kvm_memory_slot *memslot;
484
-
memslot = gfn_to_memslot(kvm, gfn);
485
-
if (memslot && memslot->dirty_bitmap)
486
-
kvmppc_update_dirty_map(memslot,
487
-
gfn, PMD_SIZE);
488
-
}
351
+
kvmppc_unmap_pte(kvm, pmdp_ptep(pmd), lgpa, PMD_SHIFT);
489
352
}
490
353
if (level == 1) {
491
354
if (!pmd_none(*pmd)) {
492
355
/*
493
356
* There's a page table page here, but we wanted to
494
357
* install a large page, so remove and free the page
495
-
* table page. new_ptep will be NULL since level == 1.
358
+
* table page.
496
359
*/
497
-
new_ptep = pte_offset_kernel(pmd, 0);
498
-
pmd_clear(pmd);
499
-
kvmppc_radix_flush_pwc(kvm, gpa);
360
+
kvmppc_unmap_free_pmd_entry_table(kvm, pmd, gpa);
500
361
}
501
362
kvmppc_radix_set_pte_at(kvm, gpa, pmdp_ptep(pmd), pte);
502
363
ret = 0;
···
513
378
ret = 0;
514
379
goto out_unlock;
515
380
}
516
-
/* PTE was previously valid, so invalidate it */
517
-
old = kvmppc_radix_update_pte(kvm, ptep, _PAGE_PRESENT,
518
-
0, gpa, 0);
519
-
kvmppc_radix_tlbie_page(kvm, gpa, 0);
520
-
if (old & _PAGE_DIRTY)
521
-
mark_page_dirty(kvm, gpa >> PAGE_SHIFT);
381
+
/* Valid page here already, add our extra bits */
382
+
WARN_ON_ONCE((pte_val(*ptep) ^ pte_val(pte)) &
383
+
PTE_BITS_MUST_MATCH);
384
+
kvmppc_radix_update_pte(kvm, ptep, 0, pte_val(pte), gpa, 0);
385
+
ret = 0;
386
+
goto out_unlock;
522
387
}
523
388
kvmppc_radix_set_pte_at(kvm, gpa, ptep, pte);
524
389
ret = 0;
···
700
565
unsigned long mask = (1ul << shift) - PAGE_SIZE;
701
566
pte = __pte(pte_val(pte) | (hva & mask));
702
567
}
703
-
if (!(writing || upgrade_write))
704
-
pte = __pte(pte_val(pte) & ~ _PAGE_WRITE);
705
-
pte = __pte(pte_val(pte) | _PAGE_EXEC);
568
+
pte = __pte(pte_val(pte) | _PAGE_EXEC | _PAGE_ACCESSED);
569
+
if (writing || upgrade_write) {
570
+
if (pte_val(pte) & _PAGE_WRITE)
571
+
pte = __pte(pte_val(pte) | _PAGE_DIRTY);
572
+
} else {
573
+
pte = __pte(pte_val(pte) & ~(_PAGE_WRITE | _PAGE_DIRTY));
574
+
}
706
575
}
707
576
708
577
/* Allocate space in the tree and write the PTE */
···
871
732
if (!kvm->arch.pgtable)
872
733
return -ENOMEM;
873
734
return 0;
874
-
}
875
-
876
-
void kvmppc_free_radix(struct kvm *kvm)
877
-
{
878
-
unsigned long ig, iu, im;
879
-
pte_t *pte;
880
-
pmd_t *pmd;
881
-
pud_t *pud;
882
-
pgd_t *pgd;
883
-
884
-
if (!kvm->arch.pgtable)
885
-
return;
886
-
pgd = kvm->arch.pgtable;
887
-
for (ig = 0; ig < PTRS_PER_PGD; ++ig, ++pgd) {
888
-
if (!pgd_present(*pgd))
889
-
continue;
890
-
pud = pud_offset(pgd, 0);
891
-
for (iu = 0; iu < PTRS_PER_PUD; ++iu, ++pud) {
892
-
if (!pud_present(*pud))
893
-
continue;
894
-
if (pud_huge(*pud)) {
895
-
pud_clear(pud);
896
-
continue;
897
-
}
898
-
pmd = pmd_offset(pud, 0);
899
-
for (im = 0; im < PTRS_PER_PMD; ++im, ++pmd) {
900
-
if (pmd_is_leaf(*pmd)) {
901
-
pmd_clear(pmd);
902
-
continue;
903
-
}
904
-
if (!pmd_present(*pmd))
905
-
continue;
906
-
pte = pte_offset_map(pmd, 0);
907
-
memset(pte, 0, sizeof(long) << PTE_INDEX_SIZE);
908
-
kvmppc_pte_free(pte);
909
-
pmd_clear(pmd);
910
-
}
911
-
kvmppc_pmd_free(pmd_offset(pud, 0));
912
-
pud_clear(pud);
913
-
}
914
-
pud_free(kvm->mm, pud_offset(pgd, 0));
915
-
pgd_clear(pgd);
916
-
}
917
-
pgd_free(kvm->mm, kvm->arch.pgtable);
918
-
kvm->arch.pgtable = NULL;
919
735
}
920
736
921
737
static void pte_ctor(void *addr)
+54
-17
arch/powerpc/kvm/book3s_64_vio.c
+54
-17
arch/powerpc/kvm/book3s_64_vio.c
···
176
176
177
177
if (!tbltmp)
178
178
continue;
179
-
/*
180
-
* Make sure hardware table parameters are exactly the same;
181
-
* this is used in the TCE handlers where boundary checks
182
-
* use only the first attached table.
183
-
*/
184
-
if ((tbltmp->it_page_shift == stt->page_shift) &&
185
-
(tbltmp->it_offset == stt->offset) &&
186
-
(tbltmp->it_size == stt->size)) {
179
+
/* Make sure hardware table parameters are compatible */
180
+
if ((tbltmp->it_page_shift <= stt->page_shift) &&
181
+
(tbltmp->it_offset << tbltmp->it_page_shift ==
182
+
stt->offset << stt->page_shift) &&
183
+
(tbltmp->it_size << tbltmp->it_page_shift ==
184
+
stt->size << stt->page_shift)) {
187
185
/*
188
186
* Reference the table to avoid races with
189
187
* add/remove DMA windows.
···
235
237
kfree(stt);
236
238
}
237
239
238
-
static int kvm_spapr_tce_fault(struct vm_fault *vmf)
240
+
static vm_fault_t kvm_spapr_tce_fault(struct vm_fault *vmf)
239
241
{
240
242
struct kvmppc_spapr_tce_table *stt = vmf->vma->vm_file->private_data;
241
243
struct page *page;
···
300
302
int ret = -ENOMEM;
301
303
int i;
302
304
303
-
if (!args->size)
305
+
if (!args->size || args->page_shift < 12 || args->page_shift > 34 ||
306
+
(args->offset + args->size > (ULLONG_MAX >> args->page_shift)))
304
307
return -EINVAL;
305
308
306
309
size = _ALIGN_UP(args->size, PAGE_SIZE >> 3);
···
395
396
return H_SUCCESS;
396
397
}
397
398
398
-
static long kvmppc_tce_iommu_unmap(struct kvm *kvm,
399
+
static long kvmppc_tce_iommu_do_unmap(struct kvm *kvm,
399
400
struct iommu_table *tbl, unsigned long entry)
400
401
{
401
402
enum dma_data_direction dir = DMA_NONE;
···
415
416
return ret;
416
417
}
417
418
418
-
long kvmppc_tce_iommu_map(struct kvm *kvm, struct iommu_table *tbl,
419
+
static long kvmppc_tce_iommu_unmap(struct kvm *kvm,
420
+
struct kvmppc_spapr_tce_table *stt, struct iommu_table *tbl,
421
+
unsigned long entry)
422
+
{
423
+
unsigned long i, ret = H_SUCCESS;
424
+
unsigned long subpages = 1ULL << (stt->page_shift - tbl->it_page_shift);
425
+
unsigned long io_entry = entry * subpages;
426
+
427
+
for (i = 0; i < subpages; ++i) {
428
+
ret = kvmppc_tce_iommu_do_unmap(kvm, tbl, io_entry + i);
429
+
if (ret != H_SUCCESS)
430
+
break;
431
+
}
432
+
433
+
return ret;
434
+
}
435
+
436
+
long kvmppc_tce_iommu_do_map(struct kvm *kvm, struct iommu_table *tbl,
419
437
unsigned long entry, unsigned long ua,
420
438
enum dma_data_direction dir)
421
439
{
···
467
451
*pua = ua;
468
452
469
453
return 0;
454
+
}
455
+
456
+
static long kvmppc_tce_iommu_map(struct kvm *kvm,
457
+
struct kvmppc_spapr_tce_table *stt, struct iommu_table *tbl,
458
+
unsigned long entry, unsigned long ua,
459
+
enum dma_data_direction dir)
460
+
{
461
+
unsigned long i, pgoff, ret = H_SUCCESS;
462
+
unsigned long subpages = 1ULL << (stt->page_shift - tbl->it_page_shift);
463
+
unsigned long io_entry = entry * subpages;
464
+
465
+
for (i = 0, pgoff = 0; i < subpages;
466
+
++i, pgoff += IOMMU_PAGE_SIZE(tbl)) {
467
+
468
+
ret = kvmppc_tce_iommu_do_map(kvm, tbl,
469
+
io_entry + i, ua + pgoff, dir);
470
+
if (ret != H_SUCCESS)
471
+
break;
472
+
}
473
+
474
+
return ret;
470
475
}
471
476
472
477
long kvmppc_h_put_tce(struct kvm_vcpu *vcpu, unsigned long liobn,
···
528
491
529
492
list_for_each_entry_lockless(stit, &stt->iommu_tables, next) {
530
493
if (dir == DMA_NONE)
531
-
ret = kvmppc_tce_iommu_unmap(vcpu->kvm,
494
+
ret = kvmppc_tce_iommu_unmap(vcpu->kvm, stt,
532
495
stit->tbl, entry);
533
496
else
534
-
ret = kvmppc_tce_iommu_map(vcpu->kvm, stit->tbl,
497
+
ret = kvmppc_tce_iommu_map(vcpu->kvm, stt, stit->tbl,
535
498
entry, ua, dir);
536
499
537
500
if (ret == H_SUCCESS)
···
607
570
return H_PARAMETER;
608
571
609
572
list_for_each_entry_lockless(stit, &stt->iommu_tables, next) {
610
-
ret = kvmppc_tce_iommu_map(vcpu->kvm,
573
+
ret = kvmppc_tce_iommu_map(vcpu->kvm, stt,
611
574
stit->tbl, entry + i, ua,
612
575
iommu_tce_direction(tce));
613
576
···
652
615
return H_PARAMETER;
653
616
654
617
list_for_each_entry_lockless(stit, &stt->iommu_tables, next) {
655
-
unsigned long entry = ioba >> stit->tbl->it_page_shift;
618
+
unsigned long entry = ioba >> stt->page_shift;
656
619
657
620
for (i = 0; i < npages; ++i) {
658
-
ret = kvmppc_tce_iommu_unmap(vcpu->kvm,
621
+
ret = kvmppc_tce_iommu_unmap(vcpu->kvm, stt,
659
622
stit->tbl, entry + i);
660
623
661
624
if (ret == H_SUCCESS)
+46
-8
arch/powerpc/kvm/book3s_64_vio_hv.c
+46
-8
arch/powerpc/kvm/book3s_64_vio_hv.c
···
221
221
return H_SUCCESS;
222
222
}
223
223
224
-
static long kvmppc_rm_tce_iommu_unmap(struct kvm *kvm,
224
+
static long kvmppc_rm_tce_iommu_do_unmap(struct kvm *kvm,
225
225
struct iommu_table *tbl, unsigned long entry)
226
226
{
227
227
enum dma_data_direction dir = DMA_NONE;
···
245
245
return ret;
246
246
}
247
247
248
-
static long kvmppc_rm_tce_iommu_map(struct kvm *kvm, struct iommu_table *tbl,
248
+
static long kvmppc_rm_tce_iommu_unmap(struct kvm *kvm,
249
+
struct kvmppc_spapr_tce_table *stt, struct iommu_table *tbl,
250
+
unsigned long entry)
251
+
{
252
+
unsigned long i, ret = H_SUCCESS;
253
+
unsigned long subpages = 1ULL << (stt->page_shift - tbl->it_page_shift);
254
+
unsigned long io_entry = entry * subpages;
255
+
256
+
for (i = 0; i < subpages; ++i) {
257
+
ret = kvmppc_rm_tce_iommu_do_unmap(kvm, tbl, io_entry + i);
258
+
if (ret != H_SUCCESS)
259
+
break;
260
+
}
261
+
262
+
return ret;
263
+
}
264
+
265
+
static long kvmppc_rm_tce_iommu_do_map(struct kvm *kvm, struct iommu_table *tbl,
249
266
unsigned long entry, unsigned long ua,
250
267
enum dma_data_direction dir)
251
268
{
···
307
290
return 0;
308
291
}
309
292
293
+
static long kvmppc_rm_tce_iommu_map(struct kvm *kvm,
294
+
struct kvmppc_spapr_tce_table *stt, struct iommu_table *tbl,
295
+
unsigned long entry, unsigned long ua,
296
+
enum dma_data_direction dir)
297
+
{
298
+
unsigned long i, pgoff, ret = H_SUCCESS;
299
+
unsigned long subpages = 1ULL << (stt->page_shift - tbl->it_page_shift);
300
+
unsigned long io_entry = entry * subpages;
301
+
302
+
for (i = 0, pgoff = 0; i < subpages;
303
+
++i, pgoff += IOMMU_PAGE_SIZE(tbl)) {
304
+
305
+
ret = kvmppc_rm_tce_iommu_do_map(kvm, tbl,
306
+
io_entry + i, ua + pgoff, dir);
307
+
if (ret != H_SUCCESS)
308
+
break;
309
+
}
310
+
311
+
return ret;
312
+
}
313
+
310
314
long kvmppc_rm_h_put_tce(struct kvm_vcpu *vcpu, unsigned long liobn,
311
315
unsigned long ioba, unsigned long tce)
312
316
{
···
365
327
366
328
list_for_each_entry_lockless(stit, &stt->iommu_tables, next) {
367
329
if (dir == DMA_NONE)
368
-
ret = kvmppc_rm_tce_iommu_unmap(vcpu->kvm,
330
+
ret = kvmppc_rm_tce_iommu_unmap(vcpu->kvm, stt,
369
331
stit->tbl, entry);
370
332
else
371
-
ret = kvmppc_rm_tce_iommu_map(vcpu->kvm,
333
+
ret = kvmppc_rm_tce_iommu_map(vcpu->kvm, stt,
372
334
stit->tbl, entry, ua, dir);
373
335
374
336
if (ret == H_SUCCESS)
···
515
477
return H_PARAMETER;
516
478
517
479
list_for_each_entry_lockless(stit, &stt->iommu_tables, next) {
518
-
ret = kvmppc_rm_tce_iommu_map(vcpu->kvm,
480
+
ret = kvmppc_rm_tce_iommu_map(vcpu->kvm, stt,
519
481
stit->tbl, entry + i, ua,
520
482
iommu_tce_direction(tce));
521
483
···
564
526
return H_PARAMETER;
565
527
566
528
list_for_each_entry_lockless(stit, &stt->iommu_tables, next) {
567
-
unsigned long entry = ioba >> stit->tbl->it_page_shift;
529
+
unsigned long entry = ioba >> stt->page_shift;
568
530
569
531
for (i = 0; i < npages; ++i) {
570
-
ret = kvmppc_rm_tce_iommu_unmap(vcpu->kvm,
532
+
ret = kvmppc_rm_tce_iommu_unmap(vcpu->kvm, stt,
571
533
stit->tbl, entry + i);
572
534
573
535
if (ret == H_SUCCESS)
···
609
571
page = stt->pages[idx / TCES_PER_PAGE];
610
572
tbl = (u64 *)page_address(page);
611
573
612
-
vcpu->arch.gpr[4] = tbl[idx % TCES_PER_PAGE];
574
+
vcpu->arch.regs.gpr[4] = tbl[idx % TCES_PER_PAGE];
613
575
614
576
return H_SUCCESS;
615
577
}
+359
-12
arch/powerpc/kvm/book3s_emulate.c
+359
-12
arch/powerpc/kvm/book3s_emulate.c
···
23
23
#include <asm/reg.h>
24
24
#include <asm/switch_to.h>
25
25
#include <asm/time.h>
26
+
#include <asm/tm.h>
26
27
#include "book3s.h"
28
+
#include <asm/asm-prototypes.h>
27
29
28
30
#define OP_19_XOP_RFID 18
29
31
#define OP_19_XOP_RFI 50
···
48
46
#define OP_31_XOP_SLBMFEV 851
49
47
#define OP_31_XOP_EIOIO 854
50
48
#define OP_31_XOP_SLBMFEE 915
49
+
50
+
#define OP_31_XOP_TBEGIN 654
51
+
#define OP_31_XOP_TABORT 910
52
+
53
+
#define OP_31_XOP_TRECLAIM 942
54
+
#define OP_31_XOP_TRCHKPT 1006
51
55
52
56
/* DCBZ is actually 1014, but we patch it to 1010 so we get a trap */
53
57
#define OP_31_XOP_DCBZ 1010
···
95
87
return true;
96
88
}
97
89
90
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
91
+
static inline void kvmppc_copyto_vcpu_tm(struct kvm_vcpu *vcpu)
92
+
{
93
+
memcpy(&vcpu->arch.gpr_tm[0], &vcpu->arch.regs.gpr[0],
94
+
sizeof(vcpu->arch.gpr_tm));
95
+
memcpy(&vcpu->arch.fp_tm, &vcpu->arch.fp,
96
+
sizeof(struct thread_fp_state));
97
+
memcpy(&vcpu->arch.vr_tm, &vcpu->arch.vr,
98
+
sizeof(struct thread_vr_state));
99
+
vcpu->arch.ppr_tm = vcpu->arch.ppr;
100
+
vcpu->arch.dscr_tm = vcpu->arch.dscr;
101
+
vcpu->arch.amr_tm = vcpu->arch.amr;
102
+
vcpu->arch.ctr_tm = vcpu->arch.regs.ctr;
103
+
vcpu->arch.tar_tm = vcpu->arch.tar;
104
+
vcpu->arch.lr_tm = vcpu->arch.regs.link;
105
+
vcpu->arch.cr_tm = vcpu->arch.cr;
106
+
vcpu->arch.xer_tm = vcpu->arch.regs.xer;
107
+
vcpu->arch.vrsave_tm = vcpu->arch.vrsave;
108
+
}
109
+
110
+
static inline void kvmppc_copyfrom_vcpu_tm(struct kvm_vcpu *vcpu)
111
+
{
112
+
memcpy(&vcpu->arch.regs.gpr[0], &vcpu->arch.gpr_tm[0],
113
+
sizeof(vcpu->arch.regs.gpr));
114
+
memcpy(&vcpu->arch.fp, &vcpu->arch.fp_tm,
115
+
sizeof(struct thread_fp_state));
116
+
memcpy(&vcpu->arch.vr, &vcpu->arch.vr_tm,
117
+
sizeof(struct thread_vr_state));
118
+
vcpu->arch.ppr = vcpu->arch.ppr_tm;
119
+
vcpu->arch.dscr = vcpu->arch.dscr_tm;
120
+
vcpu->arch.amr = vcpu->arch.amr_tm;
121
+
vcpu->arch.regs.ctr = vcpu->arch.ctr_tm;
122
+
vcpu->arch.tar = vcpu->arch.tar_tm;
123
+
vcpu->arch.regs.link = vcpu->arch.lr_tm;
124
+
vcpu->arch.cr = vcpu->arch.cr_tm;
125
+
vcpu->arch.regs.xer = vcpu->arch.xer_tm;
126
+
vcpu->arch.vrsave = vcpu->arch.vrsave_tm;
127
+
}
128
+
129
+
static void kvmppc_emulate_treclaim(struct kvm_vcpu *vcpu, int ra_val)
130
+
{
131
+
unsigned long guest_msr = kvmppc_get_msr(vcpu);
132
+
int fc_val = ra_val ? ra_val : 1;
133
+
uint64_t texasr;
134
+
135
+
/* CR0 = 0 | MSR[TS] | 0 */
136
+
vcpu->arch.cr = (vcpu->arch.cr & ~(CR0_MASK << CR0_SHIFT)) |
137
+
(((guest_msr & MSR_TS_MASK) >> (MSR_TS_S_LG - 1))
138
+
<< CR0_SHIFT);
139
+
140
+
preempt_disable();
141
+
tm_enable();
142
+
texasr = mfspr(SPRN_TEXASR);
143
+
kvmppc_save_tm_pr(vcpu);
144
+
kvmppc_copyfrom_vcpu_tm(vcpu);
145
+
146
+
/* failure recording depends on Failure Summary bit */
147
+
if (!(texasr & TEXASR_FS)) {
148
+
texasr &= ~TEXASR_FC;
149
+
texasr |= ((u64)fc_val << TEXASR_FC_LG) | TEXASR_FS;
150
+
151
+
texasr &= ~(TEXASR_PR | TEXASR_HV);
152
+
if (kvmppc_get_msr(vcpu) & MSR_PR)
153
+
texasr |= TEXASR_PR;
154
+
155
+
if (kvmppc_get_msr(vcpu) & MSR_HV)
156
+
texasr |= TEXASR_HV;
157
+
158
+
vcpu->arch.texasr = texasr;
159
+
vcpu->arch.tfiar = kvmppc_get_pc(vcpu);
160
+
mtspr(SPRN_TEXASR, texasr);
161
+
mtspr(SPRN_TFIAR, vcpu->arch.tfiar);
162
+
}
163
+
tm_disable();
164
+
/*
165
+
* treclaim need quit to non-transactional state.
166
+
*/
167
+
guest_msr &= ~(MSR_TS_MASK);
168
+
kvmppc_set_msr(vcpu, guest_msr);
169
+
preempt_enable();
170
+
171
+
if (vcpu->arch.shadow_fscr & FSCR_TAR)
172
+
mtspr(SPRN_TAR, vcpu->arch.tar);
173
+
}
174
+
175
+
static void kvmppc_emulate_trchkpt(struct kvm_vcpu *vcpu)
176
+
{
177
+
unsigned long guest_msr = kvmppc_get_msr(vcpu);
178
+
179
+
preempt_disable();
180
+
/*
181
+
* need flush FP/VEC/VSX to vcpu save area before
182
+
* copy.
183
+
*/
184
+
kvmppc_giveup_ext(vcpu, MSR_VSX);
185
+
kvmppc_giveup_fac(vcpu, FSCR_TAR_LG);
186
+
kvmppc_copyto_vcpu_tm(vcpu);
187
+
kvmppc_save_tm_sprs(vcpu);
188
+
189
+
/*
190
+
* as a result of trecheckpoint. set TS to suspended.
191
+
*/
192
+
guest_msr &= ~(MSR_TS_MASK);
193
+
guest_msr |= MSR_TS_S;
194
+
kvmppc_set_msr(vcpu, guest_msr);
195
+
kvmppc_restore_tm_pr(vcpu);
196
+
preempt_enable();
197
+
}
198
+
199
+
/* emulate tabort. at guest privilege state */
200
+
void kvmppc_emulate_tabort(struct kvm_vcpu *vcpu, int ra_val)
201
+
{
202
+
/* currently we only emulate tabort. but no emulation of other
203
+
* tabort variants since there is no kernel usage of them at
204
+
* present.
205
+
*/
206
+
unsigned long guest_msr = kvmppc_get_msr(vcpu);
207
+
uint64_t org_texasr;
208
+
209
+
preempt_disable();
210
+
tm_enable();
211
+
org_texasr = mfspr(SPRN_TEXASR);
212
+
tm_abort(ra_val);
213
+
214
+
/* CR0 = 0 | MSR[TS] | 0 */
215
+
vcpu->arch.cr = (vcpu->arch.cr & ~(CR0_MASK << CR0_SHIFT)) |
216
+
(((guest_msr & MSR_TS_MASK) >> (MSR_TS_S_LG - 1))
217
+
<< CR0_SHIFT);
218
+
219
+
vcpu->arch.texasr = mfspr(SPRN_TEXASR);
220
+
/* failure recording depends on Failure Summary bit,
221
+
* and tabort will be treated as nops in non-transactional
222
+
* state.
223
+
*/
224
+
if (!(org_texasr & TEXASR_FS) &&
225
+
MSR_TM_ACTIVE(guest_msr)) {
226
+
vcpu->arch.texasr &= ~(TEXASR_PR | TEXASR_HV);
227
+
if (guest_msr & MSR_PR)
228
+
vcpu->arch.texasr |= TEXASR_PR;
229
+
230
+
if (guest_msr & MSR_HV)
231
+
vcpu->arch.texasr |= TEXASR_HV;
232
+
233
+
vcpu->arch.tfiar = kvmppc_get_pc(vcpu);
234
+
}
235
+
tm_disable();
236
+
preempt_enable();
237
+
}
238
+
239
+
#endif
240
+
98
241
int kvmppc_core_emulate_op_pr(struct kvm_run *run, struct kvm_vcpu *vcpu,
99
242
unsigned int inst, int *advance)
100
243
{
···
276
117
case 19:
277
118
switch (get_xop(inst)) {
278
119
case OP_19_XOP_RFID:
279
-
case OP_19_XOP_RFI:
120
+
case OP_19_XOP_RFI: {
121
+
unsigned long srr1 = kvmppc_get_srr1(vcpu);
122
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
123
+
unsigned long cur_msr = kvmppc_get_msr(vcpu);
124
+
125
+
/*
126
+
* add rules to fit in ISA specification regarding TM
127
+
* state transistion in TM disable/Suspended state,
128
+
* and target TM state is TM inactive(00) state. (the
129
+
* change should be suppressed).
130
+
*/
131
+
if (((cur_msr & MSR_TM) == 0) &&
132
+
((srr1 & MSR_TM) == 0) &&
133
+
MSR_TM_SUSPENDED(cur_msr) &&
134
+
!MSR_TM_ACTIVE(srr1))
135
+
srr1 |= MSR_TS_S;
136
+
#endif
280
137
kvmppc_set_pc(vcpu, kvmppc_get_srr0(vcpu));
281
-
kvmppc_set_msr(vcpu, kvmppc_get_srr1(vcpu));
138
+
kvmppc_set_msr(vcpu, srr1);
282
139
*advance = 0;
283
140
break;
141
+
}
284
142
285
143
default:
286
144
emulated = EMULATE_FAIL;
···
480
304
481
305
break;
482
306
}
307
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
308
+
case OP_31_XOP_TBEGIN:
309
+
{
310
+
if (!cpu_has_feature(CPU_FTR_TM))
311
+
break;
312
+
313
+
if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
314
+
kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
315
+
emulated = EMULATE_AGAIN;
316
+
break;
317
+
}
318
+
319
+
if (!(kvmppc_get_msr(vcpu) & MSR_PR)) {
320
+
preempt_disable();
321
+
vcpu->arch.cr = (CR0_TBEGIN_FAILURE |
322
+
(vcpu->arch.cr & ~(CR0_MASK << CR0_SHIFT)));
323
+
324
+
vcpu->arch.texasr = (TEXASR_FS | TEXASR_EXACT |
325
+
(((u64)(TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
326
+
<< TEXASR_FC_LG));
327
+
328
+
if ((inst >> 21) & 0x1)
329
+
vcpu->arch.texasr |= TEXASR_ROT;
330
+
331
+
if (kvmppc_get_msr(vcpu) & MSR_HV)
332
+
vcpu->arch.texasr |= TEXASR_HV;
333
+
334
+
vcpu->arch.tfhar = kvmppc_get_pc(vcpu) + 4;
335
+
vcpu->arch.tfiar = kvmppc_get_pc(vcpu);
336
+
337
+
kvmppc_restore_tm_sprs(vcpu);
338
+
preempt_enable();
339
+
} else
340
+
emulated = EMULATE_FAIL;
341
+
break;
342
+
}
343
+
case OP_31_XOP_TABORT:
344
+
{
345
+
ulong guest_msr = kvmppc_get_msr(vcpu);
346
+
unsigned long ra_val = 0;
347
+
348
+
if (!cpu_has_feature(CPU_FTR_TM))
349
+
break;
350
+
351
+
if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
352
+
kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
353
+
emulated = EMULATE_AGAIN;
354
+
break;
355
+
}
356
+
357
+
/* only emulate for privilege guest, since problem state
358
+
* guest can run with TM enabled and we don't expect to
359
+
* trap at here for that case.
360
+
*/
361
+
WARN_ON(guest_msr & MSR_PR);
362
+
363
+
if (ra)
364
+
ra_val = kvmppc_get_gpr(vcpu, ra);
365
+
366
+
kvmppc_emulate_tabort(vcpu, ra_val);
367
+
break;
368
+
}
369
+
case OP_31_XOP_TRECLAIM:
370
+
{
371
+
ulong guest_msr = kvmppc_get_msr(vcpu);
372
+
unsigned long ra_val = 0;
373
+
374
+
if (!cpu_has_feature(CPU_FTR_TM))
375
+
break;
376
+
377
+
if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
378
+
kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
379
+
emulated = EMULATE_AGAIN;
380
+
break;
381
+
}
382
+
383
+
/* generate interrupts based on priorities */
384
+
if (guest_msr & MSR_PR) {
385
+
/* Privileged Instruction type Program Interrupt */
386
+
kvmppc_core_queue_program(vcpu, SRR1_PROGPRIV);
387
+
emulated = EMULATE_AGAIN;
388
+
break;
389
+
}
390
+
391
+
if (!MSR_TM_ACTIVE(guest_msr)) {
392
+
/* TM bad thing interrupt */
393
+
kvmppc_core_queue_program(vcpu, SRR1_PROGTM);
394
+
emulated = EMULATE_AGAIN;
395
+
break;
396
+
}
397
+
398
+
if (ra)
399
+
ra_val = kvmppc_get_gpr(vcpu, ra);
400
+
kvmppc_emulate_treclaim(vcpu, ra_val);
401
+
break;
402
+
}
403
+
case OP_31_XOP_TRCHKPT:
404
+
{
405
+
ulong guest_msr = kvmppc_get_msr(vcpu);
406
+
unsigned long texasr;
407
+
408
+
if (!cpu_has_feature(CPU_FTR_TM))
409
+
break;
410
+
411
+
if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
412
+
kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
413
+
emulated = EMULATE_AGAIN;
414
+
break;
415
+
}
416
+
417
+
/* generate interrupt based on priorities */
418
+
if (guest_msr & MSR_PR) {
419
+
/* Privileged Instruction type Program Intr */
420
+
kvmppc_core_queue_program(vcpu, SRR1_PROGPRIV);
421
+
emulated = EMULATE_AGAIN;
422
+
break;
423
+
}
424
+
425
+
tm_enable();
426
+
texasr = mfspr(SPRN_TEXASR);
427
+
tm_disable();
428
+
429
+
if (MSR_TM_ACTIVE(guest_msr) ||
430
+
!(texasr & (TEXASR_FS))) {
431
+
/* TM bad thing interrupt */
432
+
kvmppc_core_queue_program(vcpu, SRR1_PROGTM);
433
+
emulated = EMULATE_AGAIN;
434
+
break;
435
+
}
436
+
437
+
kvmppc_emulate_trchkpt(vcpu);
438
+
break;
439
+
}
440
+
#endif
483
441
default:
484
442
emulated = EMULATE_FAIL;
485
443
}
···
775
465
break;
776
466
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
777
467
case SPRN_TFHAR:
778
-
vcpu->arch.tfhar = spr_val;
779
-
break;
780
468
case SPRN_TEXASR:
781
-
vcpu->arch.texasr = spr_val;
782
-
break;
783
469
case SPRN_TFIAR:
784
-
vcpu->arch.tfiar = spr_val;
470
+
if (!cpu_has_feature(CPU_FTR_TM))
471
+
break;
472
+
473
+
if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
474
+
kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
475
+
emulated = EMULATE_AGAIN;
476
+
break;
477
+
}
478
+
479
+
if (MSR_TM_ACTIVE(kvmppc_get_msr(vcpu)) &&
480
+
!((MSR_TM_SUSPENDED(kvmppc_get_msr(vcpu))) &&
481
+
(sprn == SPRN_TFHAR))) {
482
+
/* it is illegal to mtspr() TM regs in
483
+
* other than non-transactional state, with
484
+
* the exception of TFHAR in suspend state.
485
+
*/
486
+
kvmppc_core_queue_program(vcpu, SRR1_PROGTM);
487
+
emulated = EMULATE_AGAIN;
488
+
break;
489
+
}
490
+
491
+
tm_enable();
492
+
if (sprn == SPRN_TFHAR)
493
+
mtspr(SPRN_TFHAR, spr_val);
494
+
else if (sprn == SPRN_TEXASR)
495
+
mtspr(SPRN_TEXASR, spr_val);
496
+
else
497
+
mtspr(SPRN_TFIAR, spr_val);
498
+
tm_disable();
499
+
785
500
break;
786
501
#endif
787
502
#endif
···
953
618
break;
954
619
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
955
620
case SPRN_TFHAR:
956
-
*spr_val = vcpu->arch.tfhar;
957
-
break;
958
621
case SPRN_TEXASR:
959
-
*spr_val = vcpu->arch.texasr;
960
-
break;
961
622
case SPRN_TFIAR:
962
-
*spr_val = vcpu->arch.tfiar;
623
+
if (!cpu_has_feature(CPU_FTR_TM))
624
+
break;
625
+
626
+
if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
627
+
kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
628
+
emulated = EMULATE_AGAIN;
629
+
break;
630
+
}
631
+
632
+
tm_enable();
633
+
if (sprn == SPRN_TFHAR)
634
+
*spr_val = mfspr(SPRN_TFHAR);
635
+
else if (sprn == SPRN_TEXASR)
636
+
*spr_val = mfspr(SPRN_TEXASR);
637
+
else if (sprn == SPRN_TFIAR)
638
+
*spr_val = mfspr(SPRN_TFIAR);
639
+
tm_disable();
963
640
break;
964
641
#endif
965
642
#endif
+94
-3
arch/powerpc/kvm/book3s_hv.c
+94
-3
arch/powerpc/kvm/book3s_hv.c
···
123
123
static void kvmppc_end_cede(struct kvm_vcpu *vcpu);
124
124
static int kvmppc_hv_setup_htab_rma(struct kvm_vcpu *vcpu);
125
125
126
+
/*
127
+
* RWMR values for POWER8. These control the rate at which PURR
128
+
* and SPURR count and should be set according to the number of
129
+
* online threads in the vcore being run.
130
+
*/
131
+
#define RWMR_RPA_P8_1THREAD 0x164520C62609AECA
132
+
#define RWMR_RPA_P8_2THREAD 0x7FFF2908450D8DA9
133
+
#define RWMR_RPA_P8_3THREAD 0x164520C62609AECA
134
+
#define RWMR_RPA_P8_4THREAD 0x199A421245058DA9
135
+
#define RWMR_RPA_P8_5THREAD 0x164520C62609AECA
136
+
#define RWMR_RPA_P8_6THREAD 0x164520C62609AECA
137
+
#define RWMR_RPA_P8_7THREAD 0x164520C62609AECA
138
+
#define RWMR_RPA_P8_8THREAD 0x164520C62609AECA
139
+
140
+
static unsigned long p8_rwmr_values[MAX_SMT_THREADS + 1] = {
141
+
RWMR_RPA_P8_1THREAD,
142
+
RWMR_RPA_P8_1THREAD,
143
+
RWMR_RPA_P8_2THREAD,
144
+
RWMR_RPA_P8_3THREAD,
145
+
RWMR_RPA_P8_4THREAD,
146
+
RWMR_RPA_P8_5THREAD,
147
+
RWMR_RPA_P8_6THREAD,
148
+
RWMR_RPA_P8_7THREAD,
149
+
RWMR_RPA_P8_8THREAD,
150
+
};
151
+
126
152
static inline struct kvm_vcpu *next_runnable_thread(struct kvmppc_vcore *vc,
127
153
int *ip)
128
154
{
···
397
371
398
372
pr_err("vcpu %p (%d):\n", vcpu, vcpu->vcpu_id);
399
373
pr_err("pc = %.16lx msr = %.16llx trap = %x\n",
400
-
vcpu->arch.pc, vcpu->arch.shregs.msr, vcpu->arch.trap);
374
+
vcpu->arch.regs.nip, vcpu->arch.shregs.msr, vcpu->arch.trap);
401
375
for (r = 0; r < 16; ++r)
402
376
pr_err("r%2d = %.16lx r%d = %.16lx\n",
403
377
r, kvmppc_get_gpr(vcpu, r),
404
378
r+16, kvmppc_get_gpr(vcpu, r+16));
405
379
pr_err("ctr = %.16lx lr = %.16lx\n",
406
-
vcpu->arch.ctr, vcpu->arch.lr);
380
+
vcpu->arch.regs.ctr, vcpu->arch.regs.link);
407
381
pr_err("srr0 = %.16llx srr1 = %.16llx\n",
408
382
vcpu->arch.shregs.srr0, vcpu->arch.shregs.srr1);
409
383
pr_err("sprg0 = %.16llx sprg1 = %.16llx\n",
···
411
385
pr_err("sprg2 = %.16llx sprg3 = %.16llx\n",
412
386
vcpu->arch.shregs.sprg2, vcpu->arch.shregs.sprg3);
413
387
pr_err("cr = %.8x xer = %.16lx dsisr = %.8x\n",
414
-
vcpu->arch.cr, vcpu->arch.xer, vcpu->arch.shregs.dsisr);
388
+
vcpu->arch.cr, vcpu->arch.regs.xer, vcpu->arch.shregs.dsisr);
415
389
pr_err("dar = %.16llx\n", vcpu->arch.shregs.dar);
416
390
pr_err("fault dar = %.16lx dsisr = %.8x\n",
417
391
vcpu->arch.fault_dar, vcpu->arch.fault_dsisr);
···
1552
1526
*val = get_reg_val(id, vcpu->arch.dec_expires +
1553
1527
vcpu->arch.vcore->tb_offset);
1554
1528
break;
1529
+
case KVM_REG_PPC_ONLINE:
1530
+
*val = get_reg_val(id, vcpu->arch.online);
1531
+
break;
1555
1532
default:
1556
1533
r = -EINVAL;
1557
1534
break;
···
1785
1756
case KVM_REG_PPC_DEC_EXPIRY:
1786
1757
vcpu->arch.dec_expires = set_reg_val(id, *val) -
1787
1758
vcpu->arch.vcore->tb_offset;
1759
+
break;
1760
+
case KVM_REG_PPC_ONLINE:
1761
+
i = set_reg_val(id, *val);
1762
+
if (i && !vcpu->arch.online)
1763
+
atomic_inc(&vcpu->arch.vcore->online_count);
1764
+
else if (!i && vcpu->arch.online)
1765
+
atomic_dec(&vcpu->arch.vcore->online_count);
1766
+
vcpu->arch.online = i;
1788
1767
break;
1789
1768
default:
1790
1769
r = -EINVAL;
···
2887
2850
}
2888
2851
}
2889
2852
2853
+
/*
2854
+
* On POWER8, set RWMR register.
2855
+
* Since it only affects PURR and SPURR, it doesn't affect
2856
+
* the host, so we don't save/restore the host value.
2857
+
*/
2858
+
if (is_power8) {
2859
+
unsigned long rwmr_val = RWMR_RPA_P8_8THREAD;
2860
+
int n_online = atomic_read(&vc->online_count);
2861
+
2862
+
/*
2863
+
* Use the 8-thread value if we're doing split-core
2864
+
* or if the vcore's online count looks bogus.
2865
+
*/
2866
+
if (split == 1 && threads_per_subcore == MAX_SMT_THREADS &&
2867
+
n_online >= 1 && n_online <= MAX_SMT_THREADS)
2868
+
rwmr_val = p8_rwmr_values[n_online];
2869
+
mtspr(SPRN_RWMR, rwmr_val);
2870
+
}
2871
+
2890
2872
/* Start all the threads */
2891
2873
active = 0;
2892
2874
for (sub = 0; sub < core_info.n_subcores; ++sub) {
···
2957
2901
2958
2902
for (sub = 0; sub < core_info.n_subcores; ++sub)
2959
2903
spin_unlock(&core_info.vc[sub]->lock);
2904
+
2905
+
if (kvm_is_radix(vc->kvm)) {
2906
+
int tmp = pcpu;
2907
+
2908
+
/*
2909
+
* Do we need to flush the process scoped TLB for the LPAR?
2910
+
*
2911
+
* On POWER9, individual threads can come in here, but the
2912
+
* TLB is shared between the 4 threads in a core, hence
2913
+
* invalidating on one thread invalidates for all.
2914
+
* Thus we make all 4 threads use the same bit here.
2915
+
*
2916
+
* Hash must be flushed in realmode in order to use tlbiel.
2917
+
*/
2918
+
mtspr(SPRN_LPID, vc->kvm->arch.lpid);
2919
+
isync();
2920
+
2921
+
if (cpu_has_feature(CPU_FTR_ARCH_300))
2922
+
tmp &= ~0x3UL;
2923
+
2924
+
if (cpumask_test_cpu(tmp, &vc->kvm->arch.need_tlb_flush)) {
2925
+
radix__local_flush_tlb_lpid_guest(vc->kvm->arch.lpid);
2926
+
/* Clear the bit after the TLB flush */
2927
+
cpumask_clear_cpu(tmp, &vc->kvm->arch.need_tlb_flush);
2928
+
}
2929
+
}
2960
2930
2961
2931
/*
2962
2932
* Interrupts will be enabled once we get into the guest,
···
3437
3355
current->thread.regs->msr &= ~MSR_TM;
3438
3356
}
3439
3357
#endif
3358
+
3359
+
/*
3360
+
* Force online to 1 for the sake of old userspace which doesn't
3361
+
* set it.
3362
+
*/
3363
+
if (!vcpu->arch.online) {
3364
+
atomic_inc(&vcpu->arch.vcore->online_count);
3365
+
vcpu->arch.online = 1;
3366
+
}
3440
3367
3441
3368
kvmppc_core_prepare_to_enter(vcpu);
3442
3369
+17
-4
arch/powerpc/kvm/book3s_hv_builtin.c
+17
-4
arch/powerpc/kvm/book3s_hv_builtin.c
···
18
18
#include <linux/cma.h>
19
19
#include <linux/bitops.h>
20
20
21
+
#include <asm/asm-prototypes.h>
21
22
#include <asm/cputable.h>
22
23
#include <asm/kvm_ppc.h>
23
24
#include <asm/kvm_book3s.h>
···
212
211
213
212
/* Only need to do the expensive mfmsr() on radix */
214
213
if (kvm_is_radix(vcpu->kvm) && (mfmsr() & MSR_IR))
215
-
r = powernv_get_random_long(&vcpu->arch.gpr[4]);
214
+
r = powernv_get_random_long(&vcpu->arch.regs.gpr[4]);
216
215
else
217
-
r = powernv_get_random_real_mode(&vcpu->arch.gpr[4]);
216
+
r = powernv_get_random_real_mode(&vcpu->arch.regs.gpr[4]);
218
217
if (r)
219
218
return H_SUCCESS;
220
219
···
563
562
{
564
563
if (!kvmppc_xics_enabled(vcpu))
565
564
return H_TOO_HARD;
566
-
vcpu->arch.gpr[5] = get_tb();
565
+
vcpu->arch.regs.gpr[5] = get_tb();
567
566
if (xive_enabled()) {
568
567
if (is_rm())
569
568
return xive_rm_h_xirr(vcpu);
···
634
633
635
634
void kvmppc_bad_interrupt(struct pt_regs *regs)
636
635
{
637
-
die("Bad interrupt in KVM entry/exit code", regs, SIGABRT);
636
+
/*
637
+
* 100 could happen at any time, 200 can happen due to invalid real
638
+
* address access for example (or any time due to a hardware problem).
639
+
*/
640
+
if (TRAP(regs) == 0x100) {
641
+
get_paca()->in_nmi++;
642
+
system_reset_exception(regs);
643
+
get_paca()->in_nmi--;
644
+
} else if (TRAP(regs) == 0x200) {
645
+
machine_check_exception(regs);
646
+
} else {
647
+
die("Bad interrupt in KVM entry/exit code", regs, SIGABRT);
648
+
}
638
649
panic("Bad KVM trap");
639
650
}
640
651
+1
-1
arch/powerpc/kvm/book3s_hv_interrupts.S
+1
-1
arch/powerpc/kvm/book3s_hv_interrupts.S
+8
-28
arch/powerpc/kvm/book3s_hv_rm_mmu.c
+8
-28
arch/powerpc/kvm/book3s_hv_rm_mmu.c
···
418
418
long pte_index, unsigned long pteh, unsigned long ptel)
419
419
{
420
420
return kvmppc_do_h_enter(vcpu->kvm, flags, pte_index, pteh, ptel,
421
-
vcpu->arch.pgdir, true, &vcpu->arch.gpr[4]);
421
+
vcpu->arch.pgdir, true,
422
+
&vcpu->arch.regs.gpr[4]);
422
423
}
423
424
424
425
#ifdef __BIG_ENDIAN__
···
435
434
(HPTE_R_KEY_HI | HPTE_R_KEY_LO));
436
435
}
437
436
438
-
static inline int try_lock_tlbie(unsigned int *lock)
439
-
{
440
-
unsigned int tmp, old;
441
-
unsigned int token = LOCK_TOKEN;
442
-
443
-
asm volatile("1:lwarx %1,0,%2\n"
444
-
" cmpwi cr0,%1,0\n"
445
-
" bne 2f\n"
446
-
" stwcx. %3,0,%2\n"
447
-
" bne- 1b\n"
448
-
" isync\n"
449
-
"2:"
450
-
: "=&r" (tmp), "=&r" (old)
451
-
: "r" (lock), "r" (token)
452
-
: "cc", "memory");
453
-
return old == 0;
454
-
}
455
-
456
437
static void do_tlbies(struct kvm *kvm, unsigned long *rbvalues,
457
438
long npages, int global, bool need_sync)
458
439
{
···
446
463
* the RS field, this is backwards-compatible with P7 and P8.
447
464
*/
448
465
if (global) {
449
-
while (!try_lock_tlbie(&kvm->arch.tlbie_lock))
450
-
cpu_relax();
451
466
if (need_sync)
452
467
asm volatile("ptesync" : : : "memory");
453
468
for (i = 0; i < npages; ++i) {
···
464
483
}
465
484
466
485
asm volatile("eieio; tlbsync; ptesync" : : : "memory");
467
-
kvm->arch.tlbie_lock = 0;
468
486
} else {
469
487
if (need_sync)
470
488
asm volatile("ptesync" : : : "memory");
···
541
561
unsigned long pte_index, unsigned long avpn)
542
562
{
543
563
return kvmppc_do_h_remove(vcpu->kvm, flags, pte_index, avpn,
544
-
&vcpu->arch.gpr[4]);
564
+
&vcpu->arch.regs.gpr[4]);
545
565
}
546
566
547
567
long kvmppc_h_bulk_remove(struct kvm_vcpu *vcpu)
548
568
{
549
569
struct kvm *kvm = vcpu->kvm;
550
-
unsigned long *args = &vcpu->arch.gpr[4];
570
+
unsigned long *args = &vcpu->arch.regs.gpr[4];
551
571
__be64 *hp, *hptes[4];
552
572
unsigned long tlbrb[4];
553
573
long int i, j, k, n, found, indexes[4];
···
767
787
r = rev[i].guest_rpte | (r & (HPTE_R_R | HPTE_R_C));
768
788
r &= ~HPTE_GR_RESERVED;
769
789
}
770
-
vcpu->arch.gpr[4 + i * 2] = v;
771
-
vcpu->arch.gpr[5 + i * 2] = r;
790
+
vcpu->arch.regs.gpr[4 + i * 2] = v;
791
+
vcpu->arch.regs.gpr[5 + i * 2] = r;
772
792
}
773
793
return H_SUCCESS;
774
794
}
···
814
834
}
815
835
}
816
836
}
817
-
vcpu->arch.gpr[4] = gr;
837
+
vcpu->arch.regs.gpr[4] = gr;
818
838
ret = H_SUCCESS;
819
839
out:
820
840
unlock_hpte(hpte, v & ~HPTE_V_HVLOCK);
···
861
881
kvmppc_set_dirty_from_hpte(kvm, v, gr);
862
882
}
863
883
}
864
-
vcpu->arch.gpr[4] = gr;
884
+
vcpu->arch.regs.gpr[4] = gr;
865
885
ret = H_SUCCESS;
866
886
out:
867
887
unlock_hpte(hpte, v & ~HPTE_V_HVLOCK);
+1
-1
arch/powerpc/kvm/book3s_hv_rm_xics.c
+1
-1
arch/powerpc/kvm/book3s_hv_rm_xics.c
+84
-248
arch/powerpc/kvm/book3s_hv_rmhandlers.S
+84
-248
arch/powerpc/kvm/book3s_hv_rmhandlers.S
···
39
39
extsw reg, reg; \
40
40
END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
41
41
42
-
#define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
43
-
44
42
/* Values in HSTATE_NAPPING(r13) */
45
43
#define NAPPING_CEDE 1
46
44
#define NAPPING_NOVCPU 2
···
637
639
/* Primary thread switches to guest partition. */
638
640
cmpwi r6,0
639
641
bne 10f
642
+
643
+
/* Radix has already switched LPID and flushed core TLB */
644
+
bne cr7, 22f
645
+
640
646
lwz r7,KVM_LPID(r9)
641
647
BEGIN_FTR_SECTION
642
648
ld r6,KVM_SDR1(r9)
···
652
650
mtspr SPRN_LPID,r7
653
651
isync
654
652
655
-
/* See if we need to flush the TLB */
653
+
/* See if we need to flush the TLB. Hash has to be done in RM */
656
654
lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
657
655
BEGIN_FTR_SECTION
658
656
/*
···
679
677
li r7,0x800 /* IS field = 0b10 */
680
678
ptesync
681
679
li r0,0 /* RS for P9 version of tlbiel */
682
-
bne cr7, 29f
683
680
28: tlbiel r7 /* On P9, rs=0, RIC=0, PRS=0, R=0 */
684
681
addi r7,r7,0x1000
685
682
bdnz 28b
686
-
b 30f
687
-
29: PPC_TLBIEL(7,0,2,1,1) /* for radix, RIC=2, PRS=1, R=1 */
688
-
addi r7,r7,0x1000
689
-
bdnz 29b
690
-
30: ptesync
683
+
ptesync
691
684
23: ldarx r7,0,r6 /* clear the bit after TLB flushed */
692
685
andc r7,r7,r8
693
686
stdcx. r7,0,r6
···
796
799
/*
797
800
* NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
798
801
*/
799
-
bl kvmppc_restore_tm
802
+
mr r3, r4
803
+
ld r4, VCPU_MSR(r3)
804
+
bl kvmppc_restore_tm_hv
805
+
ld r4, HSTATE_KVM_VCPU(r13)
800
806
91:
801
807
#endif
802
808
···
1783
1783
/*
1784
1784
* NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
1785
1785
*/
1786
-
bl kvmppc_save_tm
1786
+
mr r3, r9
1787
+
ld r4, VCPU_MSR(r3)
1788
+
bl kvmppc_save_tm_hv
1789
+
ld r9, HSTATE_KVM_VCPU(r13)
1787
1790
91:
1788
1791
#endif
1789
1792
···
2689
2686
/*
2690
2687
* NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
2691
2688
*/
2692
-
ld r9, HSTATE_KVM_VCPU(r13)
2693
-
bl kvmppc_save_tm
2689
+
ld r3, HSTATE_KVM_VCPU(r13)
2690
+
ld r4, VCPU_MSR(r3)
2691
+
bl kvmppc_save_tm_hv
2694
2692
91:
2695
2693
#endif
2696
2694
···
2809
2805
/*
2810
2806
* NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
2811
2807
*/
2812
-
bl kvmppc_restore_tm
2808
+
mr r3, r4
2809
+
ld r4, VCPU_MSR(r3)
2810
+
bl kvmppc_restore_tm_hv
2811
+
ld r4, HSTATE_KVM_VCPU(r13)
2813
2812
91:
2814
2813
#endif
2815
2814
···
3133
3126
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
3134
3127
/*
3135
3128
* Save transactional state and TM-related registers.
3136
-
* Called with r9 pointing to the vcpu struct.
3129
+
* Called with r3 pointing to the vcpu struct and r4 containing
3130
+
* the guest MSR value.
3137
3131
* This can modify all checkpointed registers, but
3138
-
* restores r1, r2 and r9 (vcpu pointer) before exit.
3132
+
* restores r1 and r2 before exit.
3139
3133
*/
3140
-
kvmppc_save_tm:
3134
+
kvmppc_save_tm_hv:
3135
+
/* See if we need to handle fake suspend mode */
3136
+
BEGIN_FTR_SECTION
3137
+
b __kvmppc_save_tm
3138
+
END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
3139
+
3140
+
lbz r0, HSTATE_FAKE_SUSPEND(r13) /* Were we fake suspended? */
3141
+
cmpwi r0, 0
3142
+
beq __kvmppc_save_tm
3143
+
3144
+
/* The following code handles the fake_suspend = 1 case */
3141
3145
mflr r0
3142
3146
std r0, PPC_LR_STKOFF(r1)
3143
3147
stdu r1, -PPC_MIN_STKFRM(r1)
···
3159
3141
rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
3160
3142
mtmsrd r8
3161
3143
3162
-
ld r5, VCPU_MSR(r9)
3163
-
rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
3164
-
beq 1f /* TM not active in guest. */
3165
-
3166
-
std r1, HSTATE_HOST_R1(r13)
3167
-
li r3, TM_CAUSE_KVM_RESCHED
3168
-
3169
-
BEGIN_FTR_SECTION
3170
-
lbz r0, HSTATE_FAKE_SUSPEND(r13) /* Were we fake suspended? */
3171
-
cmpwi r0, 0
3172
-
beq 3f
3173
3144
rldicl. r8, r8, 64 - MSR_TS_S_LG, 62 /* Did we actually hrfid? */
3174
3145
beq 4f
3175
-
BEGIN_FTR_SECTION_NESTED(96)
3146
+
BEGIN_FTR_SECTION
3176
3147
bl pnv_power9_force_smt4_catch
3177
-
END_FTR_SECTION_NESTED(CPU_FTR_P9_TM_XER_SO_BUG, CPU_FTR_P9_TM_XER_SO_BUG, 96)
3148
+
END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
3178
3149
nop
3179
-
b 6f
3180
-
3:
3181
-
/* Emulation of the treclaim instruction needs TEXASR before treclaim */
3182
-
mfspr r6, SPRN_TEXASR
3183
-
std r6, VCPU_ORIG_TEXASR(r9)
3184
-
6:
3185
-
END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_HV_ASSIST)
3186
3150
3187
-
/* Clear the MSR RI since r1, r13 are all going to be foobar. */
3151
+
std r1, HSTATE_HOST_R1(r13)
3152
+
3153
+
/* Clear the MSR RI since r1, r13 may be foobar. */
3188
3154
li r5, 0
3189
3155
mtmsrd r5, 1
3190
3156
3191
-
/* All GPRs are volatile at this point. */
3157
+
/* We have to treclaim here because that's the only way to do S->N */
3158
+
li r3, TM_CAUSE_KVM_RESCHED
3192
3159
TRECLAIM(R3)
3193
3160
3194
-
/* Temporarily store r13 and r9 so we have some regs to play with */
3195
-
SET_SCRATCH0(r13)
3196
-
GET_PACA(r13)
3197
-
std r9, PACATMSCRATCH(r13)
3198
-
3199
-
/* If doing TM emulation on POWER9 DD2.2, check for fake suspend mode */
3200
-
BEGIN_FTR_SECTION
3201
-
lbz r9, HSTATE_FAKE_SUSPEND(r13)
3202
-
cmpwi r9, 0
3203
-
beq 2f
3204
3161
/*
3205
3162
* We were in fake suspend, so we are not going to save the
3206
3163
* register state as the guest checkpointed state (since
3207
3164
* we already have it), therefore we can now use any volatile GPR.
3208
3165
*/
3209
-
/* Reload stack pointer and TOC. */
3166
+
/* Reload PACA pointer, stack pointer and TOC. */
3167
+
GET_PACA(r13)
3210
3168
ld r1, HSTATE_HOST_R1(r13)
3211
3169
ld r2, PACATOC(r13)
3170
+
3212
3171
/* Set MSR RI now we have r1 and r13 back. */
3213
3172
li r5, MSR_RI
3214
3173
mtmsrd r5, 1
3174
+
3215
3175
HMT_MEDIUM
3216
3176
ld r6, HSTATE_DSCR(r13)
3217
3177
mtspr SPRN_DSCR, r6
···
3204
3208
li r0, PSSCR_FAKE_SUSPEND
3205
3209
andc r3, r3, r0
3206
3210
mtspr SPRN_PSSCR, r3
3207
-
ld r9, HSTATE_KVM_VCPU(r13)
3211
+
3208
3212
/* Don't save TEXASR, use value from last exit in real suspend state */
3209
-
b 11f
3210
-
2:
3211
-
END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_HV_ASSIST)
3212
-
3213
3213
ld r9, HSTATE_KVM_VCPU(r13)
3214
-
3215
-
/* Get a few more GPRs free. */
3216
-
std r29, VCPU_GPRS_TM(29)(r9)
3217
-
std r30, VCPU_GPRS_TM(30)(r9)
3218
-
std r31, VCPU_GPRS_TM(31)(r9)
3219
-
3220
-
/* Save away PPR and DSCR soon so don't run with user values. */
3221
-
mfspr r31, SPRN_PPR
3222
-
HMT_MEDIUM
3223
-
mfspr r30, SPRN_DSCR
3224
-
ld r29, HSTATE_DSCR(r13)
3225
-
mtspr SPRN_DSCR, r29
3226
-
3227
-
/* Save all but r9, r13 & r29-r31 */
3228
-
reg = 0
3229
-
.rept 29
3230
-
.if (reg != 9) && (reg != 13)
3231
-
std reg, VCPU_GPRS_TM(reg)(r9)
3232
-
.endif
3233
-
reg = reg + 1
3234
-
.endr
3235
-
/* ... now save r13 */
3236
-
GET_SCRATCH0(r4)
3237
-
std r4, VCPU_GPRS_TM(13)(r9)
3238
-
/* ... and save r9 */
3239
-
ld r4, PACATMSCRATCH(r13)
3240
-
std r4, VCPU_GPRS_TM(9)(r9)
3241
-
3242
-
/* Reload stack pointer and TOC. */
3243
-
ld r1, HSTATE_HOST_R1(r13)
3244
-
ld r2, PACATOC(r13)
3245
-
3246
-
/* Set MSR RI now we have r1 and r13 back. */
3247
-
li r5, MSR_RI
3248
-
mtmsrd r5, 1
3249
-
3250
-
/* Save away checkpinted SPRs. */
3251
-
std r31, VCPU_PPR_TM(r9)
3252
-
std r30, VCPU_DSCR_TM(r9)
3253
-
mflr r5
3254
-
mfcr r6
3255
-
mfctr r7
3256
-
mfspr r8, SPRN_AMR
3257
-
mfspr r10, SPRN_TAR
3258
-
mfxer r11
3259
-
std r5, VCPU_LR_TM(r9)
3260
-
stw r6, VCPU_CR_TM(r9)
3261
-
std r7, VCPU_CTR_TM(r9)
3262
-
std r8, VCPU_AMR_TM(r9)
3263
-
std r10, VCPU_TAR_TM(r9)
3264
-
std r11, VCPU_XER_TM(r9)
3265
-
3266
-
/* Restore r12 as trap number. */
3267
-
lwz r12, VCPU_TRAP(r9)
3268
-
3269
-
/* Save FP/VSX. */
3270
-
addi r3, r9, VCPU_FPRS_TM
3271
-
bl store_fp_state
3272
-
addi r3, r9, VCPU_VRS_TM
3273
-
bl store_vr_state
3274
-
mfspr r6, SPRN_VRSAVE
3275
-
stw r6, VCPU_VRSAVE_TM(r9)
3276
-
1:
3277
-
/*
3278
-
* We need to save these SPRs after the treclaim so that the software
3279
-
* error code is recorded correctly in the TEXASR. Also the user may
3280
-
* change these outside of a transaction, so they must always be
3281
-
* context switched.
3282
-
*/
3283
-
mfspr r7, SPRN_TEXASR
3284
-
std r7, VCPU_TEXASR(r9)
3285
-
11:
3286
3214
mfspr r5, SPRN_TFHAR
3287
3215
mfspr r6, SPRN_TFIAR
3288
3216
std r5, VCPU_TFHAR(r9)
···
3219
3299
3220
3300
/*
3221
3301
* Restore transactional state and TM-related registers.
3222
-
* Called with r4 pointing to the vcpu struct.
3302
+
* Called with r3 pointing to the vcpu struct
3303
+
* and r4 containing the guest MSR value.
3223
3304
* This potentially modifies all checkpointed registers.
3224
-
* It restores r1, r2, r4 from the PACA.
3305
+
* It restores r1 and r2 from the PACA.
3225
3306
*/
3226
-
kvmppc_restore_tm:
3227
-
mflr r0
3228
-
std r0, PPC_LR_STKOFF(r1)
3229
-
3230
-
/* Turn on TM/FP/VSX/VMX so we can restore them. */
3231
-
mfmsr r5
3232
-
li r6, MSR_TM >> 32
3233
-
sldi r6, r6, 32
3234
-
or r5, r5, r6
3235
-
ori r5, r5, MSR_FP
3236
-
oris r5, r5, (MSR_VEC | MSR_VSX)@h
3237
-
mtmsrd r5
3238
-
3239
-
/*
3240
-
* The user may change these outside of a transaction, so they must
3241
-
* always be context switched.
3242
-
*/
3243
-
ld r5, VCPU_TFHAR(r4)
3244
-
ld r6, VCPU_TFIAR(r4)
3245
-
ld r7, VCPU_TEXASR(r4)
3246
-
mtspr SPRN_TFHAR, r5
3247
-
mtspr SPRN_TFIAR, r6
3248
-
mtspr SPRN_TEXASR, r7
3249
-
3250
-
li r0, 0
3251
-
stb r0, HSTATE_FAKE_SUSPEND(r13)
3252
-
ld r5, VCPU_MSR(r4)
3253
-
rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
3254
-
beqlr /* TM not active in guest */
3255
-
std r1, HSTATE_HOST_R1(r13)
3256
-
3257
-
/* Make sure the failure summary is set, otherwise we'll program check
3258
-
* when we trechkpt. It's possible that this might have been not set
3259
-
* on a kvmppc_set_one_reg() call but we shouldn't let this crash the
3260
-
* host.
3261
-
*/
3262
-
oris r7, r7, (TEXASR_FS)@h
3263
-
mtspr SPRN_TEXASR, r7
3264
-
3307
+
kvmppc_restore_tm_hv:
3265
3308
/*
3266
3309
* If we are doing TM emulation for the guest on a POWER9 DD2,
3267
3310
* then we don't actually do a trechkpt -- we either set up
3268
3311
* fake-suspend mode, or emulate a TM rollback.
3269
3312
*/
3270
3313
BEGIN_FTR_SECTION
3271
-
b .Ldo_tm_fake_load
3272
-
END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_HV_ASSIST)
3314
+
b __kvmppc_restore_tm
3315
+
END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
3316
+
mflr r0
3317
+
std r0, PPC_LR_STKOFF(r1)
3318
+
3319
+
li r0, 0
3320
+
stb r0, HSTATE_FAKE_SUSPEND(r13)
3321
+
3322
+
/* Turn on TM so we can restore TM SPRs */
3323
+
mfmsr r5
3324
+
li r0, 1
3325
+
rldimi r5, r0, MSR_TM_LG, 63-MSR_TM_LG
3326
+
mtmsrd r5
3273
3327
3274
3328
/*
3275
-
* We need to load up the checkpointed state for the guest.
3276
-
* We need to do this early as it will blow away any GPRs, VSRs and
3277
-
* some SPRs.
3329
+
* The user may change these outside of a transaction, so they must
3330
+
* always be context switched.
3278
3331
*/
3332
+
ld r5, VCPU_TFHAR(r3)
3333
+
ld r6, VCPU_TFIAR(r3)
3334
+
ld r7, VCPU_TEXASR(r3)
3335
+
mtspr SPRN_TFHAR, r5
3336
+
mtspr SPRN_TFIAR, r6
3337
+
mtspr SPRN_TEXASR, r7
3279
3338
3280
-
mr r31, r4
3281
-
addi r3, r31, VCPU_FPRS_TM
3282
-
bl load_fp_state
3283
-
addi r3, r31, VCPU_VRS_TM
3284
-
bl load_vr_state
3285
-
mr r4, r31
3286
-
lwz r7, VCPU_VRSAVE_TM(r4)
3287
-
mtspr SPRN_VRSAVE, r7
3339
+
rldicl. r5, r4, 64 - MSR_TS_S_LG, 62
3340
+
beqlr /* TM not active in guest */
3288
3341
3289
-
ld r5, VCPU_LR_TM(r4)
3290
-
lwz r6, VCPU_CR_TM(r4)
3291
-
ld r7, VCPU_CTR_TM(r4)
3292
-
ld r8, VCPU_AMR_TM(r4)
3293
-
ld r9, VCPU_TAR_TM(r4)
3294
-
ld r10, VCPU_XER_TM(r4)
3295
-
mtlr r5
3296
-
mtcr r6
3297
-
mtctr r7
3298
-
mtspr SPRN_AMR, r8
3299
-
mtspr SPRN_TAR, r9
3300
-
mtxer r10
3342
+
/* Make sure the failure summary is set */
3343
+
oris r7, r7, (TEXASR_FS)@h
3344
+
mtspr SPRN_TEXASR, r7
3301
3345
3302
-
/*
3303
-
* Load up PPR and DSCR values but don't put them in the actual SPRs
3304
-
* till the last moment to avoid running with userspace PPR and DSCR for
3305
-
* too long.
3306
-
*/
3307
-
ld r29, VCPU_DSCR_TM(r4)
3308
-
ld r30, VCPU_PPR_TM(r4)
3309
-
3310
-
std r2, PACATMSCRATCH(r13) /* Save TOC */
3311
-
3312
-
/* Clear the MSR RI since r1, r13 are all going to be foobar. */
3313
-
li r5, 0
3314
-
mtmsrd r5, 1
3315
-
3316
-
/* Load GPRs r0-r28 */
3317
-
reg = 0
3318
-
.rept 29
3319
-
ld reg, VCPU_GPRS_TM(reg)(r31)
3320
-
reg = reg + 1
3321
-
.endr
3322
-
3323
-
mtspr SPRN_DSCR, r29
3324
-
mtspr SPRN_PPR, r30
3325
-
3326
-
/* Load final GPRs */
3327
-
ld 29, VCPU_GPRS_TM(29)(r31)
3328
-
ld 30, VCPU_GPRS_TM(30)(r31)
3329
-
ld 31, VCPU_GPRS_TM(31)(r31)
3330
-
3331
-
/* TM checkpointed state is now setup. All GPRs are now volatile. */
3332
-
TRECHKPT
3333
-
3334
-
/* Now let's get back the state we need. */
3335
-
HMT_MEDIUM
3336
-
GET_PACA(r13)
3337
-
ld r29, HSTATE_DSCR(r13)
3338
-
mtspr SPRN_DSCR, r29
3339
-
ld r4, HSTATE_KVM_VCPU(r13)
3340
-
ld r1, HSTATE_HOST_R1(r13)
3341
-
ld r2, PACATMSCRATCH(r13)
3342
-
3343
-
/* Set the MSR RI since we have our registers back. */
3344
-
li r5, MSR_RI
3345
-
mtmsrd r5, 1
3346
-
9:
3347
-
ld r0, PPC_LR_STKOFF(r1)
3348
-
mtlr r0
3349
-
blr
3350
-
3351
-
.Ldo_tm_fake_load:
3352
3346
cmpwi r5, 1 /* check for suspended state */
3353
3347
bgt 10f
3354
3348
stb r5, HSTATE_FAKE_SUSPEND(r13)
3355
-
b 9b /* and return */
3349
+
b 9f /* and return */
3356
3350
10: stdu r1, -PPC_MIN_STKFRM(r1)
3357
3351
/* guest is in transactional state, so simulate rollback */
3358
-
mr r3, r4
3359
3352
bl kvmhv_emulate_tm_rollback
3360
3353
nop
3361
-
ld r4, HSTATE_KVM_VCPU(r13) /* our vcpu pointer has been trashed */
3362
3354
addi r1, r1, PPC_MIN_STKFRM
3363
-
b 9b
3364
-
#endif
3355
+
9: ld r0, PPC_LR_STKOFF(r1)
3356
+
mtlr r0
3357
+
blr
3358
+
#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
3365
3359
3366
3360
/*
3367
3361
* We come here if we get any exception or interrupt while we are
···
3406
3572
bcl 20, 31, .+4
3407
3573
5: mflr r3
3408
3574
addi r3, r3, 9f - 5b
3575
+
li r4, -1
3576
+
rldimi r3, r4, 62, 0 /* ensure 0xc000000000000000 bits are set */
3409
3577
ld r4, PACAKMSR(r13)
3410
3578
mtspr SPRN_SRR0, r3
3411
3579
mtspr SPRN_SRR1, r4
+5
-5
arch/powerpc/kvm/book3s_hv_tm.c
+5
-5
arch/powerpc/kvm/book3s_hv_tm.c
···
19
19
u64 texasr, tfiar;
20
20
u64 msr = vcpu->arch.shregs.msr;
21
21
22
-
tfiar = vcpu->arch.pc & ~0x3ull;
22
+
tfiar = vcpu->arch.regs.nip & ~0x3ull;
23
23
texasr = (failure_cause << 56) | TEXASR_ABORT | TEXASR_FS | TEXASR_EXACT;
24
24
if (MSR_TM_SUSPENDED(vcpu->arch.shregs.msr))
25
25
texasr |= TEXASR_SUSP;
···
57
57
(newmsr & MSR_TM)));
58
58
newmsr = sanitize_msr(newmsr);
59
59
vcpu->arch.shregs.msr = newmsr;
60
-
vcpu->arch.cfar = vcpu->arch.pc - 4;
61
-
vcpu->arch.pc = vcpu->arch.shregs.srr0;
60
+
vcpu->arch.cfar = vcpu->arch.regs.nip - 4;
61
+
vcpu->arch.regs.nip = vcpu->arch.shregs.srr0;
62
62
return RESUME_GUEST;
63
63
64
64
case PPC_INST_RFEBB:
···
90
90
vcpu->arch.bescr = bescr;
91
91
msr = (msr & ~MSR_TS_MASK) | MSR_TS_T;
92
92
vcpu->arch.shregs.msr = msr;
93
-
vcpu->arch.cfar = vcpu->arch.pc - 4;
94
-
vcpu->arch.pc = vcpu->arch.ebbrr;
93
+
vcpu->arch.cfar = vcpu->arch.regs.nip - 4;
94
+
vcpu->arch.regs.nip = vcpu->arch.ebbrr;
95
95
return RESUME_GUEST;
96
96
97
97
case PPC_INST_MTMSRD:
+5
-5
arch/powerpc/kvm/book3s_hv_tm_builtin.c
+5
-5
arch/powerpc/kvm/book3s_hv_tm_builtin.c
···
35
35
return 0;
36
36
newmsr = sanitize_msr(newmsr);
37
37
vcpu->arch.shregs.msr = newmsr;
38
-
vcpu->arch.cfar = vcpu->arch.pc - 4;
39
-
vcpu->arch.pc = vcpu->arch.shregs.srr0;
38
+
vcpu->arch.cfar = vcpu->arch.regs.nip - 4;
39
+
vcpu->arch.regs.nip = vcpu->arch.shregs.srr0;
40
40
return 1;
41
41
42
42
case PPC_INST_RFEBB:
···
58
58
mtspr(SPRN_BESCR, bescr);
59
59
msr = (msr & ~MSR_TS_MASK) | MSR_TS_T;
60
60
vcpu->arch.shregs.msr = msr;
61
-
vcpu->arch.cfar = vcpu->arch.pc - 4;
62
-
vcpu->arch.pc = mfspr(SPRN_EBBRR);
61
+
vcpu->arch.cfar = vcpu->arch.regs.nip - 4;
62
+
vcpu->arch.regs.nip = mfspr(SPRN_EBBRR);
63
63
return 1;
64
64
65
65
case PPC_INST_MTMSRD:
···
103
103
void kvmhv_emulate_tm_rollback(struct kvm_vcpu *vcpu)
104
104
{
105
105
vcpu->arch.shregs.msr &= ~MSR_TS_MASK; /* go to N state */
106
-
vcpu->arch.pc = vcpu->arch.tfhar;
106
+
vcpu->arch.regs.nip = vcpu->arch.tfhar;
107
107
copy_from_checkpoint(vcpu);
108
108
vcpu->arch.cr = (vcpu->arch.cr & 0x0fffffff) | 0xa0000000;
109
109
}
+395
-87
arch/powerpc/kvm/book3s_pr.c
+395
-87
arch/powerpc/kvm/book3s_pr.c
···
42
42
#include <linux/highmem.h>
43
43
#include <linux/module.h>
44
44
#include <linux/miscdevice.h>
45
+
#include <asm/asm-prototypes.h>
46
+
#include <asm/tm.h>
45
47
46
48
#include "book3s.h"
47
49
···
55
53
56
54
static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr,
57
55
ulong msr);
58
-
static void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac);
56
+
#ifdef CONFIG_PPC_BOOK3S_64
57
+
static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac);
58
+
#endif
59
59
60
60
/* Some compatibility defines */
61
61
#ifdef CONFIG_PPC_BOOK3S_32
···
118
114
119
115
if (kvmppc_is_split_real(vcpu))
120
116
kvmppc_fixup_split_real(vcpu);
117
+
118
+
kvmppc_restore_tm_pr(vcpu);
121
119
}
122
120
123
121
static void kvmppc_core_vcpu_put_pr(struct kvm_vcpu *vcpu)
···
139
133
140
134
kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX);
141
135
kvmppc_giveup_fac(vcpu, FSCR_TAR_LG);
136
+
kvmppc_save_tm_pr(vcpu);
142
137
143
138
/* Enable AIL if supported */
144
139
if (cpu_has_feature(CPU_FTR_HVMODE) &&
···
154
147
{
155
148
struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
156
149
157
-
svcpu->gpr[0] = vcpu->arch.gpr[0];
158
-
svcpu->gpr[1] = vcpu->arch.gpr[1];
159
-
svcpu->gpr[2] = vcpu->arch.gpr[2];
160
-
svcpu->gpr[3] = vcpu->arch.gpr[3];
161
-
svcpu->gpr[4] = vcpu->arch.gpr[4];
162
-
svcpu->gpr[5] = vcpu->arch.gpr[5];
163
-
svcpu->gpr[6] = vcpu->arch.gpr[6];
164
-
svcpu->gpr[7] = vcpu->arch.gpr[7];
165
-
svcpu->gpr[8] = vcpu->arch.gpr[8];
166
-
svcpu->gpr[9] = vcpu->arch.gpr[9];
167
-
svcpu->gpr[10] = vcpu->arch.gpr[10];
168
-
svcpu->gpr[11] = vcpu->arch.gpr[11];
169
-
svcpu->gpr[12] = vcpu->arch.gpr[12];
170
-
svcpu->gpr[13] = vcpu->arch.gpr[13];
150
+
svcpu->gpr[0] = vcpu->arch.regs.gpr[0];
151
+
svcpu->gpr[1] = vcpu->arch.regs.gpr[1];
152
+
svcpu->gpr[2] = vcpu->arch.regs.gpr[2];
153
+
svcpu->gpr[3] = vcpu->arch.regs.gpr[3];
154
+
svcpu->gpr[4] = vcpu->arch.regs.gpr[4];
155
+
svcpu->gpr[5] = vcpu->arch.regs.gpr[5];
156
+
svcpu->gpr[6] = vcpu->arch.regs.gpr[6];
157
+
svcpu->gpr[7] = vcpu->arch.regs.gpr[7];
158
+
svcpu->gpr[8] = vcpu->arch.regs.gpr[8];
159
+
svcpu->gpr[9] = vcpu->arch.regs.gpr[9];
160
+
svcpu->gpr[10] = vcpu->arch.regs.gpr[10];
161
+
svcpu->gpr[11] = vcpu->arch.regs.gpr[11];
162
+
svcpu->gpr[12] = vcpu->arch.regs.gpr[12];
163
+
svcpu->gpr[13] = vcpu->arch.regs.gpr[13];
171
164
svcpu->cr = vcpu->arch.cr;
172
-
svcpu->xer = vcpu->arch.xer;
173
-
svcpu->ctr = vcpu->arch.ctr;
174
-
svcpu->lr = vcpu->arch.lr;
175
-
svcpu->pc = vcpu->arch.pc;
165
+
svcpu->xer = vcpu->arch.regs.xer;
166
+
svcpu->ctr = vcpu->arch.regs.ctr;
167
+
svcpu->lr = vcpu->arch.regs.link;
168
+
svcpu->pc = vcpu->arch.regs.nip;
176
169
#ifdef CONFIG_PPC_BOOK3S_64
177
170
svcpu->shadow_fscr = vcpu->arch.shadow_fscr;
178
171
#endif
···
189
182
svcpu_put(svcpu);
190
183
}
191
184
185
+
static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu)
186
+
{
187
+
ulong guest_msr = kvmppc_get_msr(vcpu);
188
+
ulong smsr = guest_msr;
189
+
190
+
/* Guest MSR values */
191
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
192
+
smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE |
193
+
MSR_TM | MSR_TS_MASK;
194
+
#else
195
+
smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE;
196
+
#endif
197
+
/* Process MSR values */
198
+
smsr |= MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_PR | MSR_EE;
199
+
/* External providers the guest reserved */
200
+
smsr |= (guest_msr & vcpu->arch.guest_owned_ext);
201
+
/* 64-bit Process MSR values */
202
+
#ifdef CONFIG_PPC_BOOK3S_64
203
+
smsr |= MSR_ISF | MSR_HV;
204
+
#endif
205
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
206
+
/*
207
+
* in guest privileged state, we want to fail all TM transactions.
208
+
* So disable MSR TM bit so that all tbegin. will be able to be
209
+
* trapped into host.
210
+
*/
211
+
if (!(guest_msr & MSR_PR))
212
+
smsr &= ~MSR_TM;
213
+
#endif
214
+
vcpu->arch.shadow_msr = smsr;
215
+
}
216
+
192
217
/* Copy data touched by real-mode code from shadow vcpu back to vcpu */
193
218
void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu)
194
219
{
195
220
struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
221
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
222
+
ulong old_msr;
223
+
#endif
196
224
197
225
/*
198
226
* Maybe we were already preempted and synced the svcpu from
···
236
194
if (!svcpu->in_use)
237
195
goto out;
238
196
239
-
vcpu->arch.gpr[0] = svcpu->gpr[0];
240
-
vcpu->arch.gpr[1] = svcpu->gpr[1];
241
-
vcpu->arch.gpr[2] = svcpu->gpr[2];
242
-
vcpu->arch.gpr[3] = svcpu->gpr[3];
243
-
vcpu->arch.gpr[4] = svcpu->gpr[4];
244
-
vcpu->arch.gpr[5] = svcpu->gpr[5];
245
-
vcpu->arch.gpr[6] = svcpu->gpr[6];
246
-
vcpu->arch.gpr[7] = svcpu->gpr[7];
247
-
vcpu->arch.gpr[8] = svcpu->gpr[8];
248
-
vcpu->arch.gpr[9] = svcpu->gpr[9];
249
-
vcpu->arch.gpr[10] = svcpu->gpr[10];
250
-
vcpu->arch.gpr[11] = svcpu->gpr[11];
251
-
vcpu->arch.gpr[12] = svcpu->gpr[12];
252
-
vcpu->arch.gpr[13] = svcpu->gpr[13];
197
+
vcpu->arch.regs.gpr[0] = svcpu->gpr[0];
198
+
vcpu->arch.regs.gpr[1] = svcpu->gpr[1];
199
+
vcpu->arch.regs.gpr[2] = svcpu->gpr[2];
200
+
vcpu->arch.regs.gpr[3] = svcpu->gpr[3];
201
+
vcpu->arch.regs.gpr[4] = svcpu->gpr[4];
202
+
vcpu->arch.regs.gpr[5] = svcpu->gpr[5];
203
+
vcpu->arch.regs.gpr[6] = svcpu->gpr[6];
204
+
vcpu->arch.regs.gpr[7] = svcpu->gpr[7];
205
+
vcpu->arch.regs.gpr[8] = svcpu->gpr[8];
206
+
vcpu->arch.regs.gpr[9] = svcpu->gpr[9];
207
+
vcpu->arch.regs.gpr[10] = svcpu->gpr[10];
208
+
vcpu->arch.regs.gpr[11] = svcpu->gpr[11];
209
+
vcpu->arch.regs.gpr[12] = svcpu->gpr[12];
210
+
vcpu->arch.regs.gpr[13] = svcpu->gpr[13];
253
211
vcpu->arch.cr = svcpu->cr;
254
-
vcpu->arch.xer = svcpu->xer;
255
-
vcpu->arch.ctr = svcpu->ctr;
256
-
vcpu->arch.lr = svcpu->lr;
257
-
vcpu->arch.pc = svcpu->pc;
212
+
vcpu->arch.regs.xer = svcpu->xer;
213
+
vcpu->arch.regs.ctr = svcpu->ctr;
214
+
vcpu->arch.regs.link = svcpu->lr;
215
+
vcpu->arch.regs.nip = svcpu->pc;
258
216
vcpu->arch.shadow_srr1 = svcpu->shadow_srr1;
259
217
vcpu->arch.fault_dar = svcpu->fault_dar;
260
218
vcpu->arch.fault_dsisr = svcpu->fault_dsisr;
···
270
228
to_book3s(vcpu)->vtb += get_vtb() - vcpu->arch.entry_vtb;
271
229
if (cpu_has_feature(CPU_FTR_ARCH_207S))
272
230
vcpu->arch.ic += mfspr(SPRN_IC) - vcpu->arch.entry_ic;
231
+
232
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
233
+
/*
234
+
* Unlike other MSR bits, MSR[TS]bits can be changed at guest without
235
+
* notifying host:
236
+
* modified by unprivileged instructions like "tbegin"/"tend"/
237
+
* "tresume"/"tsuspend" in PR KVM guest.
238
+
*
239
+
* It is necessary to sync here to calculate a correct shadow_msr.
240
+
*
241
+
* privileged guest's tbegin will be failed at present. So we
242
+
* only take care of problem state guest.
243
+
*/
244
+
old_msr = kvmppc_get_msr(vcpu);
245
+
if (unlikely((old_msr & MSR_PR) &&
246
+
(vcpu->arch.shadow_srr1 & (MSR_TS_MASK)) !=
247
+
(old_msr & (MSR_TS_MASK)))) {
248
+
old_msr &= ~(MSR_TS_MASK);
249
+
old_msr |= (vcpu->arch.shadow_srr1 & (MSR_TS_MASK));
250
+
kvmppc_set_msr_fast(vcpu, old_msr);
251
+
kvmppc_recalc_shadow_msr(vcpu);
252
+
}
253
+
#endif
254
+
273
255
svcpu->in_use = false;
274
256
275
257
out:
276
258
svcpu_put(svcpu);
277
259
}
260
+
261
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
262
+
void kvmppc_save_tm_sprs(struct kvm_vcpu *vcpu)
263
+
{
264
+
tm_enable();
265
+
vcpu->arch.tfhar = mfspr(SPRN_TFHAR);
266
+
vcpu->arch.texasr = mfspr(SPRN_TEXASR);
267
+
vcpu->arch.tfiar = mfspr(SPRN_TFIAR);
268
+
tm_disable();
269
+
}
270
+
271
+
void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu)
272
+
{
273
+
tm_enable();
274
+
mtspr(SPRN_TFHAR, vcpu->arch.tfhar);
275
+
mtspr(SPRN_TEXASR, vcpu->arch.texasr);
276
+
mtspr(SPRN_TFIAR, vcpu->arch.tfiar);
277
+
tm_disable();
278
+
}
279
+
280
+
/* loadup math bits which is enabled at kvmppc_get_msr() but not enabled at
281
+
* hardware.
282
+
*/
283
+
static void kvmppc_handle_lost_math_exts(struct kvm_vcpu *vcpu)
284
+
{
285
+
ulong exit_nr;
286
+
ulong ext_diff = (kvmppc_get_msr(vcpu) & ~vcpu->arch.guest_owned_ext) &
287
+
(MSR_FP | MSR_VEC | MSR_VSX);
288
+
289
+
if (!ext_diff)
290
+
return;
291
+
292
+
if (ext_diff == MSR_FP)
293
+
exit_nr = BOOK3S_INTERRUPT_FP_UNAVAIL;
294
+
else if (ext_diff == MSR_VEC)
295
+
exit_nr = BOOK3S_INTERRUPT_ALTIVEC;
296
+
else
297
+
exit_nr = BOOK3S_INTERRUPT_VSX;
298
+
299
+
kvmppc_handle_ext(vcpu, exit_nr, ext_diff);
300
+
}
301
+
302
+
void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu)
303
+
{
304
+
if (!(MSR_TM_ACTIVE(kvmppc_get_msr(vcpu)))) {
305
+
kvmppc_save_tm_sprs(vcpu);
306
+
return;
307
+
}
308
+
309
+
kvmppc_giveup_fac(vcpu, FSCR_TAR_LG);
310
+
kvmppc_giveup_ext(vcpu, MSR_VSX);
311
+
312
+
preempt_disable();
313
+
_kvmppc_save_tm_pr(vcpu, mfmsr());
314
+
preempt_enable();
315
+
}
316
+
317
+
void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu)
318
+
{
319
+
if (!MSR_TM_ACTIVE(kvmppc_get_msr(vcpu))) {
320
+
kvmppc_restore_tm_sprs(vcpu);
321
+
if (kvmppc_get_msr(vcpu) & MSR_TM) {
322
+
kvmppc_handle_lost_math_exts(vcpu);
323
+
if (vcpu->arch.fscr & FSCR_TAR)
324
+
kvmppc_handle_fac(vcpu, FSCR_TAR_LG);
325
+
}
326
+
return;
327
+
}
328
+
329
+
preempt_disable();
330
+
_kvmppc_restore_tm_pr(vcpu, kvmppc_get_msr(vcpu));
331
+
preempt_enable();
332
+
333
+
if (kvmppc_get_msr(vcpu) & MSR_TM) {
334
+
kvmppc_handle_lost_math_exts(vcpu);
335
+
if (vcpu->arch.fscr & FSCR_TAR)
336
+
kvmppc_handle_fac(vcpu, FSCR_TAR_LG);
337
+
}
338
+
}
339
+
#endif
278
340
279
341
static int kvmppc_core_check_requests_pr(struct kvm_vcpu *vcpu)
280
342
{
···
452
306
453
307
/*****************************************/
454
308
455
-
static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu)
456
-
{
457
-
ulong guest_msr = kvmppc_get_msr(vcpu);
458
-
ulong smsr = guest_msr;
459
-
460
-
/* Guest MSR values */
461
-
smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE;
462
-
/* Process MSR values */
463
-
smsr |= MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_PR | MSR_EE;
464
-
/* External providers the guest reserved */
465
-
smsr |= (guest_msr & vcpu->arch.guest_owned_ext);
466
-
/* 64-bit Process MSR values */
467
-
#ifdef CONFIG_PPC_BOOK3S_64
468
-
smsr |= MSR_ISF | MSR_HV;
469
-
#endif
470
-
vcpu->arch.shadow_msr = smsr;
471
-
}
472
-
473
309
static void kvmppc_set_msr_pr(struct kvm_vcpu *vcpu, u64 msr)
474
310
{
475
-
ulong old_msr = kvmppc_get_msr(vcpu);
311
+
ulong old_msr;
312
+
313
+
/* For PAPR guest, make sure MSR reflects guest mode */
314
+
if (vcpu->arch.papr_enabled)
315
+
msr = (msr & ~MSR_HV) | MSR_ME;
476
316
477
317
#ifdef EXIT_DEBUG
478
318
printk(KERN_INFO "KVM: Set MSR to 0x%llx\n", msr);
479
319
#endif
480
320
321
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
322
+
/* We should never target guest MSR to TS=10 && PR=0,
323
+
* since we always fail transaction for guest privilege
324
+
* state.
325
+
*/
326
+
if (!(msr & MSR_PR) && MSR_TM_TRANSACTIONAL(msr))
327
+
kvmppc_emulate_tabort(vcpu,
328
+
TM_CAUSE_KVM_FAC_UNAV | TM_CAUSE_PERSISTENT);
329
+
#endif
330
+
331
+
old_msr = kvmppc_get_msr(vcpu);
481
332
msr &= to_book3s(vcpu)->msr_mask;
482
333
kvmppc_set_msr_fast(vcpu, msr);
483
334
kvmppc_recalc_shadow_msr(vcpu);
···
530
387
/* Preload FPU if it's enabled */
531
388
if (kvmppc_get_msr(vcpu) & MSR_FP)
532
389
kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP);
390
+
391
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
392
+
if (kvmppc_get_msr(vcpu) & MSR_TM)
393
+
kvmppc_handle_lost_math_exts(vcpu);
394
+
#endif
533
395
}
534
396
535
397
void kvmppc_set_pvr_pr(struct kvm_vcpu *vcpu, u32 pvr)
···
732
584
pte.may_execute = !data;
733
585
}
734
586
735
-
if (page_found == -ENOENT) {
736
-
/* Page not found in guest PTE entries */
737
-
u64 ssrr1 = vcpu->arch.shadow_srr1;
738
-
u64 msr = kvmppc_get_msr(vcpu);
739
-
kvmppc_set_dar(vcpu, kvmppc_get_fault_dar(vcpu));
740
-
kvmppc_set_dsisr(vcpu, vcpu->arch.fault_dsisr);
741
-
kvmppc_set_msr_fast(vcpu, msr | (ssrr1 & 0xf8000000ULL));
742
-
kvmppc_book3s_queue_irqprio(vcpu, vec);
743
-
} else if (page_found == -EPERM) {
744
-
/* Storage protection */
745
-
u32 dsisr = vcpu->arch.fault_dsisr;
746
-
u64 ssrr1 = vcpu->arch.shadow_srr1;
747
-
u64 msr = kvmppc_get_msr(vcpu);
748
-
kvmppc_set_dar(vcpu, kvmppc_get_fault_dar(vcpu));
749
-
dsisr = (dsisr & ~DSISR_NOHPTE) | DSISR_PROTFAULT;
750
-
kvmppc_set_dsisr(vcpu, dsisr);
751
-
kvmppc_set_msr_fast(vcpu, msr | (ssrr1 & 0xf8000000ULL));
752
-
kvmppc_book3s_queue_irqprio(vcpu, vec);
587
+
if (page_found == -ENOENT || page_found == -EPERM) {
588
+
/* Page not found in guest PTE entries, or protection fault */
589
+
u64 flags;
590
+
591
+
if (page_found == -EPERM)
592
+
flags = DSISR_PROTFAULT;
593
+
else
594
+
flags = DSISR_NOHPTE;
595
+
if (data) {
596
+
flags |= vcpu->arch.fault_dsisr & DSISR_ISSTORE;
597
+
kvmppc_core_queue_data_storage(vcpu, eaddr, flags);
598
+
} else {
599
+
kvmppc_core_queue_inst_storage(vcpu, flags);
600
+
}
753
601
} else if (page_found == -EINVAL) {
754
602
/* Page not found in guest SLB */
755
603
kvmppc_set_dar(vcpu, kvmppc_get_fault_dar(vcpu));
···
827
683
}
828
684
829
685
/* Give up facility (TAR / EBB / DSCR) */
830
-
static void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac)
686
+
void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac)
831
687
{
832
688
#ifdef CONFIG_PPC_BOOK3S_64
833
689
if (!(vcpu->arch.shadow_fscr & (1ULL << fac))) {
···
946
802
947
803
#ifdef CONFIG_PPC_BOOK3S_64
948
804
949
-
static void kvmppc_trigger_fac_interrupt(struct kvm_vcpu *vcpu, ulong fac)
805
+
void kvmppc_trigger_fac_interrupt(struct kvm_vcpu *vcpu, ulong fac)
950
806
{
951
807
/* Inject the Interrupt Cause field and trigger a guest interrupt */
952
808
vcpu->arch.fscr &= ~(0xffULL << 56);
···
1008
864
break;
1009
865
}
1010
866
867
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
868
+
/* Since we disabled MSR_TM at privilege state, the mfspr instruction
869
+
* for TM spr can trigger TM fac unavailable. In this case, the
870
+
* emulation is handled by kvmppc_emulate_fac(), which invokes
871
+
* kvmppc_emulate_mfspr() finally. But note the mfspr can include
872
+
* RT for NV registers. So it need to restore those NV reg to reflect
873
+
* the update.
874
+
*/
875
+
if ((fac == FSCR_TM_LG) && !(kvmppc_get_msr(vcpu) & MSR_PR))
876
+
return RESUME_GUEST_NV;
877
+
#endif
878
+
1011
879
return RESUME_GUEST;
1012
880
}
1013
881
···
1028
872
if ((vcpu->arch.fscr & FSCR_TAR) && !(fscr & FSCR_TAR)) {
1029
873
/* TAR got dropped, drop it in shadow too */
1030
874
kvmppc_giveup_fac(vcpu, FSCR_TAR_LG);
875
+
} else if (!(vcpu->arch.fscr & FSCR_TAR) && (fscr & FSCR_TAR)) {
876
+
vcpu->arch.fscr = fscr;
877
+
kvmppc_handle_fac(vcpu, FSCR_TAR_LG);
878
+
return;
1031
879
}
880
+
1032
881
vcpu->arch.fscr = fscr;
1033
882
}
1034
883
#endif
···
1178
1017
kvmppc_mmu_pte_flush(vcpu, kvmppc_get_pc(vcpu), ~0xFFFUL);
1179
1018
r = RESUME_GUEST;
1180
1019
} else {
1181
-
u64 msr = kvmppc_get_msr(vcpu);
1182
-
msr |= shadow_srr1 & 0x58000000;
1183
-
kvmppc_set_msr_fast(vcpu, msr);
1184
-
kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
1020
+
kvmppc_core_queue_inst_storage(vcpu,
1021
+
shadow_srr1 & 0x58000000);
1185
1022
r = RESUME_GUEST;
1186
1023
}
1187
1024
break;
···
1218
1059
r = kvmppc_handle_pagefault(run, vcpu, dar, exit_nr);
1219
1060
srcu_read_unlock(&vcpu->kvm->srcu, idx);
1220
1061
} else {
1221
-
kvmppc_set_dar(vcpu, dar);
1222
-
kvmppc_set_dsisr(vcpu, fault_dsisr);
1223
-
kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
1062
+
kvmppc_core_queue_data_storage(vcpu, dar, fault_dsisr);
1224
1063
r = RESUME_GUEST;
1225
1064
}
1226
1065
break;
···
1249
1092
case BOOK3S_INTERRUPT_EXTERNAL:
1250
1093
case BOOK3S_INTERRUPT_EXTERNAL_LEVEL:
1251
1094
case BOOK3S_INTERRUPT_EXTERNAL_HV:
1095
+
case BOOK3S_INTERRUPT_H_VIRT:
1252
1096
vcpu->stat.ext_intr_exits++;
1253
1097
r = RESUME_GUEST;
1254
1098
break;
1099
+
case BOOK3S_INTERRUPT_HMI:
1255
1100
case BOOK3S_INTERRUPT_PERFMON:
1101
+
case BOOK3S_INTERRUPT_SYSTEM_RESET:
1256
1102
r = RESUME_GUEST;
1257
1103
break;
1258
1104
case BOOK3S_INTERRUPT_PROGRAM:
···
1385
1225
}
1386
1226
#ifdef CONFIG_PPC_BOOK3S_64
1387
1227
case BOOK3S_INTERRUPT_FAC_UNAVAIL:
1388
-
kvmppc_handle_fac(vcpu, vcpu->arch.shadow_fscr >> 56);
1389
-
r = RESUME_GUEST;
1228
+
r = kvmppc_handle_fac(vcpu, vcpu->arch.shadow_fscr >> 56);
1390
1229
break;
1391
1230
#endif
1392
1231
case BOOK3S_INTERRUPT_MACHINE_CHECK:
···
1538
1379
else
1539
1380
*val = get_reg_val(id, 0);
1540
1381
break;
1382
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1383
+
case KVM_REG_PPC_TFHAR:
1384
+
*val = get_reg_val(id, vcpu->arch.tfhar);
1385
+
break;
1386
+
case KVM_REG_PPC_TFIAR:
1387
+
*val = get_reg_val(id, vcpu->arch.tfiar);
1388
+
break;
1389
+
case KVM_REG_PPC_TEXASR:
1390
+
*val = get_reg_val(id, vcpu->arch.texasr);
1391
+
break;
1392
+
case KVM_REG_PPC_TM_GPR0 ... KVM_REG_PPC_TM_GPR31:
1393
+
*val = get_reg_val(id,
1394
+
vcpu->arch.gpr_tm[id-KVM_REG_PPC_TM_GPR0]);
1395
+
break;
1396
+
case KVM_REG_PPC_TM_VSR0 ... KVM_REG_PPC_TM_VSR63:
1397
+
{
1398
+
int i, j;
1399
+
1400
+
i = id - KVM_REG_PPC_TM_VSR0;
1401
+
if (i < 32)
1402
+
for (j = 0; j < TS_FPRWIDTH; j++)
1403
+
val->vsxval[j] = vcpu->arch.fp_tm.fpr[i][j];
1404
+
else {
1405
+
if (cpu_has_feature(CPU_FTR_ALTIVEC))
1406
+
val->vval = vcpu->arch.vr_tm.vr[i-32];
1407
+
else
1408
+
r = -ENXIO;
1409
+
}
1410
+
break;
1411
+
}
1412
+
case KVM_REG_PPC_TM_CR:
1413
+
*val = get_reg_val(id, vcpu->arch.cr_tm);
1414
+
break;
1415
+
case KVM_REG_PPC_TM_XER:
1416
+
*val = get_reg_val(id, vcpu->arch.xer_tm);
1417
+
break;
1418
+
case KVM_REG_PPC_TM_LR:
1419
+
*val = get_reg_val(id, vcpu->arch.lr_tm);
1420
+
break;
1421
+
case KVM_REG_PPC_TM_CTR:
1422
+
*val = get_reg_val(id, vcpu->arch.ctr_tm);
1423
+
break;
1424
+
case KVM_REG_PPC_TM_FPSCR:
1425
+
*val = get_reg_val(id, vcpu->arch.fp_tm.fpscr);
1426
+
break;
1427
+
case KVM_REG_PPC_TM_AMR:
1428
+
*val = get_reg_val(id, vcpu->arch.amr_tm);
1429
+
break;
1430
+
case KVM_REG_PPC_TM_PPR:
1431
+
*val = get_reg_val(id, vcpu->arch.ppr_tm);
1432
+
break;
1433
+
case KVM_REG_PPC_TM_VRSAVE:
1434
+
*val = get_reg_val(id, vcpu->arch.vrsave_tm);
1435
+
break;
1436
+
case KVM_REG_PPC_TM_VSCR:
1437
+
if (cpu_has_feature(CPU_FTR_ALTIVEC))
1438
+
*val = get_reg_val(id, vcpu->arch.vr_tm.vscr.u[3]);
1439
+
else
1440
+
r = -ENXIO;
1441
+
break;
1442
+
case KVM_REG_PPC_TM_DSCR:
1443
+
*val = get_reg_val(id, vcpu->arch.dscr_tm);
1444
+
break;
1445
+
case KVM_REG_PPC_TM_TAR:
1446
+
*val = get_reg_val(id, vcpu->arch.tar_tm);
1447
+
break;
1448
+
#endif
1541
1449
default:
1542
1450
r = -EINVAL;
1543
1451
break;
···
1638
1412
case KVM_REG_PPC_LPCR_64:
1639
1413
kvmppc_set_lpcr_pr(vcpu, set_reg_val(id, *val));
1640
1414
break;
1415
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1416
+
case KVM_REG_PPC_TFHAR:
1417
+
vcpu->arch.tfhar = set_reg_val(id, *val);
1418
+
break;
1419
+
case KVM_REG_PPC_TFIAR:
1420
+
vcpu->arch.tfiar = set_reg_val(id, *val);
1421
+
break;
1422
+
case KVM_REG_PPC_TEXASR:
1423
+
vcpu->arch.texasr = set_reg_val(id, *val);
1424
+
break;
1425
+
case KVM_REG_PPC_TM_GPR0 ... KVM_REG_PPC_TM_GPR31:
1426
+
vcpu->arch.gpr_tm[id - KVM_REG_PPC_TM_GPR0] =
1427
+
set_reg_val(id, *val);
1428
+
break;
1429
+
case KVM_REG_PPC_TM_VSR0 ... KVM_REG_PPC_TM_VSR63:
1430
+
{
1431
+
int i, j;
1432
+
1433
+
i = id - KVM_REG_PPC_TM_VSR0;
1434
+
if (i < 32)
1435
+
for (j = 0; j < TS_FPRWIDTH; j++)
1436
+
vcpu->arch.fp_tm.fpr[i][j] = val->vsxval[j];
1437
+
else
1438
+
if (cpu_has_feature(CPU_FTR_ALTIVEC))
1439
+
vcpu->arch.vr_tm.vr[i-32] = val->vval;
1440
+
else
1441
+
r = -ENXIO;
1442
+
break;
1443
+
}
1444
+
case KVM_REG_PPC_TM_CR:
1445
+
vcpu->arch.cr_tm = set_reg_val(id, *val);
1446
+
break;
1447
+
case KVM_REG_PPC_TM_XER:
1448
+
vcpu->arch.xer_tm = set_reg_val(id, *val);
1449
+
break;
1450
+
case KVM_REG_PPC_TM_LR:
1451
+
vcpu->arch.lr_tm = set_reg_val(id, *val);
1452
+
break;
1453
+
case KVM_REG_PPC_TM_CTR:
1454
+
vcpu->arch.ctr_tm = set_reg_val(id, *val);
1455
+
break;
1456
+
case KVM_REG_PPC_TM_FPSCR:
1457
+
vcpu->arch.fp_tm.fpscr = set_reg_val(id, *val);
1458
+
break;
1459
+
case KVM_REG_PPC_TM_AMR:
1460
+
vcpu->arch.amr_tm = set_reg_val(id, *val);
1461
+
break;
1462
+
case KVM_REG_PPC_TM_PPR:
1463
+
vcpu->arch.ppr_tm = set_reg_val(id, *val);
1464
+
break;
1465
+
case KVM_REG_PPC_TM_VRSAVE:
1466
+
vcpu->arch.vrsave_tm = set_reg_val(id, *val);
1467
+
break;
1468
+
case KVM_REG_PPC_TM_VSCR:
1469
+
if (cpu_has_feature(CPU_FTR_ALTIVEC))
1470
+
vcpu->arch.vr.vscr.u[3] = set_reg_val(id, *val);
1471
+
else
1472
+
r = -ENXIO;
1473
+
break;
1474
+
case KVM_REG_PPC_TM_DSCR:
1475
+
vcpu->arch.dscr_tm = set_reg_val(id, *val);
1476
+
break;
1477
+
case KVM_REG_PPC_TM_TAR:
1478
+
vcpu->arch.tar_tm = set_reg_val(id, *val);
1479
+
break;
1480
+
#endif
1641
1481
default:
1642
1482
r = -EINVAL;
1643
1483
break;
···
1979
1687
1980
1688
return 0;
1981
1689
}
1690
+
1691
+
static int kvm_configure_mmu_pr(struct kvm *kvm, struct kvm_ppc_mmuv3_cfg *cfg)
1692
+
{
1693
+
if (!cpu_has_feature(CPU_FTR_ARCH_300))
1694
+
return -ENODEV;
1695
+
/* Require flags and process table base and size to all be zero. */
1696
+
if (cfg->flags || cfg->process_table)
1697
+
return -EINVAL;
1698
+
return 0;
1699
+
}
1700
+
1982
1701
#else
1983
1702
static int kvm_vm_ioctl_get_smmu_info_pr(struct kvm *kvm,
1984
1703
struct kvm_ppc_smmu_info *info)
···
2038
1735
static int kvmppc_core_check_processor_compat_pr(void)
2039
1736
{
2040
1737
/*
2041
-
* Disable KVM for Power9 untill the required bits merged.
1738
+
* PR KVM can work on POWER9 inside a guest partition
1739
+
* running in HPT mode. It can't work if we are using
1740
+
* radix translation (because radix provides no way for
1741
+
* a process to have unique translations in quadrant 3).
2042
1742
*/
2043
-
if (cpu_has_feature(CPU_FTR_ARCH_300))
1743
+
if (cpu_has_feature(CPU_FTR_ARCH_300) && radix_enabled())
2044
1744
return -EIO;
2045
1745
return 0;
2046
1746
}
···
2087
1781
.arch_vm_ioctl = kvm_arch_vm_ioctl_pr,
2088
1782
#ifdef CONFIG_PPC_BOOK3S_64
2089
1783
.hcall_implemented = kvmppc_hcall_impl_pr,
1784
+
.configure_mmu = kvm_configure_mmu_pr,
2090
1785
#endif
1786
+
.giveup_ext = kvmppc_giveup_ext,
2091
1787
};
2092
1788
2093
1789
+13
arch/powerpc/kvm/book3s_segment.S
+13
arch/powerpc/kvm/book3s_segment.S
···
383
383
*/
384
384
385
385
PPC_LL r6, HSTATE_HOST_MSR(r13)
386
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
387
+
/*
388
+
* We don't want to change MSR[TS] bits via rfi here.
389
+
* The actual TM handling logic will be in host with
390
+
* recovered DR/IR bits after HSTATE_VMHANDLER.
391
+
* And MSR_TM can be enabled in HOST_MSR so rfid may
392
+
* not suppress this change and can lead to exception.
393
+
* Manually set MSR to prevent TS state change here.
394
+
*/
395
+
mfmsr r7
396
+
rldicl r7, r7, 64 - MSR_TS_S_LG, 62
397
+
rldimi r6, r7, MSR_TS_S_LG, 63 - MSR_TS_T_LG
398
+
#endif
386
399
PPC_LL r8, HSTATE_VMHANDLER(r13)
387
400
388
401
#ifdef CONFIG_PPC64
+2
-2
arch/powerpc/kvm/book3s_xive_template.c
+2
-2
arch/powerpc/kvm/book3s_xive_template.c
···
334
334
*/
335
335
336
336
/* Return interrupt and old CPPR in GPR4 */
337
-
vcpu->arch.gpr[4] = hirq | (old_cppr << 24);
337
+
vcpu->arch.regs.gpr[4] = hirq | (old_cppr << 24);
338
338
339
339
return H_SUCCESS;
340
340
}
···
369
369
hirq = GLUE(X_PFX,scan_interrupts)(xc, pending, scan_poll);
370
370
371
371
/* Return interrupt and old CPPR in GPR4 */
372
-
vcpu->arch.gpr[4] = hirq | (xc->cppr << 24);
372
+
vcpu->arch.regs.gpr[4] = hirq | (xc->cppr << 24);
373
373
374
374
return H_SUCCESS;
375
375
}
+22
-19
arch/powerpc/kvm/booke.c
+22
-19
arch/powerpc/kvm/booke.c
···
77
77
{
78
78
int i;
79
79
80
-
printk("pc: %08lx msr: %08llx\n", vcpu->arch.pc, vcpu->arch.shared->msr);
81
-
printk("lr: %08lx ctr: %08lx\n", vcpu->arch.lr, vcpu->arch.ctr);
80
+
printk("pc: %08lx msr: %08llx\n", vcpu->arch.regs.nip,
81
+
vcpu->arch.shared->msr);
82
+
printk("lr: %08lx ctr: %08lx\n", vcpu->arch.regs.link,
83
+
vcpu->arch.regs.ctr);
82
84
printk("srr0: %08llx srr1: %08llx\n", vcpu->arch.shared->srr0,
83
85
vcpu->arch.shared->srr1);
84
86
···
493
491
if (allowed) {
494
492
switch (int_class) {
495
493
case INT_CLASS_NONCRIT:
496
-
set_guest_srr(vcpu, vcpu->arch.pc,
494
+
set_guest_srr(vcpu, vcpu->arch.regs.nip,
497
495
vcpu->arch.shared->msr);
498
496
break;
499
497
case INT_CLASS_CRIT:
500
-
set_guest_csrr(vcpu, vcpu->arch.pc,
498
+
set_guest_csrr(vcpu, vcpu->arch.regs.nip,
501
499
vcpu->arch.shared->msr);
502
500
break;
503
501
case INT_CLASS_DBG:
504
-
set_guest_dsrr(vcpu, vcpu->arch.pc,
502
+
set_guest_dsrr(vcpu, vcpu->arch.regs.nip,
505
503
vcpu->arch.shared->msr);
506
504
break;
507
505
case INT_CLASS_MC:
508
-
set_guest_mcsrr(vcpu, vcpu->arch.pc,
506
+
set_guest_mcsrr(vcpu, vcpu->arch.regs.nip,
509
507
vcpu->arch.shared->msr);
510
508
break;
511
509
}
512
510
513
-
vcpu->arch.pc = vcpu->arch.ivpr | vcpu->arch.ivor[priority];
511
+
vcpu->arch.regs.nip = vcpu->arch.ivpr |
512
+
vcpu->arch.ivor[priority];
514
513
if (update_esr == true)
515
514
kvmppc_set_esr(vcpu, vcpu->arch.queued_esr);
516
515
if (update_dear == true)
···
829
826
830
827
case EMULATE_FAIL:
831
828
printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n",
832
-
__func__, vcpu->arch.pc, vcpu->arch.last_inst);
829
+
__func__, vcpu->arch.regs.nip, vcpu->arch.last_inst);
833
830
/* For debugging, encode the failing instruction and
834
831
* report it to userspace. */
835
832
run->hw.hardware_exit_reason = ~0ULL << 32;
···
878
875
*/
879
876
vcpu->arch.dbsr = 0;
880
877
run->debug.arch.status = 0;
881
-
run->debug.arch.address = vcpu->arch.pc;
878
+
run->debug.arch.address = vcpu->arch.regs.nip;
882
879
883
880
if (dbsr & (DBSR_IAC1 | DBSR_IAC2 | DBSR_IAC3 | DBSR_IAC4)) {
884
881
run->debug.arch.status |= KVMPPC_DEBUG_BREAKPOINT;
···
974
971
975
972
case EMULATE_FAIL:
976
973
pr_debug("%s: load instruction from guest address %lx failed\n",
977
-
__func__, vcpu->arch.pc);
974
+
__func__, vcpu->arch.regs.nip);
978
975
/* For debugging, encode the failing instruction and
979
976
* report it to userspace. */
980
977
run->hw.hardware_exit_reason = ~0ULL << 32;
···
1172
1169
case BOOKE_INTERRUPT_SPE_FP_DATA:
1173
1170
case BOOKE_INTERRUPT_SPE_FP_ROUND:
1174
1171
printk(KERN_CRIT "%s: unexpected SPE interrupt %u at %08lx\n",
1175
-
__func__, exit_nr, vcpu->arch.pc);
1172
+
__func__, exit_nr, vcpu->arch.regs.nip);
1176
1173
run->hw.hardware_exit_reason = exit_nr;
1177
1174
r = RESUME_HOST;
1178
1175
break;
···
1302
1299
}
1303
1300
1304
1301
case BOOKE_INTERRUPT_ITLB_MISS: {
1305
-
unsigned long eaddr = vcpu->arch.pc;
1302
+
unsigned long eaddr = vcpu->arch.regs.nip;
1306
1303
gpa_t gpaddr;
1307
1304
gfn_t gfn;
1308
1305
int gtlb_index;
···
1394
1391
int i;
1395
1392
int r;
1396
1393
1397
-
vcpu->arch.pc = 0;
1394
+
vcpu->arch.regs.nip = 0;
1398
1395
vcpu->arch.shared->pir = vcpu->vcpu_id;
1399
1396
kvmppc_set_gpr(vcpu, 1, (16<<20) - 8); /* -8 for the callee-save LR slot */
1400
1397
kvmppc_set_msr(vcpu, 0);
···
1443
1440
1444
1441
vcpu_load(vcpu);
1445
1442
1446
-
regs->pc = vcpu->arch.pc;
1443
+
regs->pc = vcpu->arch.regs.nip;
1447
1444
regs->cr = kvmppc_get_cr(vcpu);
1448
-
regs->ctr = vcpu->arch.ctr;
1449
-
regs->lr = vcpu->arch.lr;
1445
+
regs->ctr = vcpu->arch.regs.ctr;
1446
+
regs->lr = vcpu->arch.regs.link;
1450
1447
regs->xer = kvmppc_get_xer(vcpu);
1451
1448
regs->msr = vcpu->arch.shared->msr;
1452
1449
regs->srr0 = kvmppc_get_srr0(vcpu);
···
1474
1471
1475
1472
vcpu_load(vcpu);
1476
1473
1477
-
vcpu->arch.pc = regs->pc;
1474
+
vcpu->arch.regs.nip = regs->pc;
1478
1475
kvmppc_set_cr(vcpu, regs->cr);
1479
-
vcpu->arch.ctr = regs->ctr;
1480
-
vcpu->arch.lr = regs->lr;
1476
+
vcpu->arch.regs.ctr = regs->ctr;
1477
+
vcpu->arch.regs.link = regs->lr;
1481
1478
kvmppc_set_xer(vcpu, regs->xer);
1482
1479
kvmppc_set_msr(vcpu, regs->msr);
1483
1480
kvmppc_set_srr0(vcpu, regs->srr0);
+3
-3
arch/powerpc/kvm/booke_emulate.c
+3
-3
arch/powerpc/kvm/booke_emulate.c
···
34
34
35
35
static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu)
36
36
{
37
-
vcpu->arch.pc = vcpu->arch.shared->srr0;
37
+
vcpu->arch.regs.nip = vcpu->arch.shared->srr0;
38
38
kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1);
39
39
}
40
40
41
41
static void kvmppc_emul_rfdi(struct kvm_vcpu *vcpu)
42
42
{
43
-
vcpu->arch.pc = vcpu->arch.dsrr0;
43
+
vcpu->arch.regs.nip = vcpu->arch.dsrr0;
44
44
kvmppc_set_msr(vcpu, vcpu->arch.dsrr1);
45
45
}
46
46
47
47
static void kvmppc_emul_rfci(struct kvm_vcpu *vcpu)
48
48
{
49
-
vcpu->arch.pc = vcpu->arch.csrr0;
49
+
vcpu->arch.regs.nip = vcpu->arch.csrr0;
50
50
kvmppc_set_msr(vcpu, vcpu->arch.csrr1);
51
51
}
52
52
+3
-3
arch/powerpc/kvm/e500_emulate.c
+3
-3
arch/powerpc/kvm/e500_emulate.c
···
53
53
54
54
static int kvmppc_e500_emul_msgclr(struct kvm_vcpu *vcpu, int rb)
55
55
{
56
-
ulong param = vcpu->arch.gpr[rb];
56
+
ulong param = vcpu->arch.regs.gpr[rb];
57
57
int prio = dbell2prio(param);
58
58
59
59
if (prio < 0)
···
65
65
66
66
static int kvmppc_e500_emul_msgsnd(struct kvm_vcpu *vcpu, int rb)
67
67
{
68
-
ulong param = vcpu->arch.gpr[rb];
68
+
ulong param = vcpu->arch.regs.gpr[rb];
69
69
int prio = dbell2prio(rb);
70
70
int pir = param & PPC_DBELL_PIR_MASK;
71
71
int i;
···
94
94
switch (get_oc(inst)) {
95
95
case EHPRIV_OC_DEBUG:
96
96
run->exit_reason = KVM_EXIT_DEBUG;
97
-
run->debug.arch.address = vcpu->arch.pc;
97
+
run->debug.arch.address = vcpu->arch.regs.nip;
98
98
run->debug.arch.status = 0;
99
99
kvmppc_account_exit(vcpu, DEBUG_EXITS);
100
100
emulated = EMULATE_EXIT_USER;
+1
-1
arch/powerpc/kvm/e500_mmu.c
+1
-1
arch/powerpc/kvm/e500_mmu.c
+4
-4
arch/powerpc/kvm/e500_mmu_host.c
+4
-4
arch/powerpc/kvm/e500_mmu_host.c
···
625
625
}
626
626
627
627
#ifdef CONFIG_KVM_BOOKE_HV
628
-
int kvmppc_load_last_inst(struct kvm_vcpu *vcpu, enum instruction_type type,
629
-
u32 *instr)
628
+
int kvmppc_load_last_inst(struct kvm_vcpu *vcpu,
629
+
enum instruction_fetch_type type, u32 *instr)
630
630
{
631
631
gva_t geaddr;
632
632
hpa_t addr;
···
715
715
return EMULATE_DONE;
716
716
}
717
717
#else
718
-
int kvmppc_load_last_inst(struct kvm_vcpu *vcpu, enum instruction_type type,
719
-
u32 *instr)
718
+
int kvmppc_load_last_inst(struct kvm_vcpu *vcpu,
719
+
enum instruction_fetch_type type, u32 *instr)
720
720
{
721
721
return EMULATE_AGAIN;
722
722
}
+245
-547
arch/powerpc/kvm/emulate_loadstore.c
+245
-547
arch/powerpc/kvm/emulate_loadstore.c
···
31
31
#include <asm/kvm_ppc.h>
32
32
#include <asm/disassemble.h>
33
33
#include <asm/ppc-opcode.h>
34
+
#include <asm/sstep.h>
34
35
#include "timing.h"
35
36
#include "trace.h"
36
37
···
85
84
struct kvm_run *run = vcpu->run;
86
85
u32 inst;
87
86
int ra, rs, rt;
88
-
enum emulation_result emulated;
87
+
enum emulation_result emulated = EMULATE_FAIL;
89
88
int advance = 1;
89
+
struct instruction_op op;
90
90
91
91
/* this default type might be overwritten by subcategories */
92
92
kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS);
···
109
107
vcpu->arch.mmio_vsx_tx_sx_enabled = get_tx_or_sx(inst);
110
108
vcpu->arch.mmio_vsx_copy_nums = 0;
111
109
vcpu->arch.mmio_vsx_offset = 0;
112
-
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_NONE;
110
+
vcpu->arch.mmio_copy_type = KVMPPC_VSX_COPY_NONE;
113
111
vcpu->arch.mmio_sp64_extend = 0;
114
112
vcpu->arch.mmio_sign_extend = 0;
115
113
vcpu->arch.mmio_vmx_copy_nums = 0;
114
+
vcpu->arch.mmio_vmx_offset = 0;
115
+
vcpu->arch.mmio_host_swabbed = 0;
116
116
117
-
switch (get_op(inst)) {
118
-
case 31:
119
-
switch (get_xop(inst)) {
120
-
case OP_31_XOP_LWZX:
121
-
emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
117
+
emulated = EMULATE_FAIL;
118
+
vcpu->arch.regs.msr = vcpu->arch.shared->msr;
119
+
vcpu->arch.regs.ccr = vcpu->arch.cr;
120
+
if (analyse_instr(&op, &vcpu->arch.regs, inst) == 0) {
121
+
int type = op.type & INSTR_TYPE_MASK;
122
+
int size = GETSIZE(op.type);
123
+
124
+
switch (type) {
125
+
case LOAD: {
126
+
int instr_byte_swap = op.type & BYTEREV;
127
+
128
+
if (op.type & SIGNEXT)
129
+
emulated = kvmppc_handle_loads(run, vcpu,
130
+
op.reg, size, !instr_byte_swap);
131
+
else
132
+
emulated = kvmppc_handle_load(run, vcpu,
133
+
op.reg, size, !instr_byte_swap);
134
+
135
+
if ((op.type & UPDATE) && (emulated != EMULATE_FAIL))
136
+
kvmppc_set_gpr(vcpu, op.update_reg, op.ea);
137
+
122
138
break;
139
+
}
140
+
#ifdef CONFIG_PPC_FPU
141
+
case LOAD_FP:
142
+
if (kvmppc_check_fp_disabled(vcpu))
143
+
return EMULATE_DONE;
123
144
124
-
case OP_31_XOP_LWZUX:
125
-
emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
126
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
145
+
if (op.type & FPCONV)
146
+
vcpu->arch.mmio_sp64_extend = 1;
147
+
148
+
if (op.type & SIGNEXT)
149
+
emulated = kvmppc_handle_loads(run, vcpu,
150
+
KVM_MMIO_REG_FPR|op.reg, size, 1);
151
+
else
152
+
emulated = kvmppc_handle_load(run, vcpu,
153
+
KVM_MMIO_REG_FPR|op.reg, size, 1);
154
+
155
+
if ((op.type & UPDATE) && (emulated != EMULATE_FAIL))
156
+
kvmppc_set_gpr(vcpu, op.update_reg, op.ea);
157
+
127
158
break;
159
+
#endif
160
+
#ifdef CONFIG_ALTIVEC
161
+
case LOAD_VMX:
162
+
if (kvmppc_check_altivec_disabled(vcpu))
163
+
return EMULATE_DONE;
128
164
129
-
case OP_31_XOP_LBZX:
130
-
emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
165
+
/* Hardware enforces alignment of VMX accesses */
166
+
vcpu->arch.vaddr_accessed &= ~((unsigned long)size - 1);
167
+
vcpu->arch.paddr_accessed &= ~((unsigned long)size - 1);
168
+
169
+
if (size == 16) { /* lvx */
170
+
vcpu->arch.mmio_copy_type =
171
+
KVMPPC_VMX_COPY_DWORD;
172
+
} else if (size == 4) { /* lvewx */
173
+
vcpu->arch.mmio_copy_type =
174
+
KVMPPC_VMX_COPY_WORD;
175
+
} else if (size == 2) { /* lvehx */
176
+
vcpu->arch.mmio_copy_type =
177
+
KVMPPC_VMX_COPY_HWORD;
178
+
} else if (size == 1) { /* lvebx */
179
+
vcpu->arch.mmio_copy_type =
180
+
KVMPPC_VMX_COPY_BYTE;
181
+
} else
182
+
break;
183
+
184
+
vcpu->arch.mmio_vmx_offset =
185
+
(vcpu->arch.vaddr_accessed & 0xf)/size;
186
+
187
+
if (size == 16) {
188
+
vcpu->arch.mmio_vmx_copy_nums = 2;
189
+
emulated = kvmppc_handle_vmx_load(run,
190
+
vcpu, KVM_MMIO_REG_VMX|op.reg,
191
+
8, 1);
192
+
} else {
193
+
vcpu->arch.mmio_vmx_copy_nums = 1;
194
+
emulated = kvmppc_handle_vmx_load(run, vcpu,
195
+
KVM_MMIO_REG_VMX|op.reg,
196
+
size, 1);
197
+
}
131
198
break;
199
+
#endif
200
+
#ifdef CONFIG_VSX
201
+
case LOAD_VSX: {
202
+
int io_size_each;
132
203
133
-
case OP_31_XOP_LBZUX:
134
-
emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
135
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
204
+
if (op.vsx_flags & VSX_CHECK_VEC) {
205
+
if (kvmppc_check_altivec_disabled(vcpu))
206
+
return EMULATE_DONE;
207
+
} else {
208
+
if (kvmppc_check_vsx_disabled(vcpu))
209
+
return EMULATE_DONE;
210
+
}
211
+
212
+
if (op.vsx_flags & VSX_FPCONV)
213
+
vcpu->arch.mmio_sp64_extend = 1;
214
+
215
+
if (op.element_size == 8) {
216
+
if (op.vsx_flags & VSX_SPLAT)
217
+
vcpu->arch.mmio_copy_type =
218
+
KVMPPC_VSX_COPY_DWORD_LOAD_DUMP;
219
+
else
220
+
vcpu->arch.mmio_copy_type =
221
+
KVMPPC_VSX_COPY_DWORD;
222
+
} else if (op.element_size == 4) {
223
+
if (op.vsx_flags & VSX_SPLAT)
224
+
vcpu->arch.mmio_copy_type =
225
+
KVMPPC_VSX_COPY_WORD_LOAD_DUMP;
226
+
else
227
+
vcpu->arch.mmio_copy_type =
228
+
KVMPPC_VSX_COPY_WORD;
229
+
} else
230
+
break;
231
+
232
+
if (size < op.element_size) {
233
+
/* precision convert case: lxsspx, etc */
234
+
vcpu->arch.mmio_vsx_copy_nums = 1;
235
+
io_size_each = size;
236
+
} else { /* lxvw4x, lxvd2x, etc */
237
+
vcpu->arch.mmio_vsx_copy_nums =
238
+
size/op.element_size;
239
+
io_size_each = op.element_size;
240
+
}
241
+
242
+
emulated = kvmppc_handle_vsx_load(run, vcpu,
243
+
KVM_MMIO_REG_VSX | (op.reg & 0x1f),
244
+
io_size_each, 1, op.type & SIGNEXT);
136
245
break;
246
+
}
247
+
#endif
248
+
case STORE:
249
+
/* if need byte reverse, op.val has been reversed by
250
+
* analyse_instr().
251
+
*/
252
+
emulated = kvmppc_handle_store(run, vcpu, op.val,
253
+
size, 1);
137
254
138
-
case OP_31_XOP_STDX:
255
+
if ((op.type & UPDATE) && (emulated != EMULATE_FAIL))
256
+
kvmppc_set_gpr(vcpu, op.update_reg, op.ea);
257
+
258
+
break;
259
+
#ifdef CONFIG_PPC_FPU
260
+
case STORE_FP:
261
+
if (kvmppc_check_fp_disabled(vcpu))
262
+
return EMULATE_DONE;
263
+
264
+
/* The FP registers need to be flushed so that
265
+
* kvmppc_handle_store() can read actual FP vals
266
+
* from vcpu->arch.
267
+
*/
268
+
if (vcpu->kvm->arch.kvm_ops->giveup_ext)
269
+
vcpu->kvm->arch.kvm_ops->giveup_ext(vcpu,
270
+
MSR_FP);
271
+
272
+
if (op.type & FPCONV)
273
+
vcpu->arch.mmio_sp64_extend = 1;
274
+
139
275
emulated = kvmppc_handle_store(run, vcpu,
140
-
kvmppc_get_gpr(vcpu, rs), 8, 1);
141
-
break;
276
+
VCPU_FPR(vcpu, op.reg), size, 1);
142
277
143
-
case OP_31_XOP_STDUX:
144
-
emulated = kvmppc_handle_store(run, vcpu,
145
-
kvmppc_get_gpr(vcpu, rs), 8, 1);
146
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
147
-
break;
278
+
if ((op.type & UPDATE) && (emulated != EMULATE_FAIL))
279
+
kvmppc_set_gpr(vcpu, op.update_reg, op.ea);
148
280
149
-
case OP_31_XOP_STWX:
150
-
emulated = kvmppc_handle_store(run, vcpu,
151
-
kvmppc_get_gpr(vcpu, rs), 4, 1);
152
281
break;
282
+
#endif
283
+
#ifdef CONFIG_ALTIVEC
284
+
case STORE_VMX:
285
+
if (kvmppc_check_altivec_disabled(vcpu))
286
+
return EMULATE_DONE;
153
287
154
-
case OP_31_XOP_STWUX:
155
-
emulated = kvmppc_handle_store(run, vcpu,
156
-
kvmppc_get_gpr(vcpu, rs), 4, 1);
157
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
288
+
/* Hardware enforces alignment of VMX accesses. */
289
+
vcpu->arch.vaddr_accessed &= ~((unsigned long)size - 1);
290
+
vcpu->arch.paddr_accessed &= ~((unsigned long)size - 1);
291
+
292
+
if (vcpu->kvm->arch.kvm_ops->giveup_ext)
293
+
vcpu->kvm->arch.kvm_ops->giveup_ext(vcpu,
294
+
MSR_VEC);
295
+
if (size == 16) { /* stvx */
296
+
vcpu->arch.mmio_copy_type =
297
+
KVMPPC_VMX_COPY_DWORD;
298
+
} else if (size == 4) { /* stvewx */
299
+
vcpu->arch.mmio_copy_type =
300
+
KVMPPC_VMX_COPY_WORD;
301
+
} else if (size == 2) { /* stvehx */
302
+
vcpu->arch.mmio_copy_type =
303
+
KVMPPC_VMX_COPY_HWORD;
304
+
} else if (size == 1) { /* stvebx */
305
+
vcpu->arch.mmio_copy_type =
306
+
KVMPPC_VMX_COPY_BYTE;
307
+
} else
308
+
break;
309
+
310
+
vcpu->arch.mmio_vmx_offset =
311
+
(vcpu->arch.vaddr_accessed & 0xf)/size;
312
+
313
+
if (size == 16) {
314
+
vcpu->arch.mmio_vmx_copy_nums = 2;
315
+
emulated = kvmppc_handle_vmx_store(run,
316
+
vcpu, op.reg, 8, 1);
317
+
} else {
318
+
vcpu->arch.mmio_vmx_copy_nums = 1;
319
+
emulated = kvmppc_handle_vmx_store(run,
320
+
vcpu, op.reg, size, 1);
321
+
}
322
+
158
323
break;
324
+
#endif
325
+
#ifdef CONFIG_VSX
326
+
case STORE_VSX: {
327
+
int io_size_each;
159
328
160
-
case OP_31_XOP_STBX:
161
-
emulated = kvmppc_handle_store(run, vcpu,
162
-
kvmppc_get_gpr(vcpu, rs), 1, 1);
329
+
if (op.vsx_flags & VSX_CHECK_VEC) {
330
+
if (kvmppc_check_altivec_disabled(vcpu))
331
+
return EMULATE_DONE;
332
+
} else {
333
+
if (kvmppc_check_vsx_disabled(vcpu))
334
+
return EMULATE_DONE;
335
+
}
336
+
337
+
if (vcpu->kvm->arch.kvm_ops->giveup_ext)
338
+
vcpu->kvm->arch.kvm_ops->giveup_ext(vcpu,
339
+
MSR_VSX);
340
+
341
+
if (op.vsx_flags & VSX_FPCONV)
342
+
vcpu->arch.mmio_sp64_extend = 1;
343
+
344
+
if (op.element_size == 8)
345
+
vcpu->arch.mmio_copy_type =
346
+
KVMPPC_VSX_COPY_DWORD;
347
+
else if (op.element_size == 4)
348
+
vcpu->arch.mmio_copy_type =
349
+
KVMPPC_VSX_COPY_WORD;
350
+
else
351
+
break;
352
+
353
+
if (size < op.element_size) {
354
+
/* precise conversion case, like stxsspx */
355
+
vcpu->arch.mmio_vsx_copy_nums = 1;
356
+
io_size_each = size;
357
+
} else { /* stxvw4x, stxvd2x, etc */
358
+
vcpu->arch.mmio_vsx_copy_nums =
359
+
size/op.element_size;
360
+
io_size_each = op.element_size;
361
+
}
362
+
363
+
emulated = kvmppc_handle_vsx_store(run, vcpu,
364
+
op.reg & 0x1f, io_size_each, 1);
163
365
break;
164
-
165
-
case OP_31_XOP_STBUX:
166
-
emulated = kvmppc_handle_store(run, vcpu,
167
-
kvmppc_get_gpr(vcpu, rs), 1, 1);
168
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
169
-
break;
170
-
171
-
case OP_31_XOP_LHAX:
172
-
emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
173
-
break;
174
-
175
-
case OP_31_XOP_LHAUX:
176
-
emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
177
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
178
-
break;
179
-
180
-
case OP_31_XOP_LHZX:
181
-
emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
182
-
break;
183
-
184
-
case OP_31_XOP_LHZUX:
185
-
emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
186
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
187
-
break;
188
-
189
-
case OP_31_XOP_STHX:
190
-
emulated = kvmppc_handle_store(run, vcpu,
191
-
kvmppc_get_gpr(vcpu, rs), 2, 1);
192
-
break;
193
-
194
-
case OP_31_XOP_STHUX:
195
-
emulated = kvmppc_handle_store(run, vcpu,
196
-
kvmppc_get_gpr(vcpu, rs), 2, 1);
197
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
198
-
break;
199
-
200
-
case OP_31_XOP_DCBST:
201
-
case OP_31_XOP_DCBF:
202
-
case OP_31_XOP_DCBI:
366
+
}
367
+
#endif
368
+
case CACHEOP:
203
369
/* Do nothing. The guest is performing dcbi because
204
370
* hardware DMA is not snooped by the dcache, but
205
371
* emulated DMA either goes through the dcache as
206
372
* normal writes, or the host kernel has handled dcache
207
-
* coherence. */
208
-
break;
209
-
210
-
case OP_31_XOP_LWBRX:
211
-
emulated = kvmppc_handle_load(run, vcpu, rt, 4, 0);
212
-
break;
213
-
214
-
case OP_31_XOP_STWBRX:
215
-
emulated = kvmppc_handle_store(run, vcpu,
216
-
kvmppc_get_gpr(vcpu, rs), 4, 0);
217
-
break;
218
-
219
-
case OP_31_XOP_LHBRX:
220
-
emulated = kvmppc_handle_load(run, vcpu, rt, 2, 0);
221
-
break;
222
-
223
-
case OP_31_XOP_STHBRX:
224
-
emulated = kvmppc_handle_store(run, vcpu,
225
-
kvmppc_get_gpr(vcpu, rs), 2, 0);
226
-
break;
227
-
228
-
case OP_31_XOP_LDBRX:
229
-
emulated = kvmppc_handle_load(run, vcpu, rt, 8, 0);
230
-
break;
231
-
232
-
case OP_31_XOP_STDBRX:
233
-
emulated = kvmppc_handle_store(run, vcpu,
234
-
kvmppc_get_gpr(vcpu, rs), 8, 0);
235
-
break;
236
-
237
-
case OP_31_XOP_LDX:
238
-
emulated = kvmppc_handle_load(run, vcpu, rt, 8, 1);
239
-
break;
240
-
241
-
case OP_31_XOP_LDUX:
242
-
emulated = kvmppc_handle_load(run, vcpu, rt, 8, 1);
243
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
244
-
break;
245
-
246
-
case OP_31_XOP_LWAX:
247
-
emulated = kvmppc_handle_loads(run, vcpu, rt, 4, 1);
248
-
break;
249
-
250
-
case OP_31_XOP_LWAUX:
251
-
emulated = kvmppc_handle_loads(run, vcpu, rt, 4, 1);
252
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
253
-
break;
254
-
255
-
#ifdef CONFIG_PPC_FPU
256
-
case OP_31_XOP_LFSX:
257
-
if (kvmppc_check_fp_disabled(vcpu))
258
-
return EMULATE_DONE;
259
-
vcpu->arch.mmio_sp64_extend = 1;
260
-
emulated = kvmppc_handle_load(run, vcpu,
261
-
KVM_MMIO_REG_FPR|rt, 4, 1);
262
-
break;
263
-
264
-
case OP_31_XOP_LFSUX:
265
-
if (kvmppc_check_fp_disabled(vcpu))
266
-
return EMULATE_DONE;
267
-
vcpu->arch.mmio_sp64_extend = 1;
268
-
emulated = kvmppc_handle_load(run, vcpu,
269
-
KVM_MMIO_REG_FPR|rt, 4, 1);
270
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
271
-
break;
272
-
273
-
case OP_31_XOP_LFDX:
274
-
if (kvmppc_check_fp_disabled(vcpu))
275
-
return EMULATE_DONE;
276
-
emulated = kvmppc_handle_load(run, vcpu,
277
-
KVM_MMIO_REG_FPR|rt, 8, 1);
278
-
break;
279
-
280
-
case OP_31_XOP_LFDUX:
281
-
if (kvmppc_check_fp_disabled(vcpu))
282
-
return EMULATE_DONE;
283
-
emulated = kvmppc_handle_load(run, vcpu,
284
-
KVM_MMIO_REG_FPR|rt, 8, 1);
285
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
286
-
break;
287
-
288
-
case OP_31_XOP_LFIWAX:
289
-
if (kvmppc_check_fp_disabled(vcpu))
290
-
return EMULATE_DONE;
291
-
emulated = kvmppc_handle_loads(run, vcpu,
292
-
KVM_MMIO_REG_FPR|rt, 4, 1);
293
-
break;
294
-
295
-
case OP_31_XOP_LFIWZX:
296
-
if (kvmppc_check_fp_disabled(vcpu))
297
-
return EMULATE_DONE;
298
-
emulated = kvmppc_handle_load(run, vcpu,
299
-
KVM_MMIO_REG_FPR|rt, 4, 1);
300
-
break;
301
-
302
-
case OP_31_XOP_STFSX:
303
-
if (kvmppc_check_fp_disabled(vcpu))
304
-
return EMULATE_DONE;
305
-
vcpu->arch.mmio_sp64_extend = 1;
306
-
emulated = kvmppc_handle_store(run, vcpu,
307
-
VCPU_FPR(vcpu, rs), 4, 1);
308
-
break;
309
-
310
-
case OP_31_XOP_STFSUX:
311
-
if (kvmppc_check_fp_disabled(vcpu))
312
-
return EMULATE_DONE;
313
-
vcpu->arch.mmio_sp64_extend = 1;
314
-
emulated = kvmppc_handle_store(run, vcpu,
315
-
VCPU_FPR(vcpu, rs), 4, 1);
316
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
317
-
break;
318
-
319
-
case OP_31_XOP_STFDX:
320
-
if (kvmppc_check_fp_disabled(vcpu))
321
-
return EMULATE_DONE;
322
-
emulated = kvmppc_handle_store(run, vcpu,
323
-
VCPU_FPR(vcpu, rs), 8, 1);
324
-
break;
325
-
326
-
case OP_31_XOP_STFDUX:
327
-
if (kvmppc_check_fp_disabled(vcpu))
328
-
return EMULATE_DONE;
329
-
emulated = kvmppc_handle_store(run, vcpu,
330
-
VCPU_FPR(vcpu, rs), 8, 1);
331
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
332
-
break;
333
-
334
-
case OP_31_XOP_STFIWX:
335
-
if (kvmppc_check_fp_disabled(vcpu))
336
-
return EMULATE_DONE;
337
-
emulated = kvmppc_handle_store(run, vcpu,
338
-
VCPU_FPR(vcpu, rs), 4, 1);
339
-
break;
340
-
#endif
341
-
342
-
#ifdef CONFIG_VSX
343
-
case OP_31_XOP_LXSDX:
344
-
if (kvmppc_check_vsx_disabled(vcpu))
345
-
return EMULATE_DONE;
346
-
vcpu->arch.mmio_vsx_copy_nums = 1;
347
-
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_DWORD;
348
-
emulated = kvmppc_handle_vsx_load(run, vcpu,
349
-
KVM_MMIO_REG_VSX|rt, 8, 1, 0);
350
-
break;
351
-
352
-
case OP_31_XOP_LXSSPX:
353
-
if (kvmppc_check_vsx_disabled(vcpu))
354
-
return EMULATE_DONE;
355
-
vcpu->arch.mmio_vsx_copy_nums = 1;
356
-
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_DWORD;
357
-
vcpu->arch.mmio_sp64_extend = 1;
358
-
emulated = kvmppc_handle_vsx_load(run, vcpu,
359
-
KVM_MMIO_REG_VSX|rt, 4, 1, 0);
360
-
break;
361
-
362
-
case OP_31_XOP_LXSIWAX:
363
-
if (kvmppc_check_vsx_disabled(vcpu))
364
-
return EMULATE_DONE;
365
-
vcpu->arch.mmio_vsx_copy_nums = 1;
366
-
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_DWORD;
367
-
emulated = kvmppc_handle_vsx_load(run, vcpu,
368
-
KVM_MMIO_REG_VSX|rt, 4, 1, 1);
369
-
break;
370
-
371
-
case OP_31_XOP_LXSIWZX:
372
-
if (kvmppc_check_vsx_disabled(vcpu))
373
-
return EMULATE_DONE;
374
-
vcpu->arch.mmio_vsx_copy_nums = 1;
375
-
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_DWORD;
376
-
emulated = kvmppc_handle_vsx_load(run, vcpu,
377
-
KVM_MMIO_REG_VSX|rt, 4, 1, 0);
378
-
break;
379
-
380
-
case OP_31_XOP_LXVD2X:
381
-
/*
382
-
* In this case, the official load/store process is like this:
383
-
* Step1, exit from vm by page fault isr, then kvm save vsr.
384
-
* Please see guest_exit_cont->store_fp_state->SAVE_32VSRS
385
-
* as reference.
386
-
*
387
-
* Step2, copy data between memory and VCPU
388
-
* Notice: for LXVD2X/STXVD2X/LXVW4X/STXVW4X, we use
389
-
* 2copies*8bytes or 4copies*4bytes
390
-
* to simulate one copy of 16bytes.
391
-
* Also there is an endian issue here, we should notice the
392
-
* layout of memory.
393
-
* Please see MARCO of LXVD2X_ROT/STXVD2X_ROT as more reference.
394
-
* If host is little-endian, kvm will call XXSWAPD for
395
-
* LXVD2X_ROT/STXVD2X_ROT.
396
-
* So, if host is little-endian,
397
-
* the postion of memeory should be swapped.
398
-
*
399
-
* Step3, return to guest, kvm reset register.
400
-
* Please see kvmppc_hv_entry->load_fp_state->REST_32VSRS
401
-
* as reference.
402
-
*/
403
-
if (kvmppc_check_vsx_disabled(vcpu))
404
-
return EMULATE_DONE;
405
-
vcpu->arch.mmio_vsx_copy_nums = 2;
406
-
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_DWORD;
407
-
emulated = kvmppc_handle_vsx_load(run, vcpu,
408
-
KVM_MMIO_REG_VSX|rt, 8, 1, 0);
409
-
break;
410
-
411
-
case OP_31_XOP_LXVW4X:
412
-
if (kvmppc_check_vsx_disabled(vcpu))
413
-
return EMULATE_DONE;
414
-
vcpu->arch.mmio_vsx_copy_nums = 4;
415
-
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_WORD;
416
-
emulated = kvmppc_handle_vsx_load(run, vcpu,
417
-
KVM_MMIO_REG_VSX|rt, 4, 1, 0);
418
-
break;
419
-
420
-
case OP_31_XOP_LXVDSX:
421
-
if (kvmppc_check_vsx_disabled(vcpu))
422
-
return EMULATE_DONE;
423
-
vcpu->arch.mmio_vsx_copy_nums = 1;
424
-
vcpu->arch.mmio_vsx_copy_type =
425
-
KVMPPC_VSX_COPY_DWORD_LOAD_DUMP;
426
-
emulated = kvmppc_handle_vsx_load(run, vcpu,
427
-
KVM_MMIO_REG_VSX|rt, 8, 1, 0);
428
-
break;
429
-
430
-
case OP_31_XOP_STXSDX:
431
-
if (kvmppc_check_vsx_disabled(vcpu))
432
-
return EMULATE_DONE;
433
-
vcpu->arch.mmio_vsx_copy_nums = 1;
434
-
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_DWORD;
435
-
emulated = kvmppc_handle_vsx_store(run, vcpu,
436
-
rs, 8, 1);
437
-
break;
438
-
439
-
case OP_31_XOP_STXSSPX:
440
-
if (kvmppc_check_vsx_disabled(vcpu))
441
-
return EMULATE_DONE;
442
-
vcpu->arch.mmio_vsx_copy_nums = 1;
443
-
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_DWORD;
444
-
vcpu->arch.mmio_sp64_extend = 1;
445
-
emulated = kvmppc_handle_vsx_store(run, vcpu,
446
-
rs, 4, 1);
447
-
break;
448
-
449
-
case OP_31_XOP_STXSIWX:
450
-
if (kvmppc_check_vsx_disabled(vcpu))
451
-
return EMULATE_DONE;
452
-
vcpu->arch.mmio_vsx_offset = 1;
453
-
vcpu->arch.mmio_vsx_copy_nums = 1;
454
-
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_WORD;
455
-
emulated = kvmppc_handle_vsx_store(run, vcpu,
456
-
rs, 4, 1);
457
-
break;
458
-
459
-
case OP_31_XOP_STXVD2X:
460
-
if (kvmppc_check_vsx_disabled(vcpu))
461
-
return EMULATE_DONE;
462
-
vcpu->arch.mmio_vsx_copy_nums = 2;
463
-
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_DWORD;
464
-
emulated = kvmppc_handle_vsx_store(run, vcpu,
465
-
rs, 8, 1);
466
-
break;
467
-
468
-
case OP_31_XOP_STXVW4X:
469
-
if (kvmppc_check_vsx_disabled(vcpu))
470
-
return EMULATE_DONE;
471
-
vcpu->arch.mmio_vsx_copy_nums = 4;
472
-
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_WORD;
473
-
emulated = kvmppc_handle_vsx_store(run, vcpu,
474
-
rs, 4, 1);
475
-
break;
476
-
#endif /* CONFIG_VSX */
477
-
478
-
#ifdef CONFIG_ALTIVEC
479
-
case OP_31_XOP_LVX:
480
-
if (kvmppc_check_altivec_disabled(vcpu))
481
-
return EMULATE_DONE;
482
-
vcpu->arch.vaddr_accessed &= ~0xFULL;
483
-
vcpu->arch.paddr_accessed &= ~0xFULL;
484
-
vcpu->arch.mmio_vmx_copy_nums = 2;
485
-
emulated = kvmppc_handle_load128_by2x64(run, vcpu,
486
-
KVM_MMIO_REG_VMX|rt, 1);
487
-
break;
488
-
489
-
case OP_31_XOP_STVX:
490
-
if (kvmppc_check_altivec_disabled(vcpu))
491
-
return EMULATE_DONE;
492
-
vcpu->arch.vaddr_accessed &= ~0xFULL;
493
-
vcpu->arch.paddr_accessed &= ~0xFULL;
494
-
vcpu->arch.mmio_vmx_copy_nums = 2;
495
-
emulated = kvmppc_handle_store128_by2x64(run, vcpu,
496
-
rs, 1);
497
-
break;
498
-
#endif /* CONFIG_ALTIVEC */
499
-
500
-
default:
501
-
emulated = EMULATE_FAIL;
502
-
break;
503
-
}
504
-
break;
505
-
506
-
case OP_LWZ:
507
-
emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
508
-
break;
509
-
510
-
#ifdef CONFIG_PPC_FPU
511
-
case OP_STFS:
512
-
if (kvmppc_check_fp_disabled(vcpu))
513
-
return EMULATE_DONE;
514
-
vcpu->arch.mmio_sp64_extend = 1;
515
-
emulated = kvmppc_handle_store(run, vcpu,
516
-
VCPU_FPR(vcpu, rs),
517
-
4, 1);
518
-
break;
519
-
520
-
case OP_STFSU:
521
-
if (kvmppc_check_fp_disabled(vcpu))
522
-
return EMULATE_DONE;
523
-
vcpu->arch.mmio_sp64_extend = 1;
524
-
emulated = kvmppc_handle_store(run, vcpu,
525
-
VCPU_FPR(vcpu, rs),
526
-
4, 1);
527
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
528
-
break;
529
-
530
-
case OP_STFD:
531
-
if (kvmppc_check_fp_disabled(vcpu))
532
-
return EMULATE_DONE;
533
-
emulated = kvmppc_handle_store(run, vcpu,
534
-
VCPU_FPR(vcpu, rs),
535
-
8, 1);
536
-
break;
537
-
538
-
case OP_STFDU:
539
-
if (kvmppc_check_fp_disabled(vcpu))
540
-
return EMULATE_DONE;
541
-
emulated = kvmppc_handle_store(run, vcpu,
542
-
VCPU_FPR(vcpu, rs),
543
-
8, 1);
544
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
545
-
break;
546
-
#endif
547
-
548
-
case OP_LD:
549
-
rt = get_rt(inst);
550
-
switch (inst & 3) {
551
-
case 0: /* ld */
552
-
emulated = kvmppc_handle_load(run, vcpu, rt, 8, 1);
553
-
break;
554
-
case 1: /* ldu */
555
-
emulated = kvmppc_handle_load(run, vcpu, rt, 8, 1);
556
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
557
-
break;
558
-
case 2: /* lwa */
559
-
emulated = kvmppc_handle_loads(run, vcpu, rt, 4, 1);
373
+
* coherence.
374
+
*/
375
+
emulated = EMULATE_DONE;
560
376
break;
561
377
default:
562
-
emulated = EMULATE_FAIL;
563
-
}
564
-
break;
565
-
566
-
case OP_LWZU:
567
-
emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
568
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
569
-
break;
570
-
571
-
case OP_LBZ:
572
-
emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
573
-
break;
574
-
575
-
case OP_LBZU:
576
-
emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
577
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
578
-
break;
579
-
580
-
case OP_STW:
581
-
emulated = kvmppc_handle_store(run, vcpu,
582
-
kvmppc_get_gpr(vcpu, rs),
583
-
4, 1);
584
-
break;
585
-
586
-
case OP_STD:
587
-
rs = get_rs(inst);
588
-
switch (inst & 3) {
589
-
case 0: /* std */
590
-
emulated = kvmppc_handle_store(run, vcpu,
591
-
kvmppc_get_gpr(vcpu, rs), 8, 1);
592
378
break;
593
-
case 1: /* stdu */
594
-
emulated = kvmppc_handle_store(run, vcpu,
595
-
kvmppc_get_gpr(vcpu, rs), 8, 1);
596
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
597
-
break;
598
-
default:
599
-
emulated = EMULATE_FAIL;
600
379
}
601
-
break;
602
-
603
-
case OP_STWU:
604
-
emulated = kvmppc_handle_store(run, vcpu,
605
-
kvmppc_get_gpr(vcpu, rs), 4, 1);
606
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
607
-
break;
608
-
609
-
case OP_STB:
610
-
emulated = kvmppc_handle_store(run, vcpu,
611
-
kvmppc_get_gpr(vcpu, rs), 1, 1);
612
-
break;
613
-
614
-
case OP_STBU:
615
-
emulated = kvmppc_handle_store(run, vcpu,
616
-
kvmppc_get_gpr(vcpu, rs), 1, 1);
617
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
618
-
break;
619
-
620
-
case OP_LHZ:
621
-
emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
622
-
break;
623
-
624
-
case OP_LHZU:
625
-
emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
626
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
627
-
break;
628
-
629
-
case OP_LHA:
630
-
emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
631
-
break;
632
-
633
-
case OP_LHAU:
634
-
emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
635
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
636
-
break;
637
-
638
-
case OP_STH:
639
-
emulated = kvmppc_handle_store(run, vcpu,
640
-
kvmppc_get_gpr(vcpu, rs), 2, 1);
641
-
break;
642
-
643
-
case OP_STHU:
644
-
emulated = kvmppc_handle_store(run, vcpu,
645
-
kvmppc_get_gpr(vcpu, rs), 2, 1);
646
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
647
-
break;
648
-
649
-
#ifdef CONFIG_PPC_FPU
650
-
case OP_LFS:
651
-
if (kvmppc_check_fp_disabled(vcpu))
652
-
return EMULATE_DONE;
653
-
vcpu->arch.mmio_sp64_extend = 1;
654
-
emulated = kvmppc_handle_load(run, vcpu,
655
-
KVM_MMIO_REG_FPR|rt, 4, 1);
656
-
break;
657
-
658
-
case OP_LFSU:
659
-
if (kvmppc_check_fp_disabled(vcpu))
660
-
return EMULATE_DONE;
661
-
vcpu->arch.mmio_sp64_extend = 1;
662
-
emulated = kvmppc_handle_load(run, vcpu,
663
-
KVM_MMIO_REG_FPR|rt, 4, 1);
664
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
665
-
break;
666
-
667
-
case OP_LFD:
668
-
if (kvmppc_check_fp_disabled(vcpu))
669
-
return EMULATE_DONE;
670
-
emulated = kvmppc_handle_load(run, vcpu,
671
-
KVM_MMIO_REG_FPR|rt, 8, 1);
672
-
break;
673
-
674
-
case OP_LFDU:
675
-
if (kvmppc_check_fp_disabled(vcpu))
676
-
return EMULATE_DONE;
677
-
emulated = kvmppc_handle_load(run, vcpu,
678
-
KVM_MMIO_REG_FPR|rt, 8, 1);
679
-
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
680
-
break;
681
-
#endif
682
-
683
-
default:
684
-
emulated = EMULATE_FAIL;
685
-
break;
686
380
}
687
381
688
382
if (emulated == EMULATE_FAIL) {
+258
-61
arch/powerpc/kvm/powerpc.c
+258
-61
arch/powerpc/kvm/powerpc.c
···
648
648
#endif
649
649
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
650
650
case KVM_CAP_PPC_HTM:
651
-
r = hv_enabled &&
652
-
(!!(cur_cpu_spec->cpu_user_features2 & PPC_FEATURE2_HTM) ||
653
-
cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST));
651
+
r = !!(cur_cpu_spec->cpu_user_features2 & PPC_FEATURE2_HTM) ||
652
+
(hv_enabled && cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST));
654
653
break;
655
654
#endif
656
655
default:
···
906
907
}
907
908
}
908
909
910
+
static inline void kvmppc_set_vsr_word_dump(struct kvm_vcpu *vcpu,
911
+
u32 gpr)
912
+
{
913
+
union kvmppc_one_reg val;
914
+
int index = vcpu->arch.io_gpr & KVM_MMIO_REG_MASK;
915
+
916
+
if (vcpu->arch.mmio_vsx_tx_sx_enabled) {
917
+
val.vsx32val[0] = gpr;
918
+
val.vsx32val[1] = gpr;
919
+
val.vsx32val[2] = gpr;
920
+
val.vsx32val[3] = gpr;
921
+
VCPU_VSX_VR(vcpu, index) = val.vval;
922
+
} else {
923
+
val.vsx32val[0] = gpr;
924
+
val.vsx32val[1] = gpr;
925
+
VCPU_VSX_FPR(vcpu, index, 0) = val.vsxval[0];
926
+
VCPU_VSX_FPR(vcpu, index, 1) = val.vsxval[0];
927
+
}
928
+
}
929
+
909
930
static inline void kvmppc_set_vsr_word(struct kvm_vcpu *vcpu,
910
931
u32 gpr32)
911
932
{
···
952
933
#endif /* CONFIG_VSX */
953
934
954
935
#ifdef CONFIG_ALTIVEC
955
-
static inline void kvmppc_set_vmx_dword(struct kvm_vcpu *vcpu,
956
-
u64 gpr)
936
+
static inline int kvmppc_get_vmx_offset_generic(struct kvm_vcpu *vcpu,
937
+
int index, int element_size)
957
938
{
939
+
int offset;
940
+
int elts = sizeof(vector128)/element_size;
941
+
942
+
if ((index < 0) || (index >= elts))
943
+
return -1;
944
+
945
+
if (kvmppc_need_byteswap(vcpu))
946
+
offset = elts - index - 1;
947
+
else
948
+
offset = index;
949
+
950
+
return offset;
951
+
}
952
+
953
+
static inline int kvmppc_get_vmx_dword_offset(struct kvm_vcpu *vcpu,
954
+
int index)
955
+
{
956
+
return kvmppc_get_vmx_offset_generic(vcpu, index, 8);
957
+
}
958
+
959
+
static inline int kvmppc_get_vmx_word_offset(struct kvm_vcpu *vcpu,
960
+
int index)
961
+
{
962
+
return kvmppc_get_vmx_offset_generic(vcpu, index, 4);
963
+
}
964
+
965
+
static inline int kvmppc_get_vmx_hword_offset(struct kvm_vcpu *vcpu,
966
+
int index)
967
+
{
968
+
return kvmppc_get_vmx_offset_generic(vcpu, index, 2);
969
+
}
970
+
971
+
static inline int kvmppc_get_vmx_byte_offset(struct kvm_vcpu *vcpu,
972
+
int index)
973
+
{
974
+
return kvmppc_get_vmx_offset_generic(vcpu, index, 1);
975
+
}
976
+
977
+
978
+
static inline void kvmppc_set_vmx_dword(struct kvm_vcpu *vcpu,
979
+
u64 gpr)
980
+
{
981
+
union kvmppc_one_reg val;
982
+
int offset = kvmppc_get_vmx_dword_offset(vcpu,
983
+
vcpu->arch.mmio_vmx_offset);
958
984
int index = vcpu->arch.io_gpr & KVM_MMIO_REG_MASK;
959
-
u32 hi, lo;
960
-
u32 di;
961
985
962
-
#ifdef __BIG_ENDIAN
963
-
hi = gpr >> 32;
964
-
lo = gpr & 0xffffffff;
965
-
#else
966
-
lo = gpr >> 32;
967
-
hi = gpr & 0xffffffff;
968
-
#endif
969
-
970
-
di = 2 - vcpu->arch.mmio_vmx_copy_nums; /* doubleword index */
971
-
if (di > 1)
986
+
if (offset == -1)
972
987
return;
973
988
974
-
if (vcpu->arch.mmio_host_swabbed)
975
-
di = 1 - di;
989
+
val.vval = VCPU_VSX_VR(vcpu, index);
990
+
val.vsxval[offset] = gpr;
991
+
VCPU_VSX_VR(vcpu, index) = val.vval;
992
+
}
976
993
977
-
VCPU_VSX_VR(vcpu, index).u[di * 2] = hi;
978
-
VCPU_VSX_VR(vcpu, index).u[di * 2 + 1] = lo;
994
+
static inline void kvmppc_set_vmx_word(struct kvm_vcpu *vcpu,
995
+
u32 gpr32)
996
+
{
997
+
union kvmppc_one_reg val;
998
+
int offset = kvmppc_get_vmx_word_offset(vcpu,
999
+
vcpu->arch.mmio_vmx_offset);
1000
+
int index = vcpu->arch.io_gpr & KVM_MMIO_REG_MASK;
1001
+
1002
+
if (offset == -1)
1003
+
return;
1004
+
1005
+
val.vval = VCPU_VSX_VR(vcpu, index);
1006
+
val.vsx32val[offset] = gpr32;
1007
+
VCPU_VSX_VR(vcpu, index) = val.vval;
1008
+
}
1009
+
1010
+
static inline void kvmppc_set_vmx_hword(struct kvm_vcpu *vcpu,
1011
+
u16 gpr16)
1012
+
{
1013
+
union kvmppc_one_reg val;
1014
+
int offset = kvmppc_get_vmx_hword_offset(vcpu,
1015
+
vcpu->arch.mmio_vmx_offset);
1016
+
int index = vcpu->arch.io_gpr & KVM_MMIO_REG_MASK;
1017
+
1018
+
if (offset == -1)
1019
+
return;
1020
+
1021
+
val.vval = VCPU_VSX_VR(vcpu, index);
1022
+
val.vsx16val[offset] = gpr16;
1023
+
VCPU_VSX_VR(vcpu, index) = val.vval;
1024
+
}
1025
+
1026
+
static inline void kvmppc_set_vmx_byte(struct kvm_vcpu *vcpu,
1027
+
u8 gpr8)
1028
+
{
1029
+
union kvmppc_one_reg val;
1030
+
int offset = kvmppc_get_vmx_byte_offset(vcpu,
1031
+
vcpu->arch.mmio_vmx_offset);
1032
+
int index = vcpu->arch.io_gpr & KVM_MMIO_REG_MASK;
1033
+
1034
+
if (offset == -1)
1035
+
return;
1036
+
1037
+
val.vval = VCPU_VSX_VR(vcpu, index);
1038
+
val.vsx8val[offset] = gpr8;
1039
+
VCPU_VSX_VR(vcpu, index) = val.vval;
979
1040
}
980
1041
#endif /* CONFIG_ALTIVEC */
981
1042
···
1140
1041
kvmppc_set_gpr(vcpu, vcpu->arch.io_gpr, gpr);
1141
1042
break;
1142
1043
case KVM_MMIO_REG_FPR:
1044
+
if (vcpu->kvm->arch.kvm_ops->giveup_ext)
1045
+
vcpu->kvm->arch.kvm_ops->giveup_ext(vcpu, MSR_FP);
1046
+
1143
1047
VCPU_FPR(vcpu, vcpu->arch.io_gpr & KVM_MMIO_REG_MASK) = gpr;
1144
1048
break;
1145
1049
#ifdef CONFIG_PPC_BOOK3S
···
1156
1054
#endif
1157
1055
#ifdef CONFIG_VSX
1158
1056
case KVM_MMIO_REG_VSX:
1159
-
if (vcpu->arch.mmio_vsx_copy_type == KVMPPC_VSX_COPY_DWORD)
1057
+
if (vcpu->kvm->arch.kvm_ops->giveup_ext)
1058
+
vcpu->kvm->arch.kvm_ops->giveup_ext(vcpu, MSR_VSX);
1059
+
1060
+
if (vcpu->arch.mmio_copy_type == KVMPPC_VSX_COPY_DWORD)
1160
1061
kvmppc_set_vsr_dword(vcpu, gpr);
1161
-
else if (vcpu->arch.mmio_vsx_copy_type == KVMPPC_VSX_COPY_WORD)
1062
+
else if (vcpu->arch.mmio_copy_type == KVMPPC_VSX_COPY_WORD)
1162
1063
kvmppc_set_vsr_word(vcpu, gpr);
1163
-
else if (vcpu->arch.mmio_vsx_copy_type ==
1064
+
else if (vcpu->arch.mmio_copy_type ==
1164
1065
KVMPPC_VSX_COPY_DWORD_LOAD_DUMP)
1165
1066
kvmppc_set_vsr_dword_dump(vcpu, gpr);
1067
+
else if (vcpu->arch.mmio_copy_type ==
1068
+
KVMPPC_VSX_COPY_WORD_LOAD_DUMP)
1069
+
kvmppc_set_vsr_word_dump(vcpu, gpr);
1166
1070
break;
1167
1071
#endif
1168
1072
#ifdef CONFIG_ALTIVEC
1169
1073
case KVM_MMIO_REG_VMX:
1170
-
kvmppc_set_vmx_dword(vcpu, gpr);
1074
+
if (vcpu->kvm->arch.kvm_ops->giveup_ext)
1075
+
vcpu->kvm->arch.kvm_ops->giveup_ext(vcpu, MSR_VEC);
1076
+
1077
+
if (vcpu->arch.mmio_copy_type == KVMPPC_VMX_COPY_DWORD)
1078
+
kvmppc_set_vmx_dword(vcpu, gpr);
1079
+
else if (vcpu->arch.mmio_copy_type == KVMPPC_VMX_COPY_WORD)
1080
+
kvmppc_set_vmx_word(vcpu, gpr);
1081
+
else if (vcpu->arch.mmio_copy_type ==
1082
+
KVMPPC_VMX_COPY_HWORD)
1083
+
kvmppc_set_vmx_hword(vcpu, gpr);
1084
+
else if (vcpu->arch.mmio_copy_type ==
1085
+
KVMPPC_VMX_COPY_BYTE)
1086
+
kvmppc_set_vmx_byte(vcpu, gpr);
1171
1087
break;
1172
1088
#endif
1173
1089
default:
···
1348
1228
u32 dword_offset, word_offset;
1349
1229
union kvmppc_one_reg reg;
1350
1230
int vsx_offset = 0;
1351
-
int copy_type = vcpu->arch.mmio_vsx_copy_type;
1231
+
int copy_type = vcpu->arch.mmio_copy_type;
1352
1232
int result = 0;
1353
1233
1354
1234
switch (copy_type) {
···
1464
1344
#endif /* CONFIG_VSX */
1465
1345
1466
1346
#ifdef CONFIG_ALTIVEC
1467
-
/* handle quadword load access in two halves */
1468
-
int kvmppc_handle_load128_by2x64(struct kvm_run *run, struct kvm_vcpu *vcpu,
1469
-
unsigned int rt, int is_default_endian)
1347
+
int kvmppc_handle_vmx_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
1348
+
unsigned int rt, unsigned int bytes, int is_default_endian)
1470
1349
{
1471
1350
enum emulation_result emulated = EMULATE_DONE;
1472
1351
1352
+
if (vcpu->arch.mmio_vsx_copy_nums > 2)
1353
+
return EMULATE_FAIL;
1354
+
1473
1355
while (vcpu->arch.mmio_vmx_copy_nums) {
1474
-
emulated = __kvmppc_handle_load(run, vcpu, rt, 8,
1356
+
emulated = __kvmppc_handle_load(run, vcpu, rt, bytes,
1475
1357
is_default_endian, 0);
1476
1358
1477
1359
if (emulated != EMULATE_DONE)
···
1481
1359
1482
1360
vcpu->arch.paddr_accessed += run->mmio.len;
1483
1361
vcpu->arch.mmio_vmx_copy_nums--;
1362
+
vcpu->arch.mmio_vmx_offset++;
1484
1363
}
1485
1364
1486
1365
return emulated;
1487
1366
}
1488
1367
1489
-
static inline int kvmppc_get_vmx_data(struct kvm_vcpu *vcpu, int rs, u64 *val)
1368
+
int kvmppc_get_vmx_dword(struct kvm_vcpu *vcpu, int index, u64 *val)
1490
1369
{
1491
-
vector128 vrs = VCPU_VSX_VR(vcpu, rs);
1492
-
u32 di;
1493
-
u64 w0, w1;
1370
+
union kvmppc_one_reg reg;
1371
+
int vmx_offset = 0;
1372
+
int result = 0;
1494
1373
1495
-
di = 2 - vcpu->arch.mmio_vmx_copy_nums; /* doubleword index */
1496
-
if (di > 1)
1374
+
vmx_offset =
1375
+
kvmppc_get_vmx_dword_offset(vcpu, vcpu->arch.mmio_vmx_offset);
1376
+
1377
+
if (vmx_offset == -1)
1497
1378
return -1;
1498
1379
1499
-
if (vcpu->arch.mmio_host_swabbed)
1500
-
di = 1 - di;
1380
+
reg.vval = VCPU_VSX_VR(vcpu, index);
1381
+
*val = reg.vsxval[vmx_offset];
1501
1382
1502
-
w0 = vrs.u[di * 2];
1503
-
w1 = vrs.u[di * 2 + 1];
1504
-
1505
-
#ifdef __BIG_ENDIAN
1506
-
*val = (w0 << 32) | w1;
1507
-
#else
1508
-
*val = (w1 << 32) | w0;
1509
-
#endif
1510
-
return 0;
1383
+
return result;
1511
1384
}
1512
1385
1513
-
/* handle quadword store in two halves */
1514
-
int kvmppc_handle_store128_by2x64(struct kvm_run *run, struct kvm_vcpu *vcpu,
1515
-
unsigned int rs, int is_default_endian)
1386
+
int kvmppc_get_vmx_word(struct kvm_vcpu *vcpu, int index, u64 *val)
1387
+
{
1388
+
union kvmppc_one_reg reg;
1389
+
int vmx_offset = 0;
1390
+
int result = 0;
1391
+
1392
+
vmx_offset =
1393
+
kvmppc_get_vmx_word_offset(vcpu, vcpu->arch.mmio_vmx_offset);
1394
+
1395
+
if (vmx_offset == -1)
1396
+
return -1;
1397
+
1398
+
reg.vval = VCPU_VSX_VR(vcpu, index);
1399
+
*val = reg.vsx32val[vmx_offset];
1400
+
1401
+
return result;
1402
+
}
1403
+
1404
+
int kvmppc_get_vmx_hword(struct kvm_vcpu *vcpu, int index, u64 *val)
1405
+
{
1406
+
union kvmppc_one_reg reg;
1407
+
int vmx_offset = 0;
1408
+
int result = 0;
1409
+
1410
+
vmx_offset =
1411
+
kvmppc_get_vmx_hword_offset(vcpu, vcpu->arch.mmio_vmx_offset);
1412
+
1413
+
if (vmx_offset == -1)
1414
+
return -1;
1415
+
1416
+
reg.vval = VCPU_VSX_VR(vcpu, index);
1417
+
*val = reg.vsx16val[vmx_offset];
1418
+
1419
+
return result;
1420
+
}
1421
+
1422
+
int kvmppc_get_vmx_byte(struct kvm_vcpu *vcpu, int index, u64 *val)
1423
+
{
1424
+
union kvmppc_one_reg reg;
1425
+
int vmx_offset = 0;
1426
+
int result = 0;
1427
+
1428
+
vmx_offset =
1429
+
kvmppc_get_vmx_byte_offset(vcpu, vcpu->arch.mmio_vmx_offset);
1430
+
1431
+
if (vmx_offset == -1)
1432
+
return -1;
1433
+
1434
+
reg.vval = VCPU_VSX_VR(vcpu, index);
1435
+
*val = reg.vsx8val[vmx_offset];
1436
+
1437
+
return result;
1438
+
}
1439
+
1440
+
int kvmppc_handle_vmx_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
1441
+
unsigned int rs, unsigned int bytes, int is_default_endian)
1516
1442
{
1517
1443
u64 val = 0;
1444
+
unsigned int index = rs & KVM_MMIO_REG_MASK;
1518
1445
enum emulation_result emulated = EMULATE_DONE;
1446
+
1447
+
if (vcpu->arch.mmio_vsx_copy_nums > 2)
1448
+
return EMULATE_FAIL;
1519
1449
1520
1450
vcpu->arch.io_gpr = rs;
1521
1451
1522
1452
while (vcpu->arch.mmio_vmx_copy_nums) {
1523
-
if (kvmppc_get_vmx_data(vcpu, rs, &val) == -1)
1524
-
return EMULATE_FAIL;
1453
+
switch (vcpu->arch.mmio_copy_type) {
1454
+
case KVMPPC_VMX_COPY_DWORD:
1455
+
if (kvmppc_get_vmx_dword(vcpu, index, &val) == -1)
1456
+
return EMULATE_FAIL;
1525
1457
1526
-
emulated = kvmppc_handle_store(run, vcpu, val, 8,
1458
+
break;
1459
+
case KVMPPC_VMX_COPY_WORD:
1460
+
if (kvmppc_get_vmx_word(vcpu, index, &val) == -1)
1461
+
return EMULATE_FAIL;
1462
+
break;
1463
+
case KVMPPC_VMX_COPY_HWORD:
1464
+
if (kvmppc_get_vmx_hword(vcpu, index, &val) == -1)
1465
+
return EMULATE_FAIL;
1466
+
break;
1467
+
case KVMPPC_VMX_COPY_BYTE:
1468
+
if (kvmppc_get_vmx_byte(vcpu, index, &val) == -1)
1469
+
return EMULATE_FAIL;
1470
+
break;
1471
+
default:
1472
+
return EMULATE_FAIL;
1473
+
}
1474
+
1475
+
emulated = kvmppc_handle_store(run, vcpu, val, bytes,
1527
1476
is_default_endian);
1528
1477
if (emulated != EMULATE_DONE)
1529
1478
break;
1530
1479
1531
1480
vcpu->arch.paddr_accessed += run->mmio.len;
1532
1481
vcpu->arch.mmio_vmx_copy_nums--;
1482
+
vcpu->arch.mmio_vmx_offset++;
1533
1483
}
1534
1484
1535
1485
return emulated;
···
1616
1422
vcpu->arch.paddr_accessed += run->mmio.len;
1617
1423
1618
1424
if (!vcpu->mmio_is_write) {
1619
-
emulated = kvmppc_handle_load128_by2x64(run, vcpu,
1620
-
vcpu->arch.io_gpr, 1);
1425
+
emulated = kvmppc_handle_vmx_load(run, vcpu,
1426
+
vcpu->arch.io_gpr, run->mmio.len, 1);
1621
1427
} else {
1622
-
emulated = kvmppc_handle_store128_by2x64(run, vcpu,
1623
-
vcpu->arch.io_gpr, 1);
1428
+
emulated = kvmppc_handle_vmx_store(run, vcpu,
1429
+
vcpu->arch.io_gpr, run->mmio.len, 1);
1624
1430
}
1625
1431
1626
1432
switch (emulated) {
···
1764
1570
}
1765
1571
#endif
1766
1572
#ifdef CONFIG_ALTIVEC
1767
-
if (vcpu->arch.mmio_vmx_copy_nums > 0)
1573
+
if (vcpu->arch.mmio_vmx_copy_nums > 0) {
1768
1574
vcpu->arch.mmio_vmx_copy_nums--;
1575
+
vcpu->arch.mmio_vmx_offset++;
1576
+
}
1769
1577
1770
1578
if (vcpu->arch.mmio_vmx_copy_nums > 0) {
1771
1579
r = kvmppc_emulate_mmio_vmx_loadstore(vcpu, run);
···
1980
1784
void __user *argp = (void __user *)arg;
1981
1785
long r;
1982
1786
1983
-
vcpu_load(vcpu);
1984
-
1985
1787
switch (ioctl) {
1986
1788
case KVM_ENABLE_CAP:
1987
1789
{
1988
1790
struct kvm_enable_cap cap;
1989
1791
r = -EFAULT;
1792
+
vcpu_load(vcpu);
1990
1793
if (copy_from_user(&cap, argp, sizeof(cap)))
1991
1794
goto out;
1992
1795
r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
1796
+
vcpu_put(vcpu);
1993
1797
break;
1994
1798
}
1995
1799
···
2011
1815
case KVM_DIRTY_TLB: {
2012
1816
struct kvm_dirty_tlb dirty;
2013
1817
r = -EFAULT;
1818
+
vcpu_load(vcpu);
2014
1819
if (copy_from_user(&dirty, argp, sizeof(dirty)))
2015
1820
goto out;
2016
1821
r = kvm_vcpu_ioctl_dirty_tlb(vcpu, &dirty);
1822
+
vcpu_put(vcpu);
2017
1823
break;
2018
1824
}
2019
1825
#endif
···
2024
1826
}
2025
1827
2026
1828
out:
2027
-
vcpu_put(vcpu);
2028
1829
return r;
2029
1830
}
2030
1831
+384
arch/powerpc/kvm/tm.S
+384
arch/powerpc/kvm/tm.S
···
1
+
/*
2
+
* This program is free software; you can redistribute it and/or modify
3
+
* it under the terms of the GNU General Public License, version 2, as
4
+
* published by the Free Software Foundation.
5
+
*
6
+
* This program is distributed in the hope that it will be useful,
7
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
8
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9
+
* GNU General Public License for more details.
10
+
*
11
+
* Derived from book3s_hv_rmhandlers.S, which is:
12
+
*
13
+
* Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
14
+
*
15
+
*/
16
+
17
+
#include <asm/reg.h>
18
+
#include <asm/ppc_asm.h>
19
+
#include <asm/asm-offsets.h>
20
+
#include <asm/export.h>
21
+
#include <asm/tm.h>
22
+
#include <asm/cputable.h>
23
+
24
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
25
+
#define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
26
+
27
+
/*
28
+
* Save transactional state and TM-related registers.
29
+
* Called with:
30
+
* - r3 pointing to the vcpu struct
31
+
* - r4 points to the MSR with current TS bits:
32
+
* (For HV KVM, it is VCPU_MSR ; For PR KVM, it is host MSR).
33
+
* This can modify all checkpointed registers, but
34
+
* restores r1, r2 before exit.
35
+
*/
36
+
_GLOBAL(__kvmppc_save_tm)
37
+
mflr r0
38
+
std r0, PPC_LR_STKOFF(r1)
39
+
40
+
/* Turn on TM. */
41
+
mfmsr r8
42
+
li r0, 1
43
+
rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
44
+
ori r8, r8, MSR_FP
45
+
oris r8, r8, (MSR_VEC | MSR_VSX)@h
46
+
mtmsrd r8
47
+
48
+
rldicl. r4, r4, 64 - MSR_TS_S_LG, 62
49
+
beq 1f /* TM not active in guest. */
50
+
51
+
std r1, HSTATE_SCRATCH2(r13)
52
+
std r3, HSTATE_SCRATCH1(r13)
53
+
54
+
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
55
+
BEGIN_FTR_SECTION
56
+
/* Emulation of the treclaim instruction needs TEXASR before treclaim */
57
+
mfspr r6, SPRN_TEXASR
58
+
std r6, VCPU_ORIG_TEXASR(r3)
59
+
END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_HV_ASSIST)
60
+
#endif
61
+
62
+
/* Clear the MSR RI since r1, r13 are all going to be foobar. */
63
+
li r5, 0
64
+
mtmsrd r5, 1
65
+
66
+
li r3, TM_CAUSE_KVM_RESCHED
67
+
68
+
/* All GPRs are volatile at this point. */
69
+
TRECLAIM(R3)
70
+
71
+
/* Temporarily store r13 and r9 so we have some regs to play with */
72
+
SET_SCRATCH0(r13)
73
+
GET_PACA(r13)
74
+
std r9, PACATMSCRATCH(r13)
75
+
ld r9, HSTATE_SCRATCH1(r13)
76
+
77
+
/* Get a few more GPRs free. */
78
+
std r29, VCPU_GPRS_TM(29)(r9)
79
+
std r30, VCPU_GPRS_TM(30)(r9)
80
+
std r31, VCPU_GPRS_TM(31)(r9)
81
+
82
+
/* Save away PPR and DSCR soon so don't run with user values. */
83
+
mfspr r31, SPRN_PPR
84
+
HMT_MEDIUM
85
+
mfspr r30, SPRN_DSCR
86
+
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
87
+
ld r29, HSTATE_DSCR(r13)
88
+
mtspr SPRN_DSCR, r29
89
+
#endif
90
+
91
+
/* Save all but r9, r13 & r29-r31 */
92
+
reg = 0
93
+
.rept 29
94
+
.if (reg != 9) && (reg != 13)
95
+
std reg, VCPU_GPRS_TM(reg)(r9)
96
+
.endif
97
+
reg = reg + 1
98
+
.endr
99
+
/* ... now save r13 */
100
+
GET_SCRATCH0(r4)
101
+
std r4, VCPU_GPRS_TM(13)(r9)
102
+
/* ... and save r9 */
103
+
ld r4, PACATMSCRATCH(r13)
104
+
std r4, VCPU_GPRS_TM(9)(r9)
105
+
106
+
/* Reload stack pointer and TOC. */
107
+
ld r1, HSTATE_SCRATCH2(r13)
108
+
ld r2, PACATOC(r13)
109
+
110
+
/* Set MSR RI now we have r1 and r13 back. */
111
+
li r5, MSR_RI
112
+
mtmsrd r5, 1
113
+
114
+
/* Save away checkpinted SPRs. */
115
+
std r31, VCPU_PPR_TM(r9)
116
+
std r30, VCPU_DSCR_TM(r9)
117
+
mflr r5
118
+
mfcr r6
119
+
mfctr r7
120
+
mfspr r8, SPRN_AMR
121
+
mfspr r10, SPRN_TAR
122
+
mfxer r11
123
+
std r5, VCPU_LR_TM(r9)
124
+
stw r6, VCPU_CR_TM(r9)
125
+
std r7, VCPU_CTR_TM(r9)
126
+
std r8, VCPU_AMR_TM(r9)
127
+
std r10, VCPU_TAR_TM(r9)
128
+
std r11, VCPU_XER_TM(r9)
129
+
130
+
/* Restore r12 as trap number. */
131
+
lwz r12, VCPU_TRAP(r9)
132
+
133
+
/* Save FP/VSX. */
134
+
addi r3, r9, VCPU_FPRS_TM
135
+
bl store_fp_state
136
+
addi r3, r9, VCPU_VRS_TM
137
+
bl store_vr_state
138
+
mfspr r6, SPRN_VRSAVE
139
+
stw r6, VCPU_VRSAVE_TM(r9)
140
+
1:
141
+
/*
142
+
* We need to save these SPRs after the treclaim so that the software
143
+
* error code is recorded correctly in the TEXASR. Also the user may
144
+
* change these outside of a transaction, so they must always be
145
+
* context switched.
146
+
*/
147
+
mfspr r7, SPRN_TEXASR
148
+
std r7, VCPU_TEXASR(r9)
149
+
11:
150
+
mfspr r5, SPRN_TFHAR
151
+
mfspr r6, SPRN_TFIAR
152
+
std r5, VCPU_TFHAR(r9)
153
+
std r6, VCPU_TFIAR(r9)
154
+
155
+
ld r0, PPC_LR_STKOFF(r1)
156
+
mtlr r0
157
+
blr
158
+
159
+
/*
160
+
* _kvmppc_save_tm_pr() is a wrapper around __kvmppc_save_tm(), so that it can
161
+
* be invoked from C function by PR KVM only.
162
+
*/
163
+
_GLOBAL(_kvmppc_save_tm_pr)
164
+
mflr r5
165
+
std r5, PPC_LR_STKOFF(r1)
166
+
stdu r1, -SWITCH_FRAME_SIZE(r1)
167
+
SAVE_NVGPRS(r1)
168
+
169
+
/* save MSR since TM/math bits might be impacted
170
+
* by __kvmppc_save_tm().
171
+
*/
172
+
mfmsr r5
173
+
SAVE_GPR(5, r1)
174
+
175
+
/* also save DSCR/CR/TAR so that it can be recovered later */
176
+
mfspr r6, SPRN_DSCR
177
+
SAVE_GPR(6, r1)
178
+
179
+
mfcr r7
180
+
stw r7, _CCR(r1)
181
+
182
+
mfspr r8, SPRN_TAR
183
+
SAVE_GPR(8, r1)
184
+
185
+
bl __kvmppc_save_tm
186
+
187
+
REST_GPR(8, r1)
188
+
mtspr SPRN_TAR, r8
189
+
190
+
ld r7, _CCR(r1)
191
+
mtcr r7
192
+
193
+
REST_GPR(6, r1)
194
+
mtspr SPRN_DSCR, r6
195
+
196
+
/* need preserve current MSR's MSR_TS bits */
197
+
REST_GPR(5, r1)
198
+
mfmsr r6
199
+
rldicl r6, r6, 64 - MSR_TS_S_LG, 62
200
+
rldimi r5, r6, MSR_TS_S_LG, 63 - MSR_TS_T_LG
201
+
mtmsrd r5
202
+
203
+
REST_NVGPRS(r1)
204
+
addi r1, r1, SWITCH_FRAME_SIZE
205
+
ld r5, PPC_LR_STKOFF(r1)
206
+
mtlr r5
207
+
blr
208
+
209
+
EXPORT_SYMBOL_GPL(_kvmppc_save_tm_pr);
210
+
211
+
/*
212
+
* Restore transactional state and TM-related registers.
213
+
* Called with:
214
+
* - r3 pointing to the vcpu struct.
215
+
* - r4 is the guest MSR with desired TS bits:
216
+
* For HV KVM, it is VCPU_MSR
217
+
* For PR KVM, it is provided by caller
218
+
* This potentially modifies all checkpointed registers.
219
+
* It restores r1, r2 from the PACA.
220
+
*/
221
+
_GLOBAL(__kvmppc_restore_tm)
222
+
mflr r0
223
+
std r0, PPC_LR_STKOFF(r1)
224
+
225
+
/* Turn on TM/FP/VSX/VMX so we can restore them. */
226
+
mfmsr r5
227
+
li r6, MSR_TM >> 32
228
+
sldi r6, r6, 32
229
+
or r5, r5, r6
230
+
ori r5, r5, MSR_FP
231
+
oris r5, r5, (MSR_VEC | MSR_VSX)@h
232
+
mtmsrd r5
233
+
234
+
/*
235
+
* The user may change these outside of a transaction, so they must
236
+
* always be context switched.
237
+
*/
238
+
ld r5, VCPU_TFHAR(r3)
239
+
ld r6, VCPU_TFIAR(r3)
240
+
ld r7, VCPU_TEXASR(r3)
241
+
mtspr SPRN_TFHAR, r5
242
+
mtspr SPRN_TFIAR, r6
243
+
mtspr SPRN_TEXASR, r7
244
+
245
+
mr r5, r4
246
+
rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
247
+
beqlr /* TM not active in guest */
248
+
std r1, HSTATE_SCRATCH2(r13)
249
+
250
+
/* Make sure the failure summary is set, otherwise we'll program check
251
+
* when we trechkpt. It's possible that this might have been not set
252
+
* on a kvmppc_set_one_reg() call but we shouldn't let this crash the
253
+
* host.
254
+
*/
255
+
oris r7, r7, (TEXASR_FS)@h
256
+
mtspr SPRN_TEXASR, r7
257
+
258
+
/*
259
+
* We need to load up the checkpointed state for the guest.
260
+
* We need to do this early as it will blow away any GPRs, VSRs and
261
+
* some SPRs.
262
+
*/
263
+
264
+
mr r31, r3
265
+
addi r3, r31, VCPU_FPRS_TM
266
+
bl load_fp_state
267
+
addi r3, r31, VCPU_VRS_TM
268
+
bl load_vr_state
269
+
mr r3, r31
270
+
lwz r7, VCPU_VRSAVE_TM(r3)
271
+
mtspr SPRN_VRSAVE, r7
272
+
273
+
ld r5, VCPU_LR_TM(r3)
274
+
lwz r6, VCPU_CR_TM(r3)
275
+
ld r7, VCPU_CTR_TM(r3)
276
+
ld r8, VCPU_AMR_TM(r3)
277
+
ld r9, VCPU_TAR_TM(r3)
278
+
ld r10, VCPU_XER_TM(r3)
279
+
mtlr r5
280
+
mtcr r6
281
+
mtctr r7
282
+
mtspr SPRN_AMR, r8
283
+
mtspr SPRN_TAR, r9
284
+
mtxer r10
285
+
286
+
/*
287
+
* Load up PPR and DSCR values but don't put them in the actual SPRs
288
+
* till the last moment to avoid running with userspace PPR and DSCR for
289
+
* too long.
290
+
*/
291
+
ld r29, VCPU_DSCR_TM(r3)
292
+
ld r30, VCPU_PPR_TM(r3)
293
+
294
+
std r2, PACATMSCRATCH(r13) /* Save TOC */
295
+
296
+
/* Clear the MSR RI since r1, r13 are all going to be foobar. */
297
+
li r5, 0
298
+
mtmsrd r5, 1
299
+
300
+
/* Load GPRs r0-r28 */
301
+
reg = 0
302
+
.rept 29
303
+
ld reg, VCPU_GPRS_TM(reg)(r31)
304
+
reg = reg + 1
305
+
.endr
306
+
307
+
mtspr SPRN_DSCR, r29
308
+
mtspr SPRN_PPR, r30
309
+
310
+
/* Load final GPRs */
311
+
ld 29, VCPU_GPRS_TM(29)(r31)
312
+
ld 30, VCPU_GPRS_TM(30)(r31)
313
+
ld 31, VCPU_GPRS_TM(31)(r31)
314
+
315
+
/* TM checkpointed state is now setup. All GPRs are now volatile. */
316
+
TRECHKPT
317
+
318
+
/* Now let's get back the state we need. */
319
+
HMT_MEDIUM
320
+
GET_PACA(r13)
321
+
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
322
+
ld r29, HSTATE_DSCR(r13)
323
+
mtspr SPRN_DSCR, r29
324
+
#endif
325
+
ld r1, HSTATE_SCRATCH2(r13)
326
+
ld r2, PACATMSCRATCH(r13)
327
+
328
+
/* Set the MSR RI since we have our registers back. */
329
+
li r5, MSR_RI
330
+
mtmsrd r5, 1
331
+
ld r0, PPC_LR_STKOFF(r1)
332
+
mtlr r0
333
+
blr
334
+
335
+
/*
336
+
* _kvmppc_restore_tm_pr() is a wrapper around __kvmppc_restore_tm(), so that it
337
+
* can be invoked from C function by PR KVM only.
338
+
*/
339
+
_GLOBAL(_kvmppc_restore_tm_pr)
340
+
mflr r5
341
+
std r5, PPC_LR_STKOFF(r1)
342
+
stdu r1, -SWITCH_FRAME_SIZE(r1)
343
+
SAVE_NVGPRS(r1)
344
+
345
+
/* save MSR to avoid TM/math bits change */
346
+
mfmsr r5
347
+
SAVE_GPR(5, r1)
348
+
349
+
/* also save DSCR/CR/TAR so that it can be recovered later */
350
+
mfspr r6, SPRN_DSCR
351
+
SAVE_GPR(6, r1)
352
+
353
+
mfcr r7
354
+
stw r7, _CCR(r1)
355
+
356
+
mfspr r8, SPRN_TAR
357
+
SAVE_GPR(8, r1)
358
+
359
+
bl __kvmppc_restore_tm
360
+
361
+
REST_GPR(8, r1)
362
+
mtspr SPRN_TAR, r8
363
+
364
+
ld r7, _CCR(r1)
365
+
mtcr r7
366
+
367
+
REST_GPR(6, r1)
368
+
mtspr SPRN_DSCR, r6
369
+
370
+
/* need preserve current MSR's MSR_TS bits */
371
+
REST_GPR(5, r1)
372
+
mfmsr r6
373
+
rldicl r6, r6, 64 - MSR_TS_S_LG, 62
374
+
rldimi r5, r6, MSR_TS_S_LG, 63 - MSR_TS_T_LG
375
+
mtmsrd r5
376
+
377
+
REST_NVGPRS(r1)
378
+
addi r1, r1, SWITCH_FRAME_SIZE
379
+
ld r5, PPC_LR_STKOFF(r1)
380
+
mtlr r5
381
+
blr
382
+
383
+
EXPORT_SYMBOL_GPL(_kvmppc_restore_tm_pr);
384
+
#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
+2
-4
arch/x86/kvm/vmx.c
+2
-4
arch/x86/kvm/vmx.c
···
4429
4429
goto out_vmcs;
4430
4430
memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
4431
4431
4432
-
#if IS_ENABLED(CONFIG_HYPERV)
4433
-
if (static_branch_unlikely(&enable_evmcs) &&
4432
+
if (IS_ENABLED(CONFIG_HYPERV) &&
4433
+
static_branch_unlikely(&enable_evmcs) &&
4434
4434
(ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
4435
4435
struct hv_enlightened_vmcs *evmcs =
4436
4436
(struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
4437
4437
4438
4438
evmcs->hv_enlightenments_control.msr_bitmap = 1;
4439
4439
}
4440
-
#endif
4441
-
4442
4440
}
4443
4441
return 0;
4444
4442
+1
-1
arch/x86/kvm/x86.c
+1
-1
arch/x86/kvm/x86.c
···
8567
8567
/*
8568
8568
* Make sure the user can only configure tsc_khz values that
8569
8569
* fit into a signed integer.
8570
-
* A min value is not calculated needed because it will always
8570
+
* A min value is not calculated because it will always
8571
8571
* be 1 on all machines.
8572
8572
*/
8573
8573
u64 max = min(0x7fffffffULL,